Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65919581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32140022

1

T14

15

T26

4046

T27

601

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14728624	1			T14	20		T26	1785		T27	762
values[0x0]	40440675	1			T14	9		T26	1141		T27	72
values[0x1]	42890304	1			T14	11		T26	1121		T27	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56059464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42000139

1

T14

21

T26

4046

T27

721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	343661	1			T26	14		T27	7		T28	1
valid_sources[0x01]	610575	1			T26	15		T27	2		T31	6
valid_sources[0x02]	320093	1			T26	19		T27	2		T29	1
valid_sources[0x03]	314036	1			T26	17		T27	6		T28	1
valid_sources[0x04]	312437	1			T26	13		T27	7		T28	1
valid_sources[0x05]	315322	1			T26	21		T27	1		T31	6
valid_sources[0x06]	320464	1			T26	14		T27	6		T28	1
valid_sources[0x07]	565761	1			T26	14		T27	5		T28	1
valid_sources[0x08]	320747	1			T26	13		T27	4		T29	1
valid_sources[0x09]	319404	1			T26	15		T27	3		T31	3
valid_sources[0x0a]	316175	1			T26	18		T27	3		T29	3
valid_sources[0x0b]	762207	1			T26	22		T27	6		T29	1
valid_sources[0x0c]	339484	1			T26	19		T27	5		T28	1
valid_sources[0x0d]	747408	1			T26	19		T27	1		T29	2
valid_sources[0x0e]	315575	1			T26	16		T27	1		T29	2
valid_sources[0x0f]	314545	1			T26	14		T27	2		T29	1
valid_sources[0x10]	819379	1			T26	15		T27	2		T31	2
valid_sources[0x11]	701651	1			T26	17		T27	2		T28	1
valid_sources[0x12]	323951	1			T26	19		T27	5		T29	3
valid_sources[0x13]	319324	1			T26	16		T27	2		T31	3
valid_sources[0x14]	315726	1			T26	19		T28	1		T31	10
valid_sources[0x15]	678042	1			T26	15		T27	2		T28	1
valid_sources[0x16]	319682	1			T26	17		T27	6		T29	2
valid_sources[0x17]	307421	1			T26	17		T27	3		T31	7
valid_sources[0x18]	316619	1			T26	17		T27	2		T31	9
valid_sources[0x19]	324237	1			T26	17		T27	2		T29	3
valid_sources[0x1a]	329401	1			T26	15		T27	4		T31	7
valid_sources[0x1b]	323680	1			T26	16		T28	1		T31	8
valid_sources[0x1c]	325280	1			T26	11		T27	7		T31	6
valid_sources[0x1d]	320341	1			T26	22		T27	3		T29	2
valid_sources[0x1e]	317820	1			T26	10		T27	6		T28	2
valid_sources[0x1f]	797517	1			T26	16		T27	3		T28	1
valid_sources[0x20]	329938	1			T26	13		T27	3		T28	2
valid_sources[0x21]	317049	1			T26	20		T27	2		T31	5
valid_sources[0x22]	319263	1			T26	20		T27	6		T28	1
valid_sources[0x23]	735207	1			T26	20		T27	2		T28	2
valid_sources[0x24]	317832	1			T26	17		T27	6		T31	9
valid_sources[0x25]	327091	1			T26	21		T27	3		T28	3
valid_sources[0x26]	553614	1			T26	19		T27	4		T29	3
valid_sources[0x27]	315004	1			T26	16		T27	4		T29	2
valid_sources[0x28]	319918	1			T26	14		T27	4		T28	2
valid_sources[0x29]	788912	1			T26	14		T27	4		T31	4
valid_sources[0x2a]	323615	1			T26	17		T27	3		T29	5
valid_sources[0x2b]	322982	1			T26	19		T27	6		T31	5
valid_sources[0x2c]	310401	1			T26	17		T27	6		T29	1
valid_sources[0x2d]	342910	1			T26	17		T27	3		T31	4
valid_sources[0x2e]	315842	1			T26	14		T27	3		T28	1
valid_sources[0x2f]	357741	1			T26	18		T27	2		T28	1
valid_sources[0x30]	328889	1			T26	26		T28	5		T29	1
valid_sources[0x31]	824589	1			T26	10		T27	1		T29	1
valid_sources[0x32]	575764	1			T26	20		T27	6		T29	1
valid_sources[0x33]	313197	1			T26	14		T27	4		T29	1
valid_sources[0x34]	317133	1			T26	11		T27	1		T29	2
valid_sources[0x35]	717780	1			T26	21		T27	6		T28	1
valid_sources[0x36]	316832	1			T26	19		T27	7		T31	6
valid_sources[0x37]	321936	1			T26	10		T27	3		T31	8
valid_sources[0x38]	343731	1			T26	11		T27	8		T31	7
valid_sources[0x39]	597975	1			T26	15		T27	5		T28	1
valid_sources[0x3a]	329855	1			T26	13		T27	3		T28	2
valid_sources[0x3b]	624845	1			T26	23		T27	3		T28	1
valid_sources[0x3c]	316633	1			T26	12		T27	5		T29	1
valid_sources[0x3d]	327307	1			T26	18		T27	4		T29	2
valid_sources[0x3e]	310030	1			T26	24		T27	4		T29	2
valid_sources[0x3f]	310851	1			T26	13		T27	1		T28	1
valid_sources[0x40]	319237	1			T26	22		T27	5		T28	1
valid_sources[0x41]	314130	1			T26	13		T27	10		T28	2
valid_sources[0x42]	316539	1			T26	9		T27	3		T31	5
valid_sources[0x43]	321070	1			T26	10		T27	5		T29	3
valid_sources[0x44]	334100	1			T26	12		T27	1		T31	4
valid_sources[0x45]	801656	1			T26	17		T27	2		T28	1
valid_sources[0x46]	319509	1			T26	15		T27	5		T28	1
valid_sources[0x47]	315307	1			T26	15		T27	5		T29	1
valid_sources[0x48]	551447	1			T26	20		T27	5		T29	1
valid_sources[0x49]	325298	1			T26	16		T27	4		T29	1
valid_sources[0x4a]	324856	1			T26	10		T27	2		T29	1
valid_sources[0x4b]	323326	1			T26	17		T27	3		T31	3
valid_sources[0x4c]	672807	1			T26	10		T27	4		T28	1
valid_sources[0x4d]	310840	1			T26	17		T27	4		T29	4
valid_sources[0x4e]	322040	1			T26	17		T27	4		T28	2
valid_sources[0x4f]	786164	1			T26	19		T27	4		T28	1
valid_sources[0x50]	329329	1			T26	19		T27	2		T28	1
valid_sources[0x51]	319421	1			T26	13		T27	7		T31	2
valid_sources[0x52]	310820	1			T26	12		T27	4		T28	2
valid_sources[0x53]	322223	1			T26	11		T27	2		T29	1
valid_sources[0x54]	690136	1			T26	25		T27	2		T28	1
valid_sources[0x55]	317800	1			T26	21		T27	3		T31	4
valid_sources[0x56]	321632	1			T26	16		T27	4		T29	4
valid_sources[0x57]	566487	1			T26	16		T27	4		T31	9
valid_sources[0x58]	330429	1			T26	11		T27	5		T28	1
valid_sources[0x59]	314961	1			T26	17		T27	3		T29	1
valid_sources[0x5a]	321799	1			T26	15		T27	2		T31	8
valid_sources[0x5b]	320856	1			T26	13		T27	2		T28	1
valid_sources[0x5c]	315796	1			T26	12		T27	3		T28	2
valid_sources[0x5d]	316428	1			T26	14		T27	7		T28	1
valid_sources[0x5e]	319568	1			T26	10		T27	2		T28	1
valid_sources[0x5f]	319614	1			T26	15		T27	2		T28	3
valid_sources[0x60]	315750	1			T26	10		T27	4		T28	1
valid_sources[0x61]	313420	1			T26	17		T27	2		T29	3
valid_sources[0x62]	787256	1			T26	16		T27	2		T28	1
valid_sources[0x63]	322964	1			T26	15		T27	3		T28	4
valid_sources[0x64]	319789	1			T26	21		T27	6		T28	1
valid_sources[0x65]	321220	1			T26	17		T27	6		T31	6
valid_sources[0x66]	316636	1			T26	11		T27	5		T31	7
valid_sources[0x67]	535228	1			T26	24		T27	1		T29	1
valid_sources[0x68]	330108	1			T26	11		T27	2		T28	2
valid_sources[0x69]	319484	1			T26	10		T27	7		T28	1
valid_sources[0x6a]	332853	1			T26	19		T27	1		T29	5
valid_sources[0x6b]	309970	1			T26	19		T27	1		T29	2
valid_sources[0x6c]	320980	1			T26	10		T27	8		T29	1
valid_sources[0x6d]	314815	1			T26	15		T27	5		T28	1
valid_sources[0x6e]	314289	1			T26	12		T27	3		T31	7
valid_sources[0x6f]	323681	1			T26	19		T27	4		T28	1
valid_sources[0x70]	693832	1			T26	7		T27	1		T28	1
valid_sources[0x71]	323340	1			T26	15		T27	10		T29	2
valid_sources[0x72]	327343	1			T26	22		T27	2		T28	3
valid_sources[0x73]	328949	1			T26	23		T27	4		T29	1
valid_sources[0x74]	314578	1			T26	14		T27	5		T31	2
valid_sources[0x75]	320293	1			T26	20		T27	1		T28	1
valid_sources[0x76]	313087	1			T26	21		T27	5		T28	1
valid_sources[0x77]	311410	1			T26	21		T27	4		T31	8
valid_sources[0x78]	310728	1			T26	15		T27	5		T29	1
valid_sources[0x79]	319867	1			T26	21		T27	5		T29	1
valid_sources[0x7a]	313269	1			T26	11		T27	6		T28	1
valid_sources[0x7b]	320597	1			T26	21		T27	2		T29	2
valid_sources[0x7c]	322997	1			T26	13		T27	2		T28	1
valid_sources[0x7d]	314651	1			T26	15		T27	4		T31	6
valid_sources[0x7e]	322309	1			T26	9		T27	4		T29	3
valid_sources[0x7f]	319752	1			T26	8		T27	4		T28	2
valid_sources[0x80]	316471	1			T26	14		T27	2		T28	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7372713

1

T14

11

T26

1784

T27

427

values[0x0]

all_enables

biggest_size

15587443

1

T14

3

T26

1141

T27

72

values[0x1]

all_enables

biggest_size

9179866

1

T14

1

T26

1121

T27

102