Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T194,T195
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T20

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11627	0	0
DisabledNoTrigBkwd_A	2147483647	734391	0	0
DisabledNoTrigFwd_A	2147483647	1830853781	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11627	0	0
T11	49947	0	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T79	344773	0	0	0
T193	1784	984	0	0
T194	805	107	0	0
T195	0	612	0	0
T196	0	288	0	0
T197	0	454	0	0
T198	0	1082	0	0
T199	0	424	0	0
T200	0	642	0	0
T201	0	531	0	0
T202	0	267	0	0
T203	0	260	0	0
T204	1269	551	0	0
T205	0	506	0	0
T206	0	185	0	0
T207	0	415	0	0
T208	0	1085	0	0
T209	0	430	0	0
T210	0	848	0	0
T211	0	913	0	0
T212	0	1043	0	0
T213	18824	0	0	0
T214	979184	0	0	0
T215	218458	0	0	0
T216	371387	0	0	0
T217	31763	0	0	0
T218	11984	0	0	0
T219	178168	0	0	0
T220	138266	0	0	0
T221	95780	0	0	0
T222	120594	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	734391	0	0
T1	385200	348	0	0
T2	4383	0	0	0
T3	1379476	1743	0	0
T4	946824	0	0	0
T5	2376416	1057	0	0
T6	68196	0	0	0
T7	0	670	0	0
T15	0	15	0	0
T16	0	423	0	0
T17	0	826	0	0
T18	0	3309	0	0
T20	480864	86	0	0
T21	50264	7	0	0
T22	61116	35	0	0
T23	181444	1	0	0
T24	24689	14	0	0
T25	23230	0	0	0
T35	0	371	0	0
T40	0	4	0	0
T56	0	214	0	0
T57	0	14	0	0
T58	0	382	0	0
T59	0	30	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830853781	0	0
T1	513600	1173487	0	0
T2	5844	4800	0	0
T3	1379476	1040580	0	0
T4	946824	709684	0	0
T5	2376416	1782933	0	0
T6	68196	13034	0	0
T20	480864	363663	0	0
T21	50264	27543	0	0
T22	61116	28305	0	0
T23	181444	141395	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T209,T212
1	1	Covered	T1,T2,T20

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	802478565	2024	0	0
DisabledNoTrigBkwd_A	802478565	212414	0	0
DisabledNoTrigFwd_A	802478565	412605817	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	2024	0	0
T204	1269	551	0	0
T209	0	430	0	0
T212	0	1043	0	0
T214	979184	0	0	0
T215	218458	0	0	0
T216	371387	0	0	0
T217	31763	0	0	0
T218	11984	0	0	0
T219	178168	0	0	0
T220	138266	0	0	0
T221	95780	0	0	0
T222	120594	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	212414	0	0
T1	128400	310	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	2	0	0
T6	17049	0	0	0
T15	0	2	0	0
T20	120216	86	0	0
T21	12566	2	0	0
T22	15279	11	0	0
T23	45361	1	0	0
T24	0	14	0	0
T56	0	81	0	0
T58	0	132	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	412605817	0	0
T1	128400	20142	0	0
T2	1461	582	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	592913	0	0
T6	17049	3229	0	0
T20	120216	3228	0	0
T21	12566	3134	0	0
T22	15279	3012	0	0
T23	45361	16557	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T197,T198
1	1	Covered	T1,T4,T6

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	802478565	4651	0	0
DisabledNoTrigBkwd_A	802478565	186613	0	0
DisabledNoTrigFwd_A	802478565	473551167	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	4651	0	0
T11	49947	0	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T79	344773	0	0	0
T193	1784	984	0	0
T197	0	454	0	0
T198	0	1082	0	0
T200	0	642	0	0
T201	0	531	0	0
T202	0	267	0	0
T205	0	506	0	0
T206	0	185	0	0
T213	18824	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	186613	0	0
T1	128400	19	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	670	0	0
T15	0	1	0	0
T17	0	3	0	0
T18	0	4	0	0
T20	120216	0	0	0
T21	12566	2	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T35	0	3	0	0
T57	0	5	0	0
T58	0	169	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	473551167	0	0
T1	128400	127096	0	0
T2	1461	1406	0	0
T3	344869	344859	0	0
T4	236706	2020	0	0
T5	594104	594019	0	0
T6	17049	3240	0	0
T20	120216	120145	0	0
T21	12566	5948	0	0
T22	15279	9490	0	0
T23	45361	45296	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T203,T208
1	1	Covered	T1,T3,T5

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	802478565	2365	0	0
DisabledNoTrigBkwd_A	802478565	167547	0	0
DisabledNoTrigFwd_A	802478565	448927312	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	2365	0	0
T66	194904	0	0	0
T98	613037	0	0	0
T118	360893	0	0	0
T194	805	107	0	0
T203	0	260	0	0
T208	0	1085	0	0
T211	0	913	0	0
T223	60593	0	0	0
T224	151927	0	0	0
T225	26125	0	0	0
T226	83616	0	0	0
T227	199364	0	0	0
T228	6702	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	167547	0	0
T3	344869	6	0	0
T4	236706	0	0	0
T5	594104	1055	0	0
T6	17049	0	0	0
T15	0	12	0	0
T16	0	423	0	0
T17	0	2	0	0
T18	0	1747	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	23	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	0	364	0	0
T56	0	5	0	0
T57	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	448927312	0	0
T1	128400	128216	0	0
T2	1461	1406	0	0
T3	344869	343449	0	0
T4	236706	236696	0	0
T5	594104	1982	0	0
T6	17049	3269	0	0
T20	120216	120145	0	0
T21	12566	12509	0	0
T22	15279	590	0	0
T23	45361	34246	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T196,T199
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	802478565	2587	0	0
DisabledNoTrigBkwd_A	802478565	167817	0	0
DisabledNoTrigFwd_A	802478565	495769485	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	2587	0	0
T70	31052	0	0	0
T103	12023	0	0	0
T195	1896	612	0	0
T196	1049	288	0	0
T199	2716	424	0	0
T207	0	415	0	0
T210	0	848	0	0
T229	261339	0	0	0
T230	26872	0	0	0
T231	58600	0	0	0
T232	54530	0	0	0
T233	164586	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	167817	0	0
T1	128400	19	0	0
T2	1461	0	0	0
T3	344869	1737	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T17	0	821	0	0
T18	0	1558	0	0
T20	120216	0	0	0
T21	12566	3	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	4	0	0
T40	0	4	0	0
T56	0	128	0	0
T58	0	81	0	0
T59	0	30	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	495769485	0	0
T1	128400	898033	0	0
T2	1461	1406	0	0
T3	344869	7413	0	0
T4	236706	234272	0	0
T5	594104	594019	0	0
T6	17049	3296	0	0
T20	120216	120145	0	0
T21	12566	5952	0	0
T22	15279	15213	0	0
T23	45361	45296	0	0