Module Definition
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Module : alert_handler_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 96.75 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_wrap.u_reg 99.19 100.00 96.75 100.00 100.00

Line Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
TOTAL22282228100.00
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CONT_ASSIGN1693811100.00
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CONT_ASSIGN1694111100.00
CONT_ASSIGN1694211100.00
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CONT_ASSIGN1694511100.00
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CONT_ASSIGN1694711100.00
CONT_ASSIGN1694911100.00
CONT_ASSIGN1695011100.00
CONT_ASSIGN1695111100.00
CONT_ASSIGN1695311100.00
CONT_ASSIGN1695411100.00
CONT_ASSIGN1695511100.00
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CONT_ASSIGN1697011100.00
CONT_ASSIGN1697111100.00
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CONT_ASSIGN1699011100.00
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CONT_ASSIGN1700111100.00
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CONT_ASSIGN1702911100.00
CONT_ASSIGN1703011100.00
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CONT_ASSIGN1703311100.00
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CONT_ASSIGN1706011100.00
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CONT_ASSIGN1706411100.00
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CONT_ASSIGN1707011100.00
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CONT_ASSIGN1707511100.00
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CONT_ASSIGN1707911100.00
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CONT_ASSIGN1708411100.00
CONT_ASSIGN1708511100.00
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CONT_ASSIGN1709011100.00
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CONT_ASSIGN1709411100.00
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CONT_ASSIGN1713011100.00
CONT_ASSIGN1713211100.00
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CONT_ASSIGN1714111100.00
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CONT_ASSIGN1715011100.00
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CONT_ASSIGN1719211100.00
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CONT_ASSIGN1721111100.00
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CONT_ASSIGN1737511100.00
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CONT_ASSIGN1741011100.00
CONT_ASSIGN1741211100.00
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CONT_ASSIGN1742111100.00
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CONT_ASSIGN1743011100.00
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CONT_ASSIGN1744011100.00
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CONT_ASSIGN1745011100.00
CONT_ASSIGN1745111100.00
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CONT_ASSIGN1745311100.00
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CONT_ASSIGN1746111100.00
CONT_ASSIGN1746311100.00
CONT_ASSIGN1746511100.00
CONT_ASSIGN1746711100.00
CONT_ASSIGN1746911100.00
CONT_ASSIGN1747111100.00
CONT_ASSIGN1747311100.00
CONT_ASSIGN1747511100.00
CONT_ASSIGN1747711100.00
CONT_ASSIGN1747811100.00
CONT_ASSIGN1748011100.00
CONT_ASSIGN1748111100.00
CONT_ASSIGN1748211100.00
CONT_ASSIGN1748411100.00
CONT_ASSIGN1748511100.00
CONT_ASSIGN1748611100.00
CONT_ASSIGN1748711100.00
CONT_ASSIGN1748911100.00
CONT_ASSIGN1749011100.00
CONT_ASSIGN1749111100.00
CONT_ASSIGN1749311100.00
CONT_ASSIGN1749411100.00
CONT_ASSIGN1749511100.00
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CONT_ASSIGN1749811100.00
CONT_ASSIGN1749911100.00
CONT_ASSIGN1750111100.00
CONT_ASSIGN1750211100.00
CONT_ASSIGN1750311100.00
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CONT_ASSIGN1750711100.00
CONT_ASSIGN1750911100.00
CONT_ASSIGN1751011100.00
CONT_ASSIGN1751111100.00
CONT_ASSIGN1751311100.00
CONT_ASSIGN1751411100.00
CONT_ASSIGN1751511100.00
CONT_ASSIGN1751611100.00
CONT_ASSIGN1751811100.00
CONT_ASSIGN1751911100.00
CONT_ASSIGN1752011100.00
CONT_ASSIGN1752211100.00
CONT_ASSIGN1752411100.00
CONT_ASSIGN1752611100.00
CONT_ASSIGN1752811100.00
CONT_ASSIGN1753011100.00
CONT_ASSIGN1753211100.00
CONT_ASSIGN1753411100.00
CONT_ASSIGN1753611100.00
CONT_ASSIGN1753811100.00
CONT_ASSIGN1754011100.00
CONT_ASSIGN1754111100.00
CONT_ASSIGN1754311100.00
CONT_ASSIGN1754411100.00
CONT_ASSIGN1754511100.00
CONT_ASSIGN1754711100.00
CONT_ASSIGN1754811100.00
CONT_ASSIGN1754911100.00
CONT_ASSIGN1755011100.00
CONT_ASSIGN1755211100.00
CONT_ASSIGN1755311100.00
CONT_ASSIGN1755411100.00
CONT_ASSIGN1755611100.00
CONT_ASSIGN1755711100.00
CONT_ASSIGN1755811100.00
CONT_ASSIGN1756011100.00
CONT_ASSIGN1756111100.00
CONT_ASSIGN1756211100.00
CONT_ASSIGN1756411100.00
CONT_ASSIGN1756511100.00
CONT_ASSIGN1756611100.00
CONT_ASSIGN1756811100.00
CONT_ASSIGN1756911100.00
CONT_ASSIGN1757011100.00
CONT_ASSIGN1757211100.00
CONT_ASSIGN1757311100.00
CONT_ASSIGN1757411100.00
CONT_ASSIGN1757611100.00
CONT_ASSIGN1757711100.00
CONT_ASSIGN1757811100.00
ALWAYS17582351351100.00
ALWAYS17937397397100.00
ALWAYS1939533100.00
ALWAYS1940333100.00
CONT_ASSIGN1941111100.00
CONT_ASSIGN1941411100.00
CONT_ASSIGN1963411100.00
CONT_ASSIGN1985611100.00
CONT_ASSIGN1986411100.00
CONT_ASSIGN1986511100.00

Click here to see the source line report.

Cond Coverage for Module : alert_handler_reg_top
TotalCoveredPercent
Conditions4802464696.75
Logical4802464696.75
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
65-9081100.00
9122-15663100.00
15664-15833100.00
15834-15927100.00
15927100.00
15927100.00
15927-1637399.49
16376-1662693.69
16627-1683890.33
16839-1705890.57
17061-1735297.55
17355-1941189.58

Branch Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
Branches 360 360 100.00
TERNARY 15923 2 2 100.00
IF 75 3 3 100.00
CASE 17938 351 351 100.00
IF 19395 2 2 100.00
IF 19403 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 15923 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T14,T26,T27
0 Covered T14,T26,T27


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T14,T26,T27
0 1 Covered T28,T29,T30
0 0 Covered T14,T26,T27


LineNo. Expression -1-: 17938 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T14,T26,T27
addr_hit[1] Covered T14,T26,T27
addr_hit[2] Covered T14,T26,T27
addr_hit[3] Covered T14,T26,T27
addr_hit[4] Covered T14,T26,T27
addr_hit[5] Covered T14,T26,T27
addr_hit[6] Covered T14,T26,T27
addr_hit[7] Covered T14,T26,T27
addr_hit[8] Covered T14,T26,T27
addr_hit[9] Covered T14,T26,T27
addr_hit[10] Covered T14,T26,T27
addr_hit[11] Covered T14,T26,T27
addr_hit[12] Covered T14,T26,T27
addr_hit[13] Covered T14,T26,T27
addr_hit[14] Covered T14,T26,T27
addr_hit[15] Covered T14,T26,T27
addr_hit[16] Covered T14,T26,T27
addr_hit[17] Covered T14,T26,T27
addr_hit[18] Covered T14,T26,T27
addr_hit[19] Covered T14,T26,T27
addr_hit[20] Covered T14,T26,T27
addr_hit[21] Covered T14,T26,T27
addr_hit[22] Covered T14,T26,T27
addr_hit[23] Covered T14,T26,T27
addr_hit[24] Covered T14,T26,T27
addr_hit[25] Covered T14,T26,T27
addr_hit[26] Covered T14,T26,T27
addr_hit[27] Covered T14,T26,T27
addr_hit[28] Covered T14,T26,T27
addr_hit[29] Covered T14,T26,T27
addr_hit[30] Covered T14,T26,T27
addr_hit[31] Covered T14,T26,T27
addr_hit[32] Covered T14,T26,T27
addr_hit[33] Covered T14,T26,T27
addr_hit[34] Covered T14,T26,T27
addr_hit[35] Covered T14,T26,T27
addr_hit[36] Covered T14,T26,T27
addr_hit[37] Covered T14,T26,T27
addr_hit[38] Covered T14,T26,T27
addr_hit[39] Covered T14,T26,T27
addr_hit[40] Covered T14,T26,T27
addr_hit[41] Covered T14,T26,T27
addr_hit[42] Covered T14,T26,T27
addr_hit[43] Covered T14,T26,T27
addr_hit[44] Covered T14,T26,T27
addr_hit[45] Covered T14,T26,T27
addr_hit[46] Covered T14,T26,T27
addr_hit[47] Covered T14,T26,T27
addr_hit[48] Covered T14,T26,T27
addr_hit[49] Covered T14,T26,T27
addr_hit[50] Covered T14,T26,T27
addr_hit[51] Covered T14,T26,T27
addr_hit[52] Covered T14,T26,T27
addr_hit[53] Covered T14,T26,T27
addr_hit[54] Covered T14,T26,T27
addr_hit[55] Covered T14,T26,T27
addr_hit[56] Covered T14,T26,T27
addr_hit[57] Covered T14,T26,T27
addr_hit[58] Covered T14,T26,T27
addr_hit[59] Covered T14,T26,T27
addr_hit[60] Covered T14,T26,T27
addr_hit[61] Covered T14,T26,T27
addr_hit[62] Covered T14,T26,T27
addr_hit[63] Covered T14,T26,T27
addr_hit[64] Covered T14,T26,T27
addr_hit[65] Covered T14,T26,T27
addr_hit[66] Covered T14,T26,T27
addr_hit[67] Covered T14,T26,T27
addr_hit[68] Covered T14,T26,T27
addr_hit[69] Covered T14,T26,T27
addr_hit[70] Covered T14,T26,T27
addr_hit[71] Covered T14,T26,T27
addr_hit[72] Covered T14,T26,T27
addr_hit[73] Covered T14,T26,T27
addr_hit[74] Covered T14,T26,T27
addr_hit[75] Covered T14,T26,T27
addr_hit[76] Covered T14,T26,T27
addr_hit[77] Covered T14,T26,T27
addr_hit[78] Covered T14,T26,T27
addr_hit[79] Covered T14,T26,T27
addr_hit[80] Covered T14,T26,T27
addr_hit[81] Covered T14,T26,T27
addr_hit[82] Covered T14,T26,T27
addr_hit[83] Covered T14,T26,T27
addr_hit[84] Covered T14,T26,T27
addr_hit[85] Covered T14,T26,T27
addr_hit[86] Covered T14,T26,T27
addr_hit[87] Covered T14,T26,T27
addr_hit[88] Covered T14,T26,T27
addr_hit[89] Covered T14,T26,T27
addr_hit[90] Covered T14,T26,T27
addr_hit[91] Covered T14,T26,T27
addr_hit[92] Covered T14,T26,T27
addr_hit[93] Covered T14,T26,T27
addr_hit[94] Covered T14,T26,T27
addr_hit[95] Covered T14,T26,T27
addr_hit[96] Covered T14,T26,T27
addr_hit[97] Covered T14,T26,T27
addr_hit[98] Covered T14,T26,T27
addr_hit[99] Covered T14,T26,T27
addr_hit[100] Covered T14,T26,T27
addr_hit[101] Covered T14,T26,T27
addr_hit[102] Covered T14,T26,T27
addr_hit[103] Covered T14,T26,T27
addr_hit[104] Covered T14,T26,T27
addr_hit[105] Covered T14,T26,T27
addr_hit[106] Covered T14,T26,T27
addr_hit[107] Covered T14,T26,T27
addr_hit[108] Covered T14,T26,T27
addr_hit[109] Covered T14,T26,T27
addr_hit[110] Covered T14,T26,T27
addr_hit[111] Covered T14,T26,T27
addr_hit[112] Covered T14,T26,T27
addr_hit[113] Covered T14,T26,T27
addr_hit[114] Covered T14,T26,T27
addr_hit[115] Covered T14,T26,T27
addr_hit[116] Covered T14,T26,T27
addr_hit[117] Covered T14,T26,T27
addr_hit[118] Covered T14,T26,T27
addr_hit[119] Covered T14,T26,T27
addr_hit[120] Covered T14,T26,T27
addr_hit[121] Covered T14,T26,T27
addr_hit[122] Covered T14,T26,T27
addr_hit[123] Covered T14,T26,T27
addr_hit[124] Covered T14,T26,T27
addr_hit[125] Covered T14,T26,T27
addr_hit[126] Covered T14,T26,T27
addr_hit[127] Covered T14,T26,T27
addr_hit[128] Covered T14,T26,T27
addr_hit[129] Covered T14,T26,T27
addr_hit[130] Covered T14,T26,T27
addr_hit[131] Covered T14,T26,T27
addr_hit[132] Covered T14,T26,T27
addr_hit[133] Covered T14,T26,T27
addr_hit[134] Covered T14,T26,T27
addr_hit[135] Covered T14,T26,T27
addr_hit[136] Covered T14,T26,T27
addr_hit[137] Covered T14,T26,T27
addr_hit[138] Covered T14,T26,T27
addr_hit[139] Covered T14,T26,T27
addr_hit[140] Covered T14,T26,T27
addr_hit[141] Covered T14,T26,T27
addr_hit[142] Covered T14,T26,T27
addr_hit[143] Covered T14,T26,T27
addr_hit[144] Covered T14,T26,T27
addr_hit[145] Covered T14,T26,T27
addr_hit[146] Covered T14,T26,T27
addr_hit[147] Covered T14,T26,T27
addr_hit[148] Covered T14,T26,T27
addr_hit[149] Covered T14,T26,T27
addr_hit[150] Covered T14,T26,T27
addr_hit[151] Covered T14,T26,T27
addr_hit[152] Covered T14,T26,T27
addr_hit[153] Covered T14,T26,T27
addr_hit[154] Covered T14,T26,T27
addr_hit[155] Covered T14,T26,T27
addr_hit[156] Covered T14,T26,T27
addr_hit[157] Covered T14,T26,T27
addr_hit[158] Covered T14,T26,T27
addr_hit[159] Covered T14,T26,T27
addr_hit[160] Covered T14,T26,T27
addr_hit[161] Covered T14,T26,T27
addr_hit[162] Covered T14,T26,T27
addr_hit[163] Covered T14,T26,T27
addr_hit[164] Covered T14,T26,T27
addr_hit[165] Covered T14,T26,T27
addr_hit[166] Covered T14,T26,T27
addr_hit[167] Covered T14,T26,T27
addr_hit[168] Covered T14,T26,T27
addr_hit[169] Covered T14,T26,T27
addr_hit[170] Covered T14,T26,T27
addr_hit[171] Covered T14,T26,T27
addr_hit[172] Covered T14,T26,T27
addr_hit[173] Covered T14,T26,T27
addr_hit[174] Covered T14,T26,T27
addr_hit[175] Covered T14,T26,T27
addr_hit[176] Covered T14,T26,T27
addr_hit[177] Covered T14,T26,T27
addr_hit[178] Covered T14,T26,T27
addr_hit[179] Covered T14,T26,T27
addr_hit[180] Covered T14,T26,T27
addr_hit[181] Covered T14,T26,T27
addr_hit[182] Covered T14,T26,T27
addr_hit[183] Covered T14,T26,T27
addr_hit[184] Covered T14,T26,T27
addr_hit[185] Covered T14,T26,T27
addr_hit[186] Covered T14,T26,T27
addr_hit[187] Covered T14,T26,T27
addr_hit[188] Covered T14,T26,T27
addr_hit[189] Covered T14,T26,T27
addr_hit[190] Covered T14,T26,T27
addr_hit[191] Covered T14,T26,T27
addr_hit[192] Covered T14,T26,T27
addr_hit[193] Covered T14,T26,T27
addr_hit[194] Covered T14,T26,T27
addr_hit[195] Covered T14,T26,T27
addr_hit[196] Covered T14,T26,T27
addr_hit[197] Covered T14,T26,T27
addr_hit[198] Covered T14,T26,T27
addr_hit[199] Covered T14,T26,T27
addr_hit[200] Covered T14,T26,T27
addr_hit[201] Covered T14,T26,T27
addr_hit[202] Covered T14,T26,T27
addr_hit[203] Covered T14,T26,T27
addr_hit[204] Covered T14,T26,T27
addr_hit[205] Covered T14,T26,T27
addr_hit[206] Covered T14,T26,T27
addr_hit[207] Covered T14,T26,T27
addr_hit[208] Covered T14,T26,T27
addr_hit[209] Covered T14,T26,T27
addr_hit[210] Covered T14,T26,T27
addr_hit[211] Covered T14,T26,T27
addr_hit[212] Covered T14,T26,T27
addr_hit[213] Covered T14,T26,T27
addr_hit[214] Covered T14,T26,T27
addr_hit[215] Covered T14,T26,T27
addr_hit[216] Covered T14,T26,T27
addr_hit[217] Covered T14,T26,T27
addr_hit[218] Covered T14,T26,T27
addr_hit[219] Covered T14,T26,T27
addr_hit[220] Covered T14,T26,T27
addr_hit[221] Covered T14,T26,T27
addr_hit[222] Covered T14,T26,T27
addr_hit[223] Covered T14,T26,T27
addr_hit[224] Covered T14,T26,T27
addr_hit[225] Covered T14,T26,T27
addr_hit[226] Covered T14,T26,T27
addr_hit[227] Covered T14,T26,T27
addr_hit[228] Covered T14,T26,T27
addr_hit[229] Covered T14,T26,T27
addr_hit[230] Covered T14,T26,T27
addr_hit[231] Covered T14,T26,T27
addr_hit[232] Covered T14,T26,T27
addr_hit[233] Covered T14,T26,T27
addr_hit[234] Covered T14,T26,T27
addr_hit[235] Covered T14,T26,T27
addr_hit[236] Covered T14,T26,T27
addr_hit[237] Covered T14,T26,T27
addr_hit[238] Covered T14,T26,T27
addr_hit[239] Covered T14,T26,T27
addr_hit[240] Covered T14,T26,T27
addr_hit[241] Covered T14,T26,T27
addr_hit[242] Covered T14,T26,T27
addr_hit[243] Covered T14,T26,T27
addr_hit[244] Covered T14,T26,T27
addr_hit[245] Covered T14,T26,T27
addr_hit[246] Covered T14,T26,T27
addr_hit[247] Covered T14,T26,T27
addr_hit[248] Covered T14,T26,T27
addr_hit[249] Covered T14,T26,T27
addr_hit[250] Covered T14,T26,T27
addr_hit[251] Covered T14,T26,T27
addr_hit[252] Covered T14,T26,T27
addr_hit[253] Covered T14,T26,T27
addr_hit[254] Covered T14,T26,T27
addr_hit[255] Covered T14,T26,T27
addr_hit[256] Covered T14,T26,T27
addr_hit[257] Covered T14,T26,T27
addr_hit[258] Covered T14,T26,T27
addr_hit[259] Covered T14,T26,T27
addr_hit[260] Covered T14,T26,T27
addr_hit[261] Covered T14,T26,T27
addr_hit[262] Covered T14,T26,T27
addr_hit[263] Covered T14,T26,T27
addr_hit[264] Covered T14,T26,T27
addr_hit[265] Covered T14,T26,T27
addr_hit[266] Covered T14,T26,T27
addr_hit[267] Covered T14,T26,T27
addr_hit[268] Covered T14,T26,T27
addr_hit[269] Covered T14,T26,T27
addr_hit[270] Covered T14,T26,T27
addr_hit[271] Covered T14,T26,T27
addr_hit[272] Covered T14,T26,T27
addr_hit[273] Covered T14,T26,T27
addr_hit[274] Covered T14,T26,T27
addr_hit[275] Covered T14,T26,T27
addr_hit[276] Covered T14,T26,T27
addr_hit[277] Covered T14,T26,T27
addr_hit[278] Covered T14,T26,T27
addr_hit[279] Covered T14,T26,T27
addr_hit[280] Covered T14,T26,T27
addr_hit[281] Covered T14,T26,T27
addr_hit[282] Covered T14,T26,T27
addr_hit[283] Covered T14,T26,T27
addr_hit[284] Covered T14,T26,T27
addr_hit[285] Covered T14,T26,T27
addr_hit[286] Covered T14,T26,T27
addr_hit[287] Covered T14,T26,T27
addr_hit[288] Covered T14,T26,T27
addr_hit[289] Covered T14,T26,T27
addr_hit[290] Covered T14,T26,T27
addr_hit[291] Covered T14,T26,T27
addr_hit[292] Covered T14,T26,T27
addr_hit[293] Covered T14,T26,T27
addr_hit[294] Covered T14,T26,T27
addr_hit[295] Covered T14,T26,T27
addr_hit[296] Covered T14,T26,T27
addr_hit[297] Covered T14,T26,T27
addr_hit[298] Covered T14,T26,T27
addr_hit[299] Covered T14,T26,T27
addr_hit[300] Covered T14,T26,T27
addr_hit[301] Covered T14,T26,T27
addr_hit[302] Covered T14,T26,T27
addr_hit[303] Covered T14,T26,T27
addr_hit[304] Covered T14,T26,T27
addr_hit[305] Covered T14,T26,T27
addr_hit[306] Covered T14,T26,T27
addr_hit[307] Covered T14,T26,T27
addr_hit[308] Covered T14,T26,T27
addr_hit[309] Covered T14,T26,T27
addr_hit[310] Covered T14,T26,T27
addr_hit[311] Covered T14,T26,T27
addr_hit[312] Covered T14,T26,T27
addr_hit[313] Covered T14,T26,T27
addr_hit[314] Covered T14,T26,T27
addr_hit[315] Covered T14,T26,T27
addr_hit[316] Covered T14,T26,T27
addr_hit[317] Covered T14,T26,T27
addr_hit[318] Covered T14,T26,T27
addr_hit[319] Covered T14,T26,T27
addr_hit[320] Covered T14,T26,T27
addr_hit[321] Covered T14,T26,T27
addr_hit[322] Covered T14,T26,T27
addr_hit[323] Covered T14,T26,T27
addr_hit[324] Covered T14,T26,T27
addr_hit[325] Covered T14,T26,T27
addr_hit[326] Covered T14,T26,T27
addr_hit[327] Covered T14,T26,T27
addr_hit[328] Covered T14,T26,T27
addr_hit[329] Covered T14,T26,T27
addr_hit[330] Covered T14,T26,T27
addr_hit[331] Covered T14,T26,T27
addr_hit[332] Covered T14,T26,T27
addr_hit[333] Covered T14,T26,T27
addr_hit[334] Covered T14,T26,T27
addr_hit[335] Covered T14,T26,T27
addr_hit[336] Covered T14,T26,T27
addr_hit[337] Covered T14,T26,T27
addr_hit[338] Covered T14,T26,T27
addr_hit[339] Covered T14,T26,T27
addr_hit[340] Covered T14,T26,T27
addr_hit[341] Covered T14,T26,T27
addr_hit[342] Covered T14,T26,T27
addr_hit[343] Covered T14,T26,T27
addr_hit[344] Covered T14,T26,T27
addr_hit[345] Covered T14,T26,T27
addr_hit[346] Covered T14,T26,T27
addr_hit[347] Covered T14,T26,T27
addr_hit[348] Covered T14,T26,T27
addr_hit[349] Covered T14,T26,T27
default Covered T14,T26,T27


LineNo. Expression -1-: 19395 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T14,T26,T27
0 Covered T14,T26,T27


LineNo. Expression -1-: 19403 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T14,T26,T27
0 Covered T14,T26,T27


Assert Coverage for Module : alert_handler_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 826835224 95666495 0 0
reAfterRv 826835224 95666462 0 0
rePulse 826835224 14134916 0 0
wePulse 826835224 81531546 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 826835224 95666495 0 0
T14 1266 40 0 0
T26 8661 4047 0 0
T27 3088 741 0 0
T28 2386 151 0 0
T29 3872 295 0 0
T30 2712 296 0 0
T31 9342 1360 0 0
T32 30523 13601 0 0
T33 165771 59686 0 0
T34 227183 25780 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 826835224 95666462 0 0
T14 1266 40 0 0
T26 8661 4047 0 0
T27 3088 741 0 0
T28 2386 151 0 0
T29 3872 295 0 0
T30 2712 296 0 0
T31 9342 1360 0 0
T32 30523 13601 0 0
T33 165771 59686 0 0
T34 227183 25780 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 826835224 14134916 0 0
T14 1266 20 0 0
T26 8661 1785 0 0
T27 3088 705 0 0
T28 2386 28 0 0
T29 3872 50 0 0
T30 2712 53 0 0
T31 9342 560 0 0
T32 30523 5573 0 0
T33 165771 58825 0 0
T34 227183 25368 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 826835224 81531546 0 0
T14 1266 20 0 0
T26 8661 2262 0 0
T27 3088 36 0 0
T28 2386 123 0 0
T29 3872 245 0 0
T30 2712 243 0 0
T31 9342 800 0 0
T32 30523 8028 0 0
T33 165771 861 0 0
T34 227183 412 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%