Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T20
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T20

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T20

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T22,T23
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T22,T25
1	1	1	Covered	T22,T24,T25

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T25
0	1	Covered	T25,T35,T17
1	0	Covered	T22,T18,T36

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T24,T25
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T18,T36

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T24,T25
1	0	Covered	T37,T38
1	1	Covered	T25,T35,T17

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T20
1	Covered	T3,T5,T22

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T20,T22

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T20
1	Covered	T5,T21,T22

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T20
1	Covered	T1,T21,T24

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T20,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T25,T35
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T39
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T40,T41,T42
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T41,T43
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T9,T41
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T40,T44
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T22,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	857	0	0
CheckAccumTrig0_A	2147483647	2510	0	0
CheckAccumTrig1_A	2147483647	131	0	0
CheckClr_A	2147483647	1184	0	0
CheckEn_A	2147483647	1469991100	0	0
CheckPhase0_A	2147483647	2917	0	0
CheckPhase1_A	2147483647	2871	0	0
CheckPhase2_A	2147483647	2813	0	0
CheckPhase3_A	2147483647	2756	0	0
CheckTimeout0_A	2147483647	5242	0	0
CheckTimeoutSt1_A	2147483647	671223	0	0
CheckTimeoutSt2_A	2147483647	4798	0	0
CheckTimeoutStTrig_A	2147483647	313	0	0
ErrorStAllEscAsserted_A	2147483647	5038	0	0
ErrorStIsTerminal_A	2147483647	4198	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	857	0	0
T11	199788	245	0	0
T12	0	111	0	0
T13	0	127	0	0
T45	0	247	0	0
T46	0	127	0	0
T47	691228	0	0	0
T48	3795776	0	0	0
T49	491048	0	0	0
T50	2557196	0	0	0
T51	428568	0	0	0
T52	3556896	0	0	0
T53	302336	0	0	0
T54	1171076	0	0	0
T55	1082420	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2510	0	0
T1	385200	7	0	0
T2	4383	0	0	0
T3	1379476	2	0	0
T4	946824	0	0	0
T5	2376416	2	0	0
T6	68196	0	0	0
T7	0	2	0	0
T9	0	1	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	2	0	0
T20	480864	1	0	0
T21	50264	3	0	0
T22	61116	3	0	0
T23	181444	1	0	0
T24	24689	8	0	0
T25	23230	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T40	0	2	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	131	0	0
T8	1046438	0	0	0
T9	257344	0	0	0
T15	152934	0	0	0
T18	474522	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	4292	0	0	0
T36	1817280	2	0	0
T39	31490	0	0	0
T40	1051952	0	0	0
T41	476013	3	0	0
T43	0	2	0	0
T44	0	3	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	44028	0	0	0
T60	914508	1	0	0
T61	109430	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	290894	0	0	0
T76	130223	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1184	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	387061	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T15	305868	1	0	0
T16	146945	0	0	0
T17	279593	3	0	0
T18	474522	1	0	0
T19	923241	0	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	30558	1	0	0
T23	90722	0	0	0
T24	24689	8	0	0
T36	908640	4	0	0
T40	525976	10	0	0
T41	0	10	0	0
T42	0	7	0	0
T43	0	4	0	0
T58	676422	0	0	0
T59	0	3	0	0
T60	0	6	0	0
T61	0	3	0	0
T63	0	2	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	34507	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469991100	0	0
T1	513600	1162284	0	0
T2	5844	4797	0	0
T3	1379476	699854	0	0
T4	946824	709684	0	0
T5	2376416	1190886	0	0
T6	68196	13030	0	0
T20	480864	363660	0	0
T21	50264	24756	0	0
T22	61116	20897	0	0
T23	181444	127982	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2917	0	0
T1	385200	7	0	0
T2	4383	0	0	0
T3	1379476	2	0	0
T4	946824	0	0	0
T5	2376416	2	0	0
T6	68196	0	0	0
T7	0	1	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	2	0	0
T20	480864	1	0	0
T21	50264	3	0	0
T22	61116	4	0	0
T23	181444	1	0	0
T24	24689	8	0	0
T25	23230	1	0	0
T35	0	4	0	0
T40	0	2	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2871	0	0
T1	385200	7	0	0
T2	4383	0	0	0
T3	1379476	2	0	0
T4	946824	0	0	0
T5	2376416	2	0	0
T6	68196	0	0	0
T7	0	1	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	2	0	0
T20	480864	1	0	0
T21	50264	3	0	0
T22	61116	4	0	0
T23	181444	1	0	0
T24	24689	8	0	0
T25	23230	1	0	0
T35	0	4	0	0
T40	0	2	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2813	0	0
T1	385200	7	0	0
T2	4383	0	0	0
T3	1379476	2	0	0
T4	946824	0	0	0
T5	2376416	2	0	0
T6	68196	0	0	0
T7	0	1	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	2	0	0
T20	480864	1	0	0
T21	50264	3	0	0
T22	61116	4	0	0
T23	181444	1	0	0
T24	24689	8	0	0
T25	23230	1	0	0
T35	0	4	0	0
T40	0	2	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2756	0	0
T1	385200	7	0	0
T2	4383	0	0	0
T3	1379476	2	0	0
T4	946824	0	0	0
T5	2376416	2	0	0
T6	68196	0	0	0
T7	0	1	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	5	0	0
T18	0	2	0	0
T20	480864	1	0	0
T21	50264	3	0	0
T22	61116	4	0	0
T23	181444	1	0	0
T24	24689	7	0	0
T25	23230	1	0	0
T35	0	4	0	0
T40	0	2	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5242	0	0
T15	611736	0	0	0
T16	440835	0	0	0
T17	838779	4	0	0
T18	949044	4	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T24	49378	1	0	0
T25	92920	13	0	0
T35	17168	2	0	0
T36	0	23	0	0
T39	125960	17	0	0
T41	0	31	0	0
T56	542192	0	0	0
T57	185644	0	0	0
T58	1352844	0	0	0
T59	0	3	0	0
T60	0	21	0	0
T61	0	6	0	0
T62	0	68	0	0
T77	0	1	0	0
T81	0	11	0	0
T82	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	671223	0	0
T15	611736	0	0	0
T16	440835	0	0	0
T17	838779	444	0	0
T18	949044	338	0	0
T22	15279	82	0	0
T23	45361	0	0	0
T24	49378	140	0	0
T25	92920	1375	0	0
T35	17168	424	0	0
T36	0	4833	0	0
T39	125960	1414	0	0
T41	0	8288	0	0
T56	542192	0	0	0
T57	185644	0	0	0
T58	1352844	0	0	0
T59	0	211	0	0
T60	0	2095	0	0
T61	0	291	0	0
T62	0	9714	0	0
T77	0	62	0	0
T81	0	1755	0	0
T82	0	74	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4798	0	0
T7	387061	0	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T15	458802	0	0	0
T16	440835	0	0	0
T17	1118372	2	0	0
T18	949044	1	0	0
T19	923241	0	0	0
T24	24689	1	0	0
T25	69690	11	0	0
T35	12876	0	0	0
T36	908640	17	0	0
T39	94470	9	0	0
T40	525976	0	0	0
T41	0	8	0	0
T43	0	2	0	0
T52	0	1	0	0
T56	406644	0	0	0
T57	139233	0	0	0
T58	1014633	0	0	0
T59	22014	2	0	0
T60	0	18	0	0
T61	0	1	0	0
T62	0	66	0	0
T63	0	1	0	0
T77	0	1	0	0
T81	69014	9	0	0
T82	0	10	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	3	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	313	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T10	875546	0	0	0
T15	305868	0	0	0
T16	293890	0	0	0
T17	559186	1	0	0
T25	23230	1	0	0
T35	8584	1	0	0
T36	1817280	3	0	0
T39	62980	0	0	0
T40	525976	0	0	0
T41	1428039	9	0	0
T44	0	2	0	0
T52	0	3	0	0
T56	135548	0	0	0
T57	92822	0	0	0
T58	676422	0	0	0
T59	22014	1	0	0
T60	914508	1	0	0
T61	328290	0	0	0
T62	0	2	0	0
T75	581788	0	0	0
T76	260446	0	0	0
T82	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	3	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	776993	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5038	0	0
T11	199788	1438	0	0
T12	0	776	0	0
T13	0	706	0	0
T45	0	1383	0	0
T46	0	735	0	0
T47	691228	0	0	0
T48	3795776	0	0	0
T49	491048	0	0	0
T50	2557196	0	0	0
T51	428568	0	0	0
T52	3556896	0	0	0
T53	302336	0	0	0
T54	1171076	0	0	0
T55	1082420	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4198	0	0
T11	199788	1198	0	0
T12	0	656	0	0
T13	0	586	0	0
T45	0	1143	0	0
T46	0	615	0	0
T47	691228	0	0	0
T48	3795776	0	0	0
T49	491048	0	0	0
T50	2557196	0	0	0
T51	428568	0	0	0
T52	3556896	0	0	0
T53	302336	0	0	0
T54	1171076	0	0	0
T55	1082420	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	513600	513512	0	0
T2	5844	5624	0	0
T3	1379476	1379436	0	0
T4	946824	946784	0	0
T5	2376416	2376076	0	0
T6	68196	67520	0	0
T20	480864	480580	0	0
T21	50264	50036	0	0
T22	61116	60852	0	0
T23	181444	181184	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T20,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T22,T23
1	0	1	Covered	T2,T21,T24
1	1	0	Covered	T39,T17,T81
1	1	1	Covered	T24,T25,T35

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T35
0	1	Covered	T35,T17,T41
1	0	Covered	T36,T41,T61

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T24,T25,T35
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T41,T61

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T35
1	0	Not Covered
1	1	Covered	T35,T17,T41

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T21
1	Covered	T5,T24,T35

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T20,T24

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T5
1	Covered	T22,T23,T24

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T5
1	Covered	T1,T21,T24

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T20,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T22,T23

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T21,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T35
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T35,T17,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T35
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T39
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T41,T64,T66
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T20,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T20,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T41,T97,T71
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T20,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T20,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T41,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T20,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T20,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T99,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T20,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T20,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T24,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T20,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	802478565	173	0	0
CheckAccumTrig0_A	802478565	886	0	0
CheckAccumTrig1_A	802478565	59	0	0
CheckClr_A	802478565	423	0	0
CheckEn_A	802319401	304537100	0	0
CheckPhase0_A	802478565	1017	0	0
CheckPhase1_A	802478565	1003	0	0
CheckPhase2_A	802478565	980	0	0
CheckPhase3_A	802478565	959	0	0
CheckTimeout0_A	802478565	1687	0	0
CheckTimeoutSt1_A	802478565	209229	0	0
CheckTimeoutSt2_A	802478565	1544	0	0
CheckTimeoutStTrig_A	802478565	84	0	0
ErrorStAllEscAsserted_A	802478565	1280	0	0
ErrorStIsTerminal_A	802478565	1070	0	0
u_state_regs_A	802478565	802316967	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	173	0	0
T11	49947	48	0	0
T12	0	36	0	0
T13	0	26	0	0
T45	0	45	0	0
T46	0	18	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	886	0	0
T1	128400	4	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T20	120216	1	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	1	0	0
T24	0	8	0	0
T56	0	1	0	0
T58	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	59	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T36	908640	2	0	0
T40	525976	0	0	0
T41	476013	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T59	22014	0	0	0
T60	457254	0	0	0
T61	109430	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T75	290894	0	0	0
T76	130223	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	423	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T10	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T24	0	8	0	0
T36	0	4	0	0
T40	0	1	0	0
T41	0	8	0	0
T60	0	3	0	0
T61	0	3	0	0
T63	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802319401	304537100	0	0
T1	128400	8944	0	0
T2	1461	582	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	868	0	0
T6	17049	3228	0	0
T20	120216	3228	0	0
T21	12566	3134	0	0
T22	15279	1896	0	0
T23	45361	3147	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1017	0	0
T1	128400	4	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T20	120216	1	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	1	0	0
T24	0	8	0	0
T35	0	1	0	0
T56	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1003	0	0
T1	128400	4	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T20	120216	1	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	1	0	0
T24	0	8	0	0
T35	0	1	0	0
T56	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	980	0	0
T1	128400	4	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T20	120216	1	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	1	0	0
T24	0	8	0	0
T35	0	1	0	0
T56	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	959	0	0
T1	128400	4	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T20	120216	1	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	1	0	0
T24	0	7	0	0
T35	0	1	0	0
T56	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1687	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	2	0	0
T24	24689	1	0	0
T25	23230	10	0	0
T35	4292	1	0	0
T36	0	2	0	0
T39	31490	1	0	0
T41	0	11	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	1	0	0
T61	0	4	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	209229	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	255	0	0
T24	24689	140	0	0
T25	23230	1187	0	0
T35	4292	419	0	0
T36	0	24	0	0
T39	31490	93	0	0
T41	0	2790	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	61	0	0
T61	0	74	0	0
T81	0	170	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1544	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	1	0	0
T24	24689	1	0	0
T25	23230	10	0	0
T35	4292	0	0	0
T39	31490	1	0	0
T41	0	8	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	84	0	0
T10	437773	0	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	1	0	0
T35	4292	1	0	0
T39	31490	0	0	0
T41	476013	1	0	0
T44	0	1	0	0
T52	0	2	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T61	109430	0	0	0
T62	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1280	0	0
T11	49947	398	0	0
T12	0	189	0	0
T13	0	165	0	0
T45	0	325	0	0
T46	0	203	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1070	0	0
T11	49947	338	0	0
T12	0	159	0	0
T13	0	135	0	0
T45	0	265	0	0
T46	0	173	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	802316967	0	0
T1	128400	128378	0	0
T2	1461	1406	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	594019	0	0
T6	17049	16880	0	0
T20	120216	120145	0	0
T21	12566	12509	0	0
T22	15279	15213	0	0
T23	45361	45296	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T21
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T21

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T21

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T25,T35
1	0	1	Covered	T4,T56,T15
1	1	0	Covered	T1,T22,T25
1	1	1	Covered	T25,T35,T39

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T25,T35,T39
0	1	Covered	T60,T41,T101
1	0	Covered	T35,T41,T65

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T25,T35,T39
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T35,T41,T65

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T35,T39
1	0	Not Covered
1	1	Covered	T60,T41,T101

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T56
1	Covered	T1,T58,T18

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T35,T60,T41

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T35
1	Covered	T21,T56,T40

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T21,T56
1	Covered	T3,T17,T40

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T21,T17,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T56,T35,T58

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T56,T58

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T35,T39
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T35,T60,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T25,T35,T39
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T39,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T75,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T104,T52,T53
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T91,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T106,T107,T108
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T21,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	802478565	228	0	0
CheckAccumTrig0_A	802478565	499	0	0
CheckAccumTrig1_A	802478565	17	0	0
CheckClr_A	802478565	222	0	0
CheckEn_A	802319401	418239266	0	0
CheckPhase0_A	802478565	586	0	0
CheckPhase1_A	802478565	581	0	0
CheckPhase2_A	802478565	568	0	0
CheckPhase3_A	802478565	562	0	0
CheckTimeout0_A	802478565	1395	0	0
CheckTimeoutSt1_A	802478565	167763	0	0
CheckTimeoutSt2_A	802478565	1302	0	0
CheckTimeoutStTrig_A	802478565	76	0	0
ErrorStAllEscAsserted_A	802478565	1226	0	0
ErrorStIsTerminal_A	802478565	1016	0	0
u_state_regs_A	802478565	802316967	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	228	0	0
T11	49947	68	0	0
T12	0	31	0	0
T13	0	44	0	0
T45	0	59	0	0
T46	0	26	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	499	0	0
T1	128400	2	0	0
T2	1461	0	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T9	0	1	0	0
T17	0	3	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T40	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	17	0	0
T10	437773	0	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	0	0	0
T35	4292	1	0	0
T39	31490	0	0	0
T41	476013	1	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T61	109430	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	222	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T9	0	1	0	0
T17	0	2	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	0	1	0	0
T104	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802319401	418239266	0	0
T1	128400	898029	0	0
T2	1461	1405	0	0
T3	344869	7413	0	0
T4	236706	234272	0	0
T5	594104	594018	0	0
T6	17049	3295	0	0
T20	120216	120144	0	0
T21	12566	5951	0	0
T22	15279	15212	0	0
T23	45361	45295	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	586	0	0
T1	128400	2	0	0
T2	1461	0	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	1	0	0
T40	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	581	0	0
T1	128400	2	0	0
T2	1461	0	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	1	0	0
T40	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	568	0	0
T1	128400	2	0	0
T2	1461	0	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	1	0	0
T40	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	562	0	0
T1	128400	2	0	0
T2	1461	0	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	1	0	0
T40	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1395	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	1	0	0
T18	474522	2	0	0
T25	23230	1	0	0
T35	4292	1	0	0
T36	0	1	0	0
T39	31490	8	0	0
T41	0	11	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	167763	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	167	0	0
T18	474522	174	0	0
T25	23230	54	0	0
T35	4292	5	0	0
T36	0	243	0	0
T39	31490	721	0	0
T41	0	3177	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	144	0	0
T61	0	217	0	0
T81	0	337	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1302	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	1	0	0
T18	474522	2	0	0
T25	23230	1	0	0
T35	4292	0	0	0
T36	0	1	0	0
T39	31490	8	0	0
T41	0	7	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T61	0	2	0	0
T81	0	2	0	0
T84	0	5	0	0
T101	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	76	0	0
T10	437773	0	0	0
T41	476013	3	0	0
T44	0	1	0	0
T53	0	2	0	0
T60	457254	1	0	0
T61	109430	0	0	0
T62	0	1	0	0
T65	0	1	0	0
T75	290894	0	0	0
T76	130223	0	0	0
T83	24584	0	0	0
T91	0	2	0	0
T96	776993	0	0	0
T101	0	1	0	0
T104	947600	0	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	196246	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1226	0	0
T11	49947	348	0	0
T12	0	184	0	0
T13	0	187	0	0
T45	0	340	0	0
T46	0	167	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1016	0	0
T11	49947	288	0	0
T12	0	154	0	0
T13	0	157	0	0
T45	0	280	0	0
T46	0	137	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	802316967	0	0
T1	128400	128378	0	0
T2	1461	1406	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	594019	0	0
T6	17049	16880	0	0
T20	120216	120145	0	0
T21	12566	12509	0	0
T22	15279	15213	0	0
T23	45361	45296	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T21
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T21

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T21

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T22,T25
1	0	1	Covered	T4,T57,T15
1	1	0	Covered	T22,T25,T39
1	1	1	Covered	T22,T17,T18

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T17,T18
0	1	Covered	T36,T41,T82
1	0	Covered	T22,T60,T62

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T60,T62

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T18
1	0	Covered	T38
1	1	Covered	T36,T41,T82

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T21,T22
1	Covered	T35,T18,T60

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T21,T35,T57
1	Covered	T1,T22,T15

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T35
1	Covered	T21,T17,T59

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T21,T22
1	Covered	T57,T7,T36

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T22,T15

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T21,T22,T35

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T22,T35

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T35,T57,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T36,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T81
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T42,T118,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T21,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T21,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T43,T79,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T21,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T21,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T42,T65
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T21,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T21,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T119,T71
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T21,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T21,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T17,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T21,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	802478565	234	0	0
CheckAccumTrig0_A	802478565	567	0	0
CheckAccumTrig1_A	802478565	22	0	0
CheckClr_A	802478565	289	0	0
CheckEn_A	802319401	376565645	0	0
CheckPhase0_A	802478565	662	0	0
CheckPhase1_A	802478565	647	0	0
CheckPhase2_A	802478565	635	0	0
CheckPhase3_A	802478565	621	0	0
CheckTimeout0_A	802478565	871	0	0
CheckTimeoutSt1_A	802478565	117665	0	0
CheckTimeoutSt2_A	802478565	762	0	0
CheckTimeoutStTrig_A	802478565	87	0	0
ErrorStAllEscAsserted_A	802478565	1302	0	0
ErrorStIsTerminal_A	802478565	1092	0	0
u_state_regs_A	802478565	802316967	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	234	0	0
T11	49947	67	0	0
T12	0	17	0	0
T13	0	44	0	0
T45	0	69	0	0
T46	0	37	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	567	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	0	0	0
T23	45361	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	22	0	0
T15	152934	0	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	4292	0	0	0
T39	31490	0	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	289	0	0
T7	387061	0	0	0
T9	0	4	0	0
T15	152934	1	0	0
T16	146945	0	0	0
T17	279593	1	0	0
T18	474522	1	0	0
T19	923241	0	0	0
T36	908640	0	0	0
T40	525976	0	0	0
T41	0	2	0	0
T42	0	5	0	0
T58	338211	0	0	0
T59	0	3	0	0
T60	0	3	0	0
T77	0	1	0	0
T78	0	1	0	0
T81	34507	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802319401	376565645	0	0
T1	128400	127096	0	0
T2	1461	1405	0	0
T3	344869	344859	0	0
T4	236706	2020	0	0
T5	594104	594018	0	0
T6	17049	3239	0	0
T20	120216	120144	0	0
T21	12566	3163	0	0
T22	15279	3199	0	0
T23	45361	45295	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	662	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T35	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	647	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T35	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	635	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T35	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	621	0	0
T1	128400	1	0	0
T2	1461	0	0	0
T3	344869	0	0	0
T4	236706	0	0	0
T5	594104	0	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	120216	0	0	0
T21	12566	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T35	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	871	0	0
T15	152934	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	4292	0	0	0
T36	0	2	0	0
T39	31490	0	0	0
T41	0	6	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	0	2	0	0
T60	0	18	0	0
T62	0	2	0	0
T77	0	1	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	117665	0	0
T15	152934	0	0	0
T17	0	22	0	0
T18	0	163	0	0
T22	15279	82	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	4292	0	0	0
T36	0	521	0	0
T39	31490	0	0	0
T41	0	1429	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	0	22	0	0
T60	0	1700	0	0
T62	0	224	0	0
T77	0	62	0	0
T81	0	316	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	762	0	0
T7	387061	0	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T17	279593	1	0	0
T18	474522	1	0	0
T19	923241	0	0	0
T36	908640	0	0	0
T40	525976	0	0	0
T43	0	1	0	0
T59	22014	2	0	0
T60	0	17	0	0
T62	0	1	0	0
T63	0	1	0	0
T77	0	1	0	0
T81	34507	2	0	0
T82	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	87	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T36	908640	2	0	0
T40	525976	0	0	0
T41	476013	6	0	0
T59	22014	0	0	0
T60	457254	0	0	0
T61	109430	0	0	0
T75	290894	0	0	0
T76	130223	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1302	0	0
T11	49947	357	0	0
T12	0	204	0	0
T13	0	180	0	0
T45	0	362	0	0
T46	0	199	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1092	0	0
T11	49947	297	0	0
T12	0	174	0	0
T13	0	150	0	0
T45	0	302	0	0
T46	0	169	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	802316967	0	0
T1	128400	128378	0	0
T2	1461	1406	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	594019	0	0
T6	17049	16880	0	0
T20	120216	120145	0	0
T21	12566	12509	0	0
T22	15279	15213	0	0
T23	45361	45296	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T22
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T22

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T22

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T22,T23,T25
1	0	1	Covered	T1,T5,T16
1	1	0	Covered	T1,T25,T17
1	1	1	Covered	T25,T39,T18

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T25,T39,T18
0	1	Covered	T25,T36,T59
1	0	Covered	T18,T41,T43

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T25,T39,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T41,T43

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T39,T18
1	0	Covered	T37
1	1	Covered	T25,T36,T59

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T25,T56
1	Covered	T3,T22,T35

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T22
1	Covered	T25,T56,T15

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T22,T25
1	Covered	T5,T16,T18

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T22
1	Covered	T40,T41,T61

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T56,T57,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T22,T57

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T22,T25,T56

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T14
IdleSt	175	Covered	T14
Phase0St	146	Covered	T14
Phase1St	192	Covered	T14
Phase2St	209	Covered	T14
Phase3St	227	Covered	T14
TerminalSt	243	Covered	T14
TimeoutSt	153	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T14
IdleSt->Phase0St	146	Covered	T14
IdleSt->TimeoutSt	153	Covered	T14
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T14
Phase0St->Phase1St	192	Covered	T14
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T14
Phase1St->Phase2St	209	Covered	T14
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T14
Phase2St->Phase3St	227	Covered	T14
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T14
Phase3St->TerminalSt	243	Covered	T14
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T14
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T14
TimeoutSt->Phase0St	166	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T39,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T18,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T25,T39,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T39,T81
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T40,T120,T121
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T118,T122
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T80,T123
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T40,T42,T65
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T22,T17,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	802478565	222	0	0
CheckAccumTrig0_A	802478565	558	0	0
CheckAccumTrig1_A	802478565	33	0	0
CheckClr_A	802478565	250	0	0
CheckEn_A	802319401	370649089	0	0
CheckPhase0_A	802478565	652	0	0
CheckPhase1_A	802478565	640	0	0
CheckPhase2_A	802478565	630	0	0
CheckPhase3_A	802478565	614	0	0
CheckTimeout0_A	802478565	1289	0	0
CheckTimeoutSt1_A	802478565	176566	0	0
CheckTimeoutSt2_A	802478565	1190	0	0
CheckTimeoutStTrig_A	802478565	66	0	0
ErrorStAllEscAsserted_A	802478565	1230	0	0
ErrorStIsTerminal_A	802478565	1020	0	0
u_state_regs_A	802478565	802316967	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	222	0	0
T11	49947	62	0	0
T12	0	27	0	0
T13	0	13	0	0
T45	0	74	0	0
T46	0	46	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	558	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T7	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	2	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	33	0	0
T7	387061	0	0	0
T8	523219	0	0	0
T9	128672	0	0	0
T18	474522	1	0	0
T19	923241	0	0	0
T36	908640	0	0	0
T40	525976	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T52	0	1	0	0
T59	22014	0	0	0
T60	457254	0	0	0
T65	0	1	0	0
T81	34507	0	0	0
T90	0	1	0	0
T110	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	250	0	0
T15	152934	0	0	0
T17	0	1	0	0
T22	15279	1	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	0	0	0
T35	4292	0	0	0
T39	31490	0	0	0
T40	0	9	0	0
T42	0	2	0	0
T43	0	4	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T65	0	3	0	0
T77	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T88	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802319401	370649089	0	0
T1	128400	128215	0	0
T2	1461	1405	0	0
T3	344869	2723	0	0
T4	236706	236696	0	0
T5	594104	1982	0	0
T6	17049	3268	0	0
T20	120216	120144	0	0
T21	12566	12508	0	0
T22	15279	590	0	0
T23	45361	34245	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	652	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	2	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	1	0	0
T35	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	640	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	2	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	1	0	0
T35	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	630	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	2	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	1	0	0
T35	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	614	0	0
T3	344869	1	0	0
T4	236706	0	0	0
T5	594104	1	0	0
T6	17049	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	120216	0	0	0
T21	12566	0	0	0
T22	15279	2	0	0
T23	45361	0	0	0
T24	24689	0	0	0
T25	23230	1	0	0
T35	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1289	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	0	0	0
T18	474522	1	0	0
T25	23230	2	0	0
T35	4292	0	0	0
T36	0	18	0	0
T39	31490	8	0	0
T41	0	3	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	66	0	0
T81	0	6	0	0
T82	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	176566	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	0	0	0
T18	474522	1	0	0
T25	23230	134	0	0
T35	4292	0	0	0
T36	0	4045	0	0
T39	31490	600	0	0
T41	0	892	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	0	189	0	0
T60	0	190	0	0
T62	0	9490	0	0
T81	0	932	0	0
T82	0	74	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1190	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	0	0	0
T25	23230	1	0	0
T35	4292	0	0	0
T36	0	17	0	0
T39	31490	8	0	0
T43	0	1	0	0
T52	0	1	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T62	0	65	0	0
T81	34507	6	0	0
T82	0	2	0	0
T85	0	3	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	66	0	0
T15	152934	0	0	0
T16	146945	0	0	0
T17	279593	0	0	0
T25	23230	1	0	0
T35	4292	0	0	0
T36	908640	1	0	0
T39	31490	0	0	0
T41	0	2	0	0
T44	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T56	135548	0	0	0
T57	46411	0	0	0
T58	338211	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T88	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1230	0	0
T11	49947	335	0	0
T12	0	199	0	0
T13	0	174	0	0
T45	0	356	0	0
T46	0	166	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	1020	0	0
T11	49947	275	0	0
T12	0	169	0	0
T13	0	144	0	0
T45	0	296	0	0
T46	0	136	0	0
T47	172807	0	0	0
T48	948944	0	0	0
T49	122762	0	0	0
T50	639299	0	0	0
T51	107142	0	0	0
T52	889224	0	0	0
T53	75584	0	0	0
T54	292769	0	0	0
T55	270605	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	802478565	802316967	0	0
T1	128400	128378	0	0
T2	1461	1406	0	0
T3	344869	344859	0	0
T4	236706	236696	0	0
T5	594104	594019	0	0
T6	17049	16880	0	0
T20	120216	120145	0	0
T21	12566	12509	0	0
T22	15279	15213	0	0
T23	45361	45296	0	0