Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68954190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33772112

1

T17

8

T28

57316

T29

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15205246	1			T17	10		T28	106950		T29	20
values[0x0]	42341649	1			T17	5		T28	40620		T29	11
values[0x1]	45179407	1			T17	5		T28	40591		T29	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58498903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44227399

1

T17

8

T28

85516

T29

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	339697	1			T28	712		T31	512		T32	2
valid_sources[0x01]	350215	1			T28	739		T31	768		T32	2
valid_sources[0x02]	332758	1			T28	718		T31	384		T33	56
valid_sources[0x03]	645747	1			T28	798		T31	896		T32	5
valid_sources[0x04]	338246	1			T28	728		T31	320		T32	2
valid_sources[0x05]	323841	1			T28	711		T29	1		T31	320
valid_sources[0x06]	345258	1			T28	718		T31	640		T32	1
valid_sources[0x07]	673967	1			T28	773		T32	1		T33	73
valid_sources[0x08]	376485	1			T28	753		T31	128		T32	1
valid_sources[0x09]	326901	1			T28	682		T30	1		T31	320
valid_sources[0x0a]	336503	1			T28	758		T31	192		T32	4
valid_sources[0x0b]	337009	1			T28	709		T31	128		T33	60
valid_sources[0x0c]	798000	1			T28	756		T32	1		T33	45
valid_sources[0x0d]	347203	1			T28	716		T31	320		T33	39
valid_sources[0x0e]	346397	1			T28	649		T31	512		T32	3
valid_sources[0x0f]	354046	1			T28	694		T31	128		T32	1
valid_sources[0x10]	382550	1			T28	732		T31	320		T33	31
valid_sources[0x11]	349861	1			T28	705		T29	1		T32	1
valid_sources[0x12]	343350	1			T28	828		T31	512		T32	1
valid_sources[0x13]	342508	1			T28	771		T29	1		T31	512
valid_sources[0x14]	330832	1			T28	739		T31	192		T32	1
valid_sources[0x15]	329987	1			T28	763		T31	512		T32	1
valid_sources[0x16]	328536	1			T28	722		T31	320		T33	48
valid_sources[0x17]	335032	1			T28	731		T31	256		T32	1
valid_sources[0x18]	695641	1			T28	738		T31	704		T32	1
valid_sources[0x19]	661490	1			T28	706		T31	256		T32	1
valid_sources[0x1a]	729696	1			T28	677		T33	58		T34	31
valid_sources[0x1b]	340223	1			T28	718		T31	320		T32	2
valid_sources[0x1c]	335665	1			T28	741		T29	1		T31	448
valid_sources[0x1d]	340643	1			T28	747		T31	128		T32	1
valid_sources[0x1e]	343680	1			T28	710		T31	320		T32	3
valid_sources[0x1f]	318802	1			T28	787		T31	256		T32	1
valid_sources[0x20]	337758	1			T28	745		T29	1		T31	512
valid_sources[0x21]	562553	1			T28	728		T31	192		T32	1
valid_sources[0x22]	340055	1			T28	765		T31	320		T32	1
valid_sources[0x23]	380671	1			T28	752		T29	1		T30	1
valid_sources[0x24]	338470	1			T28	723		T31	128		T33	54
valid_sources[0x25]	343012	1			T28	717		T31	192		T32	1
valid_sources[0x26]	341015	1			T28	694		T31	192		T32	1
valid_sources[0x27]	347102	1			T28	786		T31	832		T32	2
valid_sources[0x28]	339257	1			T28	730		T29	1		T32	2
valid_sources[0x29]	353452	1			T28	704		T31	320		T32	2
valid_sources[0x2a]	659476	1			T28	765		T31	256		T33	146
valid_sources[0x2b]	338773	1			T28	799		T32	1		T33	44
valid_sources[0x2c]	332527	1			T28	747		T31	192		T32	1
valid_sources[0x2d]	347222	1			T28	769		T31	448		T32	1
valid_sources[0x2e]	342872	1			T28	752		T31	768		T32	1
valid_sources[0x2f]	330585	1			T28	748		T30	3		T31	832
valid_sources[0x30]	334920	1			T28	737		T31	320		T32	1
valid_sources[0x31]	336853	1			T28	714		T31	768		T32	1
valid_sources[0x32]	339825	1			T28	704		T31	320		T33	59
valid_sources[0x33]	334090	1			T28	754		T31	192		T32	1
valid_sources[0x34]	342491	1			T28	726		T31	384		T32	2
valid_sources[0x35]	355552	1			T28	678		T30	3		T31	192
valid_sources[0x36]	343732	1			T28	733		T31	384		T32	1
valid_sources[0x37]	327113	1			T28	671		T32	2		T33	72
valid_sources[0x38]	343679	1			T28	724		T31	384		T32	1
valid_sources[0x39]	342925	1			T28	796		T30	1		T31	128
valid_sources[0x3a]	649695	1			T28	761		T31	320		T33	47
valid_sources[0x3b]	330611	1			T28	804		T31	320		T32	1
valid_sources[0x3c]	337623	1			T28	721		T31	320		T32	3
valid_sources[0x3d]	335827	1			T28	628		T29	1		T32	1
valid_sources[0x3e]	345137	1			T28	679		T29	1		T31	384
valid_sources[0x3f]	1266117	1			T28	786		T31	192		T33	43
valid_sources[0x40]	330358	1			T28	728		T31	192		T32	1
valid_sources[0x41]	342169	1			T28	752		T29	2		T31	192
valid_sources[0x42]	336159	1			T28	718		T31	256		T32	1
valid_sources[0x43]	333625	1			T28	782		T31	320		T32	2
valid_sources[0x44]	350080	1			T17	20		T28	640		T31	768
valid_sources[0x45]	650706	1			T28	647		T29	1		T31	128
valid_sources[0x46]	331041	1			T28	700		T32	3		T33	52
valid_sources[0x47]	341963	1			T28	752		T30	1		T31	256
valid_sources[0x48]	334530	1			T28	745		T29	2		T31	192
valid_sources[0x49]	324813	1			T28	740		T31	320		T32	1
valid_sources[0x4a]	345582	1			T28	752		T32	2		T33	20
valid_sources[0x4b]	347809	1			T28	679		T31	640		T32	2
valid_sources[0x4c]	331284	1			T28	761		T29	1		T31	128
valid_sources[0x4d]	344470	1			T28	784		T32	1		T33	47
valid_sources[0x4e]	333233	1			T28	792		T31	320		T32	2
valid_sources[0x4f]	345962	1			T28	797		T31	128		T32	1
valid_sources[0x50]	346185	1			T28	714		T31	320		T32	1
valid_sources[0x51]	337990	1			T28	667		T31	320		T32	1
valid_sources[0x52]	331033	1			T28	682		T31	256		T32	1
valid_sources[0x53]	327890	1			T28	708		T33	49		T34	20
valid_sources[0x54]	795691	1			T28	777		T31	576		T33	44
valid_sources[0x55]	339340	1			T28	747		T31	448		T32	3
valid_sources[0x56]	335964	1			T28	781		T31	192		T33	57
valid_sources[0x57]	346965	1			T28	658		T31	320		T32	3
valid_sources[0x58]	340422	1			T28	711		T29	1		T31	640
valid_sources[0x59]	353692	1			T28	786		T31	640		T32	1
valid_sources[0x5a]	332165	1			T28	738		T30	1		T31	512
valid_sources[0x5b]	581370	1			T28	753		T29	1		T31	256
valid_sources[0x5c]	346410	1			T28	653		T31	192		T33	37
valid_sources[0x5d]	328481	1			T28	729		T31	192		T33	50
valid_sources[0x5e]	695472	1			T28	802		T31	128		T33	51
valid_sources[0x5f]	325419	1			T28	659		T29	2		T31	128
valid_sources[0x60]	336768	1			T28	739		T29	1		T31	128
valid_sources[0x61]	837296	1			T28	718		T29	2		T31	576
valid_sources[0x62]	334488	1			T28	682		T33	36		T34	23
valid_sources[0x63]	340834	1			T28	750		T31	256		T33	65
valid_sources[0x64]	649559	1			T28	673		T31	320		T32	6
valid_sources[0x65]	339177	1			T28	685		T31	128		T32	1
valid_sources[0x66]	333033	1			T28	778		T31	192		T32	1
valid_sources[0x67]	334235	1			T28	694		T31	192		T32	2
valid_sources[0x68]	596447	1			T28	697		T31	640		T32	2
valid_sources[0x69]	331670	1			T28	710		T31	448		T32	4
valid_sources[0x6a]	409324	1			T28	721		T31	320		T32	2
valid_sources[0x6b]	340053	1			T28	713		T32	1		T33	26
valid_sources[0x6c]	696805	1			T28	785		T31	448		T32	3
valid_sources[0x6d]	338975	1			T28	746		T31	576		T32	2
valid_sources[0x6e]	380960	1			T28	788		T31	512		T33	42
valid_sources[0x6f]	340908	1			T28	746		T31	768		T33	31
valid_sources[0x70]	329658	1			T28	845		T31	128		T32	2
valid_sources[0x71]	799852	1			T28	672		T31	256		T32	1
valid_sources[0x72]	336880	1			T28	683		T31	256		T32	1
valid_sources[0x73]	329131	1			T28	746		T31	128		T32	4
valid_sources[0x74]	989020	1			T28	666		T31	128		T33	83
valid_sources[0x75]	335876	1			T28	777		T31	1088		T32	2
valid_sources[0x76]	342680	1			T28	808		T31	320		T32	1
valid_sources[0x77]	786394	1			T28	738		T32	3		T33	48
valid_sources[0x78]	348618	1			T28	777		T29	1		T31	128
valid_sources[0x79]	327121	1			T28	720		T31	320		T32	1
valid_sources[0x7a]	335368	1			T28	702		T31	128		T32	4
valid_sources[0x7b]	330686	1			T28	688		T32	1		T33	55
valid_sources[0x7c]	339586	1			T28	736		T31	512		T33	83
valid_sources[0x7d]	355377	1			T28	741		T31	384		T32	4
valid_sources[0x7e]	344735	1			T28	815		T29	1		T33	38
valid_sources[0x7f]	337841	1			T28	707		T31	512		T33	78
valid_sources[0x80]	345091	1			T28	742		T31	448		T33	57

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7692265

1

T17

7

T28

35317

T29

9

values[0x0]

all_enables

biggest_size

16383396

1

T28

14322

T29

2

T30

4

values[0x1]

all_enables

biggest_size

9696451

1

T17

1

T28

7677

T29

3