Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T74,T105
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13082	0	0
DisabledNoTrigBkwd_A	2147483647	839432	0	0
DisabledNoTrigFwd_A	2147483647	1513344487	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13082	0	0
T9	403312	0	0	0
T23	1099	361	0	0
T40	33388	0	0	0
T63	737004	0	0	0
T74	3525	603	0	0
T75	404030	0	0	0
T94	16571	0	0	0
T105	1293	510	0	0
T112	42289	0	0	0
T191	0	702	0	0
T192	0	507	0	0
T193	0	1185	0	0
T194	2509	246	0	0
T195	1160	463	0	0
T196	0	669	0	0
T197	0	631	0	0
T198	0	668	0	0
T199	0	321	0	0
T200	0	699	0	0
T201	0	1637	0	0
T202	0	864	0	0
T203	0	238	0	0
T204	0	935	0	0
T205	0	259	0	0
T206	0	1327	0	0
T207	0	257	0	0
T208	6700	0	0	0
T209	468718	0	0	0
T210	4627	0	0	0
T211	1194	0	0	0
T212	17107	0	0	0
T213	325076	0	0	0
T214	31246	0	0	0
T215	146478	0	0	0
T216	175035	0	0	0
T217	70678	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	839432	0	0
T1	2905032	8636	0	0
T2	108556	0	0	0
T3	1720452	1255	0	0
T4	3822676	2389	0	0
T5	461464	3658	0	0
T6	0	1908	0	0
T7	0	2034	0	0
T8	0	487	0	0
T18	572164	1458	0	0
T19	0	3388	0	0
T20	0	4114	0	0
T22	280812	1029	0	0
T23	4396	6	0	0
T24	69680	6	0	0
T25	78156	0	0	0
T26	0	9	0	0
T53	0	166	0	0
T54	0	44	0	0
T55	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513344487	0	0
T1	2905032	1499348	0	0
T2	108556	81817	0	0
T3	1720452	1435339	0	0
T4	3822676	968365	0	0
T5	461464	131789	0	0
T18	572164	427818	0	0
T22	280812	148752	0	0
T23	4396	2416	0	0
T24	69680	54427	0	0
T25	78156	29509	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T195,T198
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708017839	1874	0	0
DisabledNoTrigBkwd_A	708017839	224424	0	0
DisabledNoTrigFwd_A	708017839	339881331	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1874	0	0
T94	16571	0	0	0
T112	42289	0	0	0
T194	2509	246	0	0
T195	1160	463	0	0
T198	0	668	0	0
T203	0	238	0	0
T205	0	259	0	0
T212	17107	0	0	0
T213	325076	0	0	0
T214	31246	0	0	0
T215	146478	0	0	0
T216	175035	0	0	0
T217	70678	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	224424	0	0
T1	726258	1928	0	0
T2	27139	0	0	0
T3	430113	8	0	0
T4	955669	655	0	0
T5	115366	1062	0	0
T7	0	1078	0	0
T18	143041	1448	0	0
T19	0	1895	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	6	0	0
T25	19539	0	0	0
T53	0	99	0	0
T55	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	339881331	0	0
T1	726258	466789	0	0
T2	27139	27077	0	0
T3	430113	385292	0	0
T4	955669	8746	0	0
T5	115366	4276	0	0
T18	143041	582	0	0
T22	70203	65244	0	0
T23	1099	598	0	0
T24	17420	2368	0	0
T25	19539	2080	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T105,T191
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708017839	4368	0	0
DisabledNoTrigBkwd_A	708017839	206465	0	0
DisabledNoTrigFwd_A	708017839	395887621	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	4368	0	0
T9	403312	0	0	0
T40	33388	0	0	0
T63	737004	0	0	0
T74	3525	603	0	0
T75	404030	0	0	0
T105	1293	510	0	0
T191	0	702	0	0
T193	0	1185	0	0
T196	0	669	0	0
T200	0	699	0	0
T208	6700	0	0	0
T209	468718	0	0	0
T210	4627	0	0	0
T211	1194	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	206465	0	0
T1	726258	3462	0	0
T2	27139	0	0	0
T3	430113	5	0	0
T4	955669	908	0	0
T5	115366	1142	0	0
T8	0	487	0	0
T18	143041	0	0	0
T19	0	587	0	0
T20	0	2692	0	0
T22	70203	8	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	60	0	0
T54	0	38	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	395887621	0	0
T1	726258	269804	0	0
T2	27139	586	0	0
T3	430113	392974	0	0
T4	955669	2800	0	0
T5	115366	2171	0	0
T18	143041	143031	0	0
T22	70203	48776	0	0
T23	1099	602	0	0
T24	17420	17353	0	0
T25	19539	12644	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T199,T202
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708017839	1546	0	0
DisabledNoTrigBkwd_A	708017839	205628	0	0
DisabledNoTrigFwd_A	708017839	388220274	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1546	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T23	1099	361	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T53	231641	0	0	0
T54	20797	0	0	0
T55	13373	0	0	0
T199	0	321	0	0
T202	0	864	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	205628	0	0
T1	726258	3236	0	0
T2	27139	0	0	0
T3	430113	503	0	0
T4	955669	826	0	0
T5	115366	0	0	0
T6	0	1908	0	0
T18	143041	9	0	0
T19	0	299	0	0
T22	70203	17	0	0
T23	1099	6	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	7	0	0
T54	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	388220274	0	0
T1	726258	212950	0	0
T2	27139	27077	0	0
T3	430113	325225	0	0
T4	955669	2804	0	0
T5	115366	115254	0	0
T18	143041	141539	0	0
T22	70203	7618	0	0
T23	1099	606	0	0
T24	17420	17353	0	0
T25	19539	12660	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T197,T201
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	708017839	5294	0	0
DisabledNoTrigBkwd_A	708017839	202915	0	0
DisabledNoTrigFwd_A	708017839	389355261	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	5294	0	0
T92	258544	0	0	0
T192	4016	507	0	0
T197	0	631	0	0
T201	0	1637	0	0
T204	0	935	0	0
T206	0	1327	0	0
T207	0	257	0	0
T218	545213	0	0	0
T219	104555	0	0	0
T220	285307	0	0	0
T221	3822	0	0	0
T222	20058	0	0	0
T223	3162	0	0	0
T224	20970	0	0	0
T225	19669	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	202915	0	0
T1	726258	10	0	0
T2	27139	0	0	0
T3	430113	739	0	0
T4	955669	0	0	0
T5	115366	1454	0	0
T7	0	956	0	0
T18	143041	1	0	0
T19	0	607	0	0
T20	0	1422	0	0
T22	70203	1004	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	2	0	0
T53	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	389355261	0	0
T1	726258	549805	0	0
T2	27139	27077	0	0
T3	430113	331848	0	0
T4	955669	954015	0	0
T5	115366	10088	0	0
T18	143041	142666	0	0
T22	70203	27114	0	0
T23	1099	610	0	0
T24	17420	17353	0	0
T25	19539	2125	0	0