Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T23,T5
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T4

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T22,T25
1	0	Covered	T3,T19,T20

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T19,T20

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T37,T38
1	1	Covered	T1,T22,T25

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T22

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T22

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T24

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T17
IdleSt	175	Covered	T17
Phase0St	146	Covered	T17
Phase1St	192	Covered	T17
Phase2St	209	Covered	T17
Phase3St	227	Covered	T17
TerminalSt	243	Covered	T17
TimeoutSt	153	Covered	T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T17
IdleSt->Phase0St	146	Covered	T17
IdleSt->TimeoutSt	153	Covered	T17
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T17
Phase0St->Phase1St	192	Covered	T17
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T17
Phase1St->Phase2St	209	Covered	T17
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T17
Phase2St->Phase3St	227	Covered	T17
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T17
Phase3St->TerminalSt	243	Covered	T17
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T17
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T17
TimeoutSt->Phase0St	166	Covered	T17

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T39
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T40,T41
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T10,T42
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T43,T44
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	903	0	0
CheckAccumTrig0_A	2147483647	2333	0	0
CheckAccumTrig1_A	2147483647	109	0	0
CheckClr_A	2147483647	1038	0	0
CheckEn_A	2147483647	1179449380	0	0
CheckPhase0_A	2147483647	2681	0	0
CheckPhase1_A	2147483647	2642	0	0
CheckPhase2_A	2147483647	2598	0	0
CheckPhase3_A	2147483647	2555	0	0
CheckTimeout0_A	2147483647	6562	0	0
CheckTimeoutSt1_A	2147483647	664224	0	0
CheckTimeoutSt2_A	2147483647	6185	0	0
CheckTimeoutStTrig_A	2147483647	268	0	0
ErrorStAllEscAsserted_A	2147483647	5011	0	0
ErrorStIsTerminal_A	2147483647	4171	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	903	0	0
T8	823092	0	0	0
T14	123600	261	0	0
T15	0	159	0	0
T16	0	119	0	0
T21	603196	0	0	0
T27	2200968	0	0	0
T45	0	241	0	0
T46	0	123	0	0
T47	447800	0	0	0
T48	139068	0	0	0
T49	1316932	0	0	0
T50	1029276	0	0	0
T51	181596	0	0	0
T52	163772	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2333	0	0
T1	2905032	13	0	0
T2	108556	0	0	0
T3	1720452	4	0	0
T4	3822676	4	0	0
T5	461464	5	0	0
T6	0	1	0	0
T7	0	13	0	0
T8	0	2	0	0
T18	572164	7	0	0
T19	0	16	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	280812	4	0	0
T23	4396	1	0	0
T24	69680	5	0	0
T25	78156	0	0	0
T26	0	4	0	0
T53	0	7	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T7	647042	0	0	0
T18	143041	0	0	0
T19	602640	1	0	0
T20	104051	1	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T39	2026	0	0	0
T41	0	1	0	0
T43	276814	0	0	0
T51	45399	1	0	0
T52	40943	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	816077	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	110421	0	0	0
T73	2891	0	0	0
T74	3525	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1038	0	0
T1	1452516	2	0	0
T2	54278	0	0	0
T3	860226	1	0	0
T4	2867007	1	0	0
T5	461464	1	0	0
T6	226790	0	0	0
T7	0	8	0	0
T10	0	1	0	0
T18	572164	4	0	0
T19	0	1	0	0
T20	0	2	0	0
T22	280812	2	0	0
T23	4396	0	0	0
T24	69680	5	0	0
T25	78156	0	0	0
T26	55994	2	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	3	0	0
T43	0	2	0	0
T48	0	1	0	0
T51	0	3	0	0
T53	463282	0	0	0
T54	20797	2	0	0
T75	0	1	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1179449380	0	0
T1	2905032	1055122	0	0
T2	108556	81814	0	0
T3	1720452	1626941	0	0
T4	3822676	968364	0	0
T5	461464	131789	0	0
T18	572164	292440	0	0
T22	280812	54721	0	0
T23	4396	2416	0	0
T24	69680	54424	0	0
T25	78156	29509	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T1	2905032	13	0	0
T2	108556	0	0	0
T3	1720452	5	0	0
T4	3822676	4	0	0
T5	461464	5	0	0
T6	0	1	0	0
T7	0	5	0	0
T8	0	1	0	0
T18	572164	7	0	0
T19	0	12	0	0
T20	0	3	0	0
T22	280812	7	0	0
T23	4396	1	0	0
T24	69680	5	0	0
T25	78156	1	0	0
T26	0	4	0	0
T53	0	9	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2642	0	0
T1	2905032	13	0	0
T2	108556	0	0	0
T3	1720452	5	0	0
T4	3822676	4	0	0
T5	461464	5	0	0
T6	0	1	0	0
T7	0	5	0	0
T8	0	1	0	0
T18	572164	7	0	0
T19	0	12	0	0
T20	0	3	0	0
T22	280812	7	0	0
T23	4396	1	0	0
T24	69680	4	0	0
T25	78156	1	0	0
T26	0	4	0	0
T53	0	9	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T1	2905032	13	0	0
T2	108556	0	0	0
T3	1720452	5	0	0
T4	3822676	4	0	0
T5	461464	5	0	0
T6	0	1	0	0
T7	0	5	0	0
T8	0	1	0	0
T18	572164	7	0	0
T19	0	12	0	0
T20	0	3	0	0
T22	280812	7	0	0
T23	4396	1	0	0
T24	69680	4	0	0
T25	78156	1	0	0
T26	0	4	0	0
T53	0	9	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2555	0	0
T1	2905032	13	0	0
T2	108556	0	0	0
T3	1720452	5	0	0
T4	3822676	4	0	0
T5	461464	5	0	0
T6	0	1	0	0
T7	0	5	0	0
T8	0	1	0	0
T18	572164	7	0	0
T19	0	12	0	0
T20	0	3	0	0
T22	280812	7	0	0
T23	4396	1	0	0
T24	69680	4	0	0
T25	78156	1	0	0
T26	0	4	0	0
T53	0	9	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6562	0	0
T1	2905032	952	0	0
T2	108556	0	0	0
T3	1720452	293	0	0
T4	3822676	5	0	0
T5	461464	3	0	0
T18	572164	1	0	0
T19	0	140	0	0
T20	0	7	0	0
T22	280812	4	0	0
T23	4396	0	0	0
T24	69680	0	0	0
T25	78156	8	0	0
T27	0	3	0	0
T43	0	14	0	0
T47	0	32	0	0
T53	0	574	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	664224	0	0
T1	2905032	58329	0	0
T2	108556	0	0	0
T3	1720452	25485	0	0
T4	3822676	179	0	0
T5	461464	150	0	0
T18	572164	113	0	0
T19	0	14917	0	0
T20	0	722	0	0
T22	280812	1681	0	0
T23	4396	0	0	0
T24	69680	0	0	0
T25	78156	1370	0	0
T27	0	236	0	0
T43	0	2019	0	0
T47	0	7056	0	0
T51	0	144	0	0
T53	0	47197	0	0
T77	0	402	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6185	0	0
T1	2905032	951	0	0
T2	108556	0	0	0
T3	1720452	291	0	0
T4	3822676	5	0	0
T5	461464	3	0	0
T18	572164	1	0	0
T19	0	137	0	0
T20	0	6	0	0
T22	280812	1	0	0
T23	4396	0	0	0
T24	69680	0	0	0
T25	78156	7	0	0
T27	0	7	0	0
T43	0	15	0	0
T47	0	31	0	0
T51	0	1	0	0
T53	0	572	0	0
T56	0	1	0	0
T75	0	5	0	0
T77	0	6	0	0
T78	0	1	0	0
T79	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268	0	0
T1	726258	1	0	0
T2	27139	0	0	0
T3	430113	0	0	0
T4	955669	0	0	0
T5	230732	0	0	0
T6	113395	0	0	0
T7	647042	0	0	0
T18	286082	0	0	0
T19	602640	1	0	0
T20	104051	0	0	0
T22	140406	2	0	0
T23	2198	0	0	0
T24	34840	0	0	0
T25	39078	1	0	0
T26	27997	0	0	0
T42	0	2	0	0
T43	0	3	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	463282	2	0	0
T54	41594	0	0	0
T55	13373	0	0	0
T57	0	1	0	0
T58	246994	5	0	0
T61	0	1	0	0
T64	0	2	0	0
T72	110421	0	0	0
T73	2891	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5011	0	0
T8	823092	0	0	0
T14	123600	1397	0	0
T15	0	751	0	0
T16	0	682	0	0
T21	603196	0	0	0
T27	2200968	0	0	0
T45	0	1476	0	0
T46	0	705	0	0
T47	447800	0	0	0
T48	139068	0	0	0
T49	1316932	0	0	0
T50	1029276	0	0	0
T51	181596	0	0	0
T52	163772	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4171	0	0
T8	823092	0	0	0
T14	123600	1157	0	0
T15	0	631	0	0
T16	0	562	0	0
T21	603196	0	0	0
T27	2200968	0	0	0
T45	0	1236	0	0
T46	0	585	0	0
T47	447800	0	0	0
T48	139068	0	0	0
T49	1316932	0	0	0
T50	1029276	0	0	0
T51	181596	0	0	0
T52	163772	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2905032	2904980	0	0
T2	108556	108308	0	0
T3	1720452	1720372	0	0
T4	3822676	3822336	0	0
T5	461464	461416	0	0
T18	572164	572124	0	0
T22	280812	280488	0	0
T23	4396	4016	0	0
T24	69680	69412	0	0
T25	78156	77796	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T22

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T54,T19
1	1	0	Covered	T1,T3,T22
1	1	1	Covered	T1,T3,T4

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T22,T19
1	0	Covered	T3,T41,T57

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T41,T57

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T22,T19

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T8,T74

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T22,T53

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T3,T22

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T5

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T22,T53,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T17
IdleSt	175	Covered	T17
Phase0St	146	Covered	T17
Phase1St	192	Covered	T17
Phase2St	209	Covered	T17
Phase3St	227	Covered	T17
TerminalSt	243	Covered	T17
TimeoutSt	153	Covered	T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T17
IdleSt->Phase0St	146	Covered	T17
IdleSt->TimeoutSt	153	Covered	T17
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T17
Phase0St->Phase1St	192	Covered	T17
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T17
Phase1St->Phase2St	209	Covered	T17
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T17
Phase2St->Phase3St	227	Covered	T17
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T17
Phase3St->TerminalSt	243	Covered	T17
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T17
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T17
TimeoutSt->Phase0St	166	Covered	T17

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T89,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T41,T65,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T64,T67
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T43,T83,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T22,T54
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708017839	250	0	0
CheckAccumTrig0_A	708017839	504	0	0
CheckAccumTrig1_A	708017839	31	0	0
CheckClr_A	708017839	219	0	0
CheckEn_A	707851430	322716761	0	0
CheckPhase0_A	708017839	586	0	0
CheckPhase1_A	708017839	575	0	0
CheckPhase2_A	708017839	560	0	0
CheckPhase3_A	708017839	553	0	0
CheckTimeout0_A	708017839	1730	0	0
CheckTimeoutSt1_A	708017839	170070	0	0
CheckTimeoutSt2_A	708017839	1641	0	0
CheckTimeoutStTrig_A	708017839	58	0	0
ErrorStAllEscAsserted_A	708017839	1313	0	0
ErrorStIsTerminal_A	708017839	1103	0	0
u_state_regs_A	708017839	707856020	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	250	0	0
T8	205773	0	0	0
T14	30900	87	0	0
T15	0	41	0	0
T16	0	29	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	54	0	0
T46	0	39	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	504	0	0
T1	726258	3	0	0
T2	27139	0	0	0
T3	430113	0	0	0
T4	955669	2	0	0
T5	115366	2	0	0
T8	0	1	0	0
T18	143041	0	0	0
T19	0	5	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	31	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T41	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	219	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T53	231641	0	0	0
T54	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707851430	322716761	0	0
T1	726258	169840	0	0
T2	27139	586	0	0
T3	430113	331067	0	0
T4	955669	2800	0	0
T5	115366	2171	0	0
T18	143041	143031	0	0
T22	70203	10425	0	0
T23	1099	602	0	0
T24	17420	17352	0	0
T25	19539	12644	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	586	0	0
T1	726258	4	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	2	0	0
T5	115366	2	0	0
T8	0	1	0	0
T18	143041	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T22	70203	3	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	575	0	0
T1	726258	4	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	2	0	0
T5	115366	2	0	0
T8	0	1	0	0
T18	143041	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T22	70203	3	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	560	0	0
T1	726258	4	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	2	0	0
T5	115366	2	0	0
T8	0	1	0	0
T18	143041	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T22	70203	3	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	553	0	0
T1	726258	4	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	2	0	0
T5	115366	2	0	0
T8	0	1	0	0
T18	143041	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T22	70203	3	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1730	0	0
T1	726258	466	0	0
T2	27139	0	0	0
T3	430113	53	0	0
T4	955669	2	0	0
T5	115366	1	0	0
T18	143041	0	0	0
T19	0	30	0	0
T20	0	1	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	2	0	0
T47	0	11	0	0
T53	0	288	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	170070	0	0
T1	726258	27934	0	0
T2	27139	0	0	0
T3	430113	4829	0	0
T4	955669	77	0	0
T5	115366	40	0	0
T18	143041	0	0	0
T19	0	3207	0	0
T20	0	24	0	0
T22	70203	14	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	339	0	0
T47	0	2494	0	0
T53	0	25503	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1641	0	0
T1	726258	465	0	0
T2	27139	0	0	0
T3	430113	52	0	0
T4	955669	2	0	0
T5	115366	1	0	0
T18	143041	0	0	0
T19	0	29	0	0
T20	0	1	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	2	0	0
T27	0	5	0	0
T47	0	11	0	0
T53	0	288	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	58	0	0
T1	726258	1	0	0
T2	27139	0	0	0
T3	430113	0	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T18	143041	0	0	0
T19	0	1	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T43	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1313	0	0
T8	205773	0	0	0
T14	30900	357	0	0
T15	0	199	0	0
T16	0	173	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	401	0	0
T46	0	183	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1103	0	0
T8	205773	0	0	0
T14	30900	297	0	0
T15	0	169	0	0
T16	0	143	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	341	0	0
T46	0	153	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	707856020	0	0
T1	726258	726245	0	0
T2	27139	27077	0	0
T3	430113	430093	0	0
T4	955669	955584	0	0
T5	115366	115354	0	0
T18	143041	143031	0	0
T22	70203	70122	0	0
T23	1099	1004	0	0
T24	17420	17353	0	0
T25	19539	19449	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T23,T5
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T4

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T53,T58,T61
1	0	Covered	T62,T64,T69

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T62,T64,T69

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T53,T58,T61

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T22,T23,T18

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T18,T54,T19

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T23
1	Covered	T1,T3,T4

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T7,T50

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T22,T23

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T23,T18,T26

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T23

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T17
IdleSt	175	Covered	T17
Phase0St	146	Covered	T17
Phase1St	192	Covered	T17
Phase2St	209	Covered	T17
Phase3St	227	Covered	T17
TerminalSt	243	Covered	T17
TimeoutSt	153	Covered	T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T17
IdleSt->Phase0St	146	Covered	T17
IdleSt->TimeoutSt	153	Covered	T17
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T17
Phase0St->Phase1St	192	Covered	T17
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T17
Phase1St->Phase2St	209	Covered	T17
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T17
Phase2St->Phase3St	227	Covered	T17
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T17
Phase3St->TerminalSt	243	Covered	T17
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T17
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T17
TimeoutSt->Phase0St	166	Covered	T17

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T53,T58,T61
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T41,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T94,T68
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T64,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T61,T70,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T26,T54
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708017839	213	0	0
CheckAccumTrig0_A	708017839	504	0	0
CheckAccumTrig1_A	708017839	13	0	0
CheckClr_A	708017839	219	0	0
CheckEn_A	707851430	293702857	0	0
CheckPhase0_A	708017839	579	0	0
CheckPhase1_A	708017839	574	0	0
CheckPhase2_A	708017839	565	0	0
CheckPhase3_A	708017839	554	0	0
CheckTimeout0_A	708017839	1634	0	0
CheckTimeoutSt1_A	708017839	168926	0	0
CheckTimeoutSt2_A	708017839	1548	0	0
CheckTimeoutStTrig_A	708017839	73	0	0
ErrorStAllEscAsserted_A	708017839	1222	0	0
ErrorStIsTerminal_A	708017839	1012	0	0
u_state_regs_A	708017839	707856020	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	213	0	0
T8	205773	0	0	0
T14	30900	55	0	0
T15	0	26	0	0
T16	0	24	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	79	0	0
T46	0	29	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	504	0	0
T1	726258	3	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	0	1	0	0
T18	143041	2	0	0
T19	0	4	0	0
T22	70203	1	0	0
T23	1099	1	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	3	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	13	0	0
T15	15858	0	0	0
T62	816077	1	0	0
T63	737004	0	0	0
T64	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T89	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	3	0	0
T99	0	1	0	0
T100	32817	0	0	0
T101	12703	0	0	0
T102	147189	0	0	0
T103	31673	0	0	0
T104	502834	0	0	0
T105	1293	0	0	0
T106	217627	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	219	0	0
T1	726258	1	0	0
T2	27139	0	0	0
T3	430113	0	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T18	143041	1	0	0
T20	0	1	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T54	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707851430	293702857	0	0
T1	726258	212950	0	0
T2	27139	27076	0	0
T3	430113	325225	0	0
T4	955669	2804	0	0
T5	115366	115254	0	0
T18	143041	6161	0	0
T22	70203	2760	0	0
T23	1099	606	0	0
T24	17420	17352	0	0
T25	19539	12660	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	579	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	0	1	0	0
T18	143041	2	0	0
T22	70203	1	0	0
T23	1099	1	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	574	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	0	1	0	0
T18	143041	2	0	0
T22	70203	1	0	0
T23	1099	1	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	565	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	0	1	0	0
T18	143041	2	0	0
T22	70203	1	0	0
T23	1099	1	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	554	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	1	0	0
T5	115366	0	0	0
T6	0	1	0	0
T18	143041	2	0	0
T22	70203	1	0	0
T23	1099	1	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1634	0	0
T1	726258	19	0	0
T2	27139	0	0	0
T3	430113	88	0	0
T4	955669	3	0	0
T5	115366	0	0	0
T18	143041	1	0	0
T19	0	39	0	0
T20	0	1	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T27	0	1	0	0
T47	0	10	0	0
T53	0	1	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	168926	0	0
T1	726258	1561	0	0
T2	27139	0	0	0
T3	430113	7983	0	0
T4	955669	102	0	0
T5	115366	0	0	0
T18	143041	113	0	0
T19	0	2942	0	0
T20	0	197	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T27	0	94	0	0
T47	0	2284	0	0
T53	0	48	0	0
T77	0	402	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1548	0	0
T1	726258	19	0	0
T2	27139	0	0	0
T3	430113	88	0	0
T4	955669	3	0	0
T5	115366	0	0	0
T18	143041	1	0	0
T19	0	39	0	0
T20	0	1	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T27	0	1	0	0
T47	0	10	0	0
T77	0	6	0	0
T79	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	73	0	0
T7	647042	0	0	0
T19	602640	0	0	0
T20	104051	0	0	0
T42	0	2	0	0
T53	231641	1	0	0
T54	20797	0	0	0
T55	13373	0	0	0
T58	246994	5	0	0
T61	0	1	0	0
T72	110421	0	0	0
T73	2891	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	173174	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1222	0	0
T8	205773	0	0	0
T14	30900	342	0	0
T15	0	171	0	0
T16	0	170	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	353	0	0
T46	0	186	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1012	0	0
T8	205773	0	0	0
T14	30900	282	0	0
T15	0	141	0	0
T16	0	140	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	293	0	0
T46	0	156	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	707856020	0	0
T1	726258	726245	0	0
T2	27139	27077	0	0
T3	430113	430093	0	0
T4	955669	955584	0	0
T5	115366	115354	0	0
T18	143041	143031	0	0
T22	70203	70122	0	0
T23	1099	1004	0	0
T24	17420	17353	0	0
T25	19539	19449	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T19,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T22

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T22
0	1	Covered	T22,T25,T53
1	0	Covered	T19,T20,T51

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T20,T51

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T38
1	1	Covered	T22,T25,T53

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T24

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T22
1	Covered	T1,T4,T24

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T22

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T24,T25,T53

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T22,T24

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T17
IdleSt	175	Covered	T17
Phase0St	146	Covered	T17
Phase1St	192	Covered	T17
Phase2St	209	Covered	T17
Phase3St	227	Covered	T17
TerminalSt	243	Covered	T17
TimeoutSt	153	Covered	T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T17
IdleSt->Phase0St	146	Covered	T17
IdleSt->TimeoutSt	153	Covered	T17
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T17
Phase0St->Phase1St	192	Covered	T17
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T17
Phase1St->Phase2St	209	Covered	T17
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T17
Phase2St->Phase3St	227	Covered	T17
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T17
Phase3St->TerminalSt	243	Covered	T17
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T17
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T17
TimeoutSt->Phase0St	166	Covered	T17

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T25,T53
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T39,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T110,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T42,T112,T113
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T44,T114
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T24,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708017839	209	0	0
CheckAccumTrig0_A	708017839	846	0	0
CheckAccumTrig1_A	708017839	48	0	0
CheckClr_A	708017839	388	0	0
CheckEn_A	707851430	233166761	0	0
CheckPhase0_A	708017839	953	0	0
CheckPhase1_A	708017839	940	0	0
CheckPhase2_A	708017839	924	0	0
CheckPhase3_A	708017839	908	0	0
CheckTimeout0_A	708017839	1342	0	0
CheckTimeoutSt1_A	708017839	145849	0	0
CheckTimeoutSt2_A	708017839	1225	0	0
CheckTimeoutStTrig_A	708017839	69	0	0
ErrorStAllEscAsserted_A	708017839	1241	0	0
ErrorStIsTerminal_A	708017839	1031	0	0
u_state_regs_A	708017839	707856020	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	209	0	0
T8	205773	0	0	0
T14	30900	52	0	0
T15	0	56	0	0
T16	0	29	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	39	0	0
T46	0	33	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	846	0	0
T1	726258	5	0	0
T2	27139	0	0	0
T3	430113	3	0	0
T4	955669	1	0	0
T5	115366	2	0	0
T7	0	8	0	0
T18	143041	4	0	0
T19	0	2	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	5	0	0
T25	19539	0	0	0
T53	0	3	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	48	0	0
T7	647042	0	0	0
T19	602640	1	0	0
T20	104051	1	0	0
T39	2026	0	0	0
T43	276814	0	0	0
T51	45399	1	0	0
T52	40943	0	0	0
T56	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T72	110421	0	0	0
T73	2891	0	0	0
T74	3525	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	388	0	0
T1	726258	1	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	7	0	0
T18	143041	3	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	5	0	0
T25	19539	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T48	0	1	0	0
T51	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707851430	233166761	0	0
T1	726258	457936	0	0
T2	27139	27076	0	0
T3	430113	638801	0	0
T4	955669	8746	0	0
T5	115366	4276	0	0
T18	143041	582	0	0
T22	70203	14422	0	0
T23	1099	598	0	0
T24	17420	2368	0	0
T25	19539	2080	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	953	0	0
T1	726258	5	0	0
T2	27139	0	0	0
T3	430113	2	0	0
T4	955669	1	0	0
T5	115366	2	0	0
T18	143041	4	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	5	0	0
T25	19539	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	940	0	0
T1	726258	5	0	0
T2	27139	0	0	0
T3	430113	2	0	0
T4	955669	1	0	0
T5	115366	2	0	0
T18	143041	4	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	4	0	0
T25	19539	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	924	0	0
T1	726258	5	0	0
T2	27139	0	0	0
T3	430113	2	0	0
T4	955669	1	0	0
T5	115366	2	0	0
T18	143041	4	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	4	0	0
T25	19539	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	908	0	0
T1	726258	5	0	0
T2	27139	0	0	0
T3	430113	2	0	0
T4	955669	1	0	0
T5	115366	2	0	0
T18	143041	4	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	4	0	0
T25	19539	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1342	0	0
T1	726258	3	0	0
T2	27139	0	0	0
T3	430113	77	0	0
T4	955669	0	0	0
T5	115366	2	0	0
T18	143041	0	0	0
T19	0	42	0	0
T20	0	1	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	3	0	0
T27	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	145849	0	0
T1	726258	182	0	0
T2	27139	0	0	0
T3	430113	6300	0	0
T4	955669	0	0	0
T5	115366	110	0	0
T18	143041	0	0	0
T19	0	5551	0	0
T22	70203	812	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	513	0	0
T27	0	64	0	0
T47	0	89	0	0
T51	0	144	0	0
T53	0	103	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1225	0	0
T1	726258	3	0	0
T2	27139	0	0	0
T3	430113	77	0	0
T4	955669	0	0	0
T5	115366	2	0	0
T18	143041	0	0	0
T19	0	41	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	2	0	0
T27	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T56	0	1	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	69	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	1	0	0
T26	27997	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	231641	1	0	0
T54	20797	0	0	0
T64	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1241	0	0
T8	205773	0	0	0
T14	30900	383	0	0
T15	0	195	0	0
T16	0	168	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	340	0	0
T46	0	155	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1031	0	0
T8	205773	0	0	0
T14	30900	323	0	0
T15	0	165	0	0
T16	0	138	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	280	0	0
T46	0	125	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	707856020	0	0
T1	726258	726245	0	0
T2	27139	27077	0	0
T3	430113	430093	0	0
T4	955669	955584	0	0
T5	115366	115354	0	0
T18	143041	143031	0	0
T22	70203	70122	0	0
T23	1099	1004	0	0
T24	17420	17353	0	0
T25	19539	19449	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T22
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T22

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T22,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T6,T53
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T22

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T22
0	1	Covered	T22,T19,T27
1	0	Covered	T3,T63,T42

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T63,T42

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T37
1	1	Covered	T22,T19,T27

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T5
1	Covered	T1,T3,T19

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T22,T19,T20

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T22
1	Covered	T5,T53,T19

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T22
1	Covered	T1,T18,T26

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T22

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T22,T5,T53

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T17
IdleSt	175	Covered	T17
Phase0St	146	Covered	T17
Phase1St	192	Covered	T17
Phase2St	209	Covered	T17
Phase3St	227	Covered	T17
TerminalSt	243	Covered	T17
TimeoutSt	153	Covered	T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T17
IdleSt->Phase0St	146	Covered	T17
IdleSt->TimeoutSt	153	Covered	T17
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T17
Phase0St->Phase1St	192	Covered	T17
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T17
Phase1St->Phase2St	209	Covered	T17
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T17
Phase2St->Phase3St	227	Covered	T17
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T17
Phase3St->TerminalSt	243	Covered	T17
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T17
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T17
TimeoutSt->Phase0St	166	Covered	T17

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T116,T88,T68
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T117,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T119,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T22,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	708017839	231	0	0
CheckAccumTrig0_A	708017839	479	0	0
CheckAccumTrig1_A	708017839	17	0	0
CheckClr_A	708017839	212	0	0
CheckEn_A	707851430	329863001	0	0
CheckPhase0_A	708017839	563	0	0
CheckPhase1_A	708017839	553	0	0
CheckPhase2_A	708017839	549	0	0
CheckPhase3_A	708017839	540	0	0
CheckTimeout0_A	708017839	1856	0	0
CheckTimeoutSt1_A	708017839	179379	0	0
CheckTimeoutSt2_A	708017839	1771	0	0
CheckTimeoutStTrig_A	708017839	68	0	0
ErrorStAllEscAsserted_A	708017839	1235	0	0
ErrorStIsTerminal_A	708017839	1025	0	0
u_state_regs_A	708017839	707856020	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	231	0	0
T8	205773	0	0	0
T14	30900	67	0	0
T15	0	36	0	0
T16	0	37	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	69	0	0
T46	0	22	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	479	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	0	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	5	0	0
T8	0	1	0	0
T18	143041	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	1	0	0
T53	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	17	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T22	70203	0	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T42	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T94	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	212	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T7	0	4	0	0
T10	0	1	0	0
T18	143041	1	0	0
T19	0	2	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T27	0	1	0	0
T41	0	1	0	0
T53	231641	0	0	0
T54	20797	0	0	0
T57	0	1	0	0
T76	0	5	0	0
T125	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707851430	329863001	0	0
T1	726258	214396	0	0
T2	27139	27076	0	0
T3	430113	331848	0	0
T4	955669	954014	0	0
T5	115366	10088	0	0
T18	143041	142666	0	0
T22	70203	27114	0	0
T23	1099	610	0	0
T24	17420	17352	0	0
T25	19539	2125	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	563	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	5	0	0
T18	143041	1	0	0
T19	0	6	0	0
T20	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	1	0	0
T53	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	553	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	5	0	0
T18	143041	1	0	0
T19	0	6	0	0
T20	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	1	0	0
T53	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	549	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	5	0	0
T18	143041	1	0	0
T19	0	6	0	0
T20	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	1	0	0
T53	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	540	0	0
T1	726258	2	0	0
T2	27139	0	0	0
T3	430113	1	0	0
T4	955669	0	0	0
T5	115366	1	0	0
T7	0	5	0	0
T18	143041	1	0	0
T19	0	6	0	0
T20	0	1	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	0	1	0	0
T53	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1856	0	0
T1	726258	464	0	0
T2	27139	0	0	0
T3	430113	75	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T18	143041	0	0	0
T19	0	29	0	0
T20	0	4	0	0
T22	70203	2	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	3	0	0
T27	0	1	0	0
T43	0	14	0	0
T47	0	10	0	0
T53	0	284	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	179379	0	0
T1	726258	28652	0	0
T2	27139	0	0	0
T3	430113	6373	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T18	143041	0	0	0
T19	0	3217	0	0
T20	0	501	0	0
T22	70203	855	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	518	0	0
T27	0	78	0	0
T43	0	2019	0	0
T47	0	2189	0	0
T53	0	21543	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1771	0	0
T1	726258	464	0	0
T2	27139	0	0	0
T3	430113	74	0	0
T4	955669	0	0	0
T5	115366	0	0	0
T18	143041	0	0	0
T19	0	28	0	0
T20	0	4	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	3	0	0
T43	0	14	0	0
T47	0	10	0	0
T53	0	284	0	0
T75	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	68	0	0
T5	115366	0	0	0
T6	113395	0	0	0
T18	143041	0	0	0
T19	0	1	0	0
T22	70203	1	0	0
T23	1099	0	0	0
T24	17420	0	0	0
T25	19539	0	0	0
T26	27997	0	0	0
T27	0	1	0	0
T37	0	1	0	0
T53	231641	0	0	0
T54	20797	0	0	0
T57	0	1	0	0
T61	0	1	0	0
T100	0	1	0	0
T107	0	2	0	0
T108	0	2	0	0
T126	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1235	0	0
T8	205773	0	0	0
T14	30900	315	0	0
T15	0	186	0	0
T16	0	171	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	382	0	0
T46	0	181	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	1025	0	0
T8	205773	0	0	0
T14	30900	255	0	0
T15	0	156	0	0
T16	0	141	0	0
T21	150799	0	0	0
T27	550242	0	0	0
T45	0	322	0	0
T46	0	151	0	0
T47	111950	0	0	0
T48	34767	0	0	0
T49	329233	0	0	0
T50	257319	0	0	0
T51	45399	0	0	0
T52	40943	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708017839	707856020	0	0
T1	726258	726245	0	0
T2	27139	27077	0	0
T3	430113	430093	0	0
T4	955669	955584	0	0
T5	115366	115354	0	0
T18	143041	143031	0	0
T22	70203	70122	0	0
T23	1099	1004	0	0
T24	17420	17353	0	0
T25	19539	19449	0	0