Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T222,T223
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13793	0	0
DisabledNoTrigBkwd_A	2147483647	827340	0	0
DisabledNoTrigFwd_A	2147483647	1609051997	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13793	0	0
T18	1474	661	0	0
T33	12300	0	0	0
T51	330967	0	0	0
T52	350750	0	0	0
T72	32895	0	0	0
T73	22178	0	0	0
T78	23234	0	0	0
T79	1430	0	0	0
T80	192522	0	0	0
T138	0	839	0	0
T145	126142	0	0	0
T222	1151	437	0	0
T223	0	341	0	0
T224	0	313	0	0
T225	0	947	0	0
T226	0	557	0	0
T227	0	699	0	0
T228	0	893	0	0
T229	0	1018	0	0
T230	0	466	0	0
T231	0	828	0	0
T232	0	960	0	0
T233	1123	382	0	0
T234	3574	1191	0	0
T235	0	1235	0	0
T236	0	1056	0	0
T237	0	122	0	0
T238	0	494	0	0
T239	0	354	0	0
T240	611080	0	0	0
T241	60642	0	0	0
T242	496708	0	0	0
T243	30239	0	0	0
T244	286951	0	0	0
T245	39691	0	0	0
T246	344769	0	0	0
T247	116423	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	827340	0	0
T1	91935	11	0	0
T2	440472	29	0	0
T3	1591000	13390	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	2995	0	0
T7	0	1	0	0
T8	0	2	0	0
T13	0	3433	0	0
T14	0	1579	0	0
T15	0	3123	0	0
T16	0	6	0	0
T17	156644	3	0	0
T18	5896	20	0	0
T19	256756	47	0	0
T20	44724	19	0	0
T21	46831	0	0	0
T22	0	10	0	0
T32	0	96	0	0
T47	0	5	0	0
T51	0	2230	0	0
T52	0	528	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1609051997	0	0
T1	122580	71726	0	0
T2	440472	282597	0	0
T3	1591000	821362	0	0
T4	65076	4360	0	0
T5	3276568	1675690	0	0
T6	2060164	1549624	0	0
T17	156644	119613	0	0
T18	5896	2528	0	0
T19	256756	195395	0	0
T20	44724	26452	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	740771789	0	0	0
DisabledNoTrigBkwd_A	740771789	275390	0	0
DisabledNoTrigFwd_A	740771789	375044378	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	275390	0	0
T1	30645	2	0	0
T2	110118	16	0	0
T3	397750	5905	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T8	0	2	0	0
T13	0	4	0	0
T17	39161	3	0	0
T18	1474	0	0	0
T19	64189	47	0	0
T20	11181	4	0	0
T22	0	8	0	0
T32	0	75	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	375044378	0	0
T1	30645	19192	0	0
T2	110118	14296	0	0
T3	397750	156254	0	0
T4	16269	1084	0	0
T5	819142	807889	0	0
T6	515041	515032	0	0
T17	39161	4491	0	0
T18	1474	626	0	0
T19	64189	3128	0	0
T20	11181	7048	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T222,T224,T225
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	740771789	5727	0	0
DisabledNoTrigBkwd_A	740771789	217398	0	0
DisabledNoTrigFwd_A	740771789	385649675	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	5727	0	0
T33	12300	0	0	0
T51	330967	0	0	0
T52	350750	0	0	0
T72	32895	0	0	0
T73	22178	0	0	0
T78	23234	0	0	0
T79	1430	0	0	0
T80	192522	0	0	0
T145	126142	0	0	0
T222	1151	437	0	0
T224	0	313	0	0
T225	0	947	0	0
T226	0	557	0	0
T231	0	828	0	0
T235	0	1235	0	0
T236	0	1056	0	0
T239	0	354	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	217398	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	2043	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	6	0	0
T13	0	1754	0	0
T14	0	12	0	0
T15	0	3123	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	4	0	0
T22	0	1	0	0
T32	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	385649675	0	0
T1	30645	24653	0	0
T2	110118	110030	0	0
T3	397750	177845	0	0
T4	16269	1088	0	0
T5	819142	38697	0	0
T6	515041	512154	0	0
T17	39161	39062	0	0
T18	1474	630	0	0
T19	64189	64089	0	0
T20	11181	4055	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T233,T234
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	740771789	1573	0	0
DisabledNoTrigBkwd_A	740771789	176783	0	0
DisabledNoTrigFwd_A	740771789	426217991	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1573	0	0
T233	1123	382	0	0
T234	3574	1191	0	0
T240	611080	0	0	0
T241	60642	0	0	0
T242	496708	0	0	0
T243	30239	0	0	0
T244	286951	0	0	0
T245	39691	0	0	0
T246	344769	0	0	0
T247	116423	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	176783	0	0
T2	110118	13	0	0
T3	397750	4326	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	6	0	0
T16	0	6	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	3	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	2	0	0
T47	0	3	0	0
T51	0	2230	0	0
T52	0	528	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	426217991	0	0
T1	30645	24650	0	0
T2	110118	48241	0	0
T3	397750	277130	0	0
T4	16269	1092	0	0
T5	819142	783535	0	0
T6	515041	513724	0	0
T17	39161	38030	0	0
T18	1474	634	0	0
T19	64189	64089	0	0
T20	11181	9705	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T223,T138
1	1	Covered	T1,T3,T5

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	740771789	6493	0	0
DisabledNoTrigBkwd_A	740771789	157769	0	0
DisabledNoTrigFwd_A	740771789	422139953	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	6493	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	0	0	0
T14	949254	0	0	0
T18	1474	661	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T138	0	839	0	0
T223	0	341	0	0
T227	0	699	0	0
T228	0	893	0	0
T229	0	1018	0	0
T230	0	466	0	0
T232	0	960	0	0
T237	0	122	0	0
T238	0	494	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	157769	0	0
T1	30645	8	0	0
T2	110118	0	0	0
T3	397750	1116	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	2983	0	0
T7	0	1	0	0
T13	0	1675	0	0
T14	0	1567	0	0
T17	39161	0	0	0
T18	1474	20	0	0
T19	64189	0	0	0
T20	11181	8	0	0
T32	0	17	0	0
T47	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	422139953	0	0
T1	30645	3231	0	0
T2	110118	110030	0	0
T3	397750	210133	0	0
T4	16269	1096	0	0
T5	819142	45569	0	0
T6	515041	8714	0	0
T17	39161	38030	0	0
T18	1474	638	0	0
T19	64189	64089	0	0
T20	11181	5644	0	0