Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T2,T3,T20
1	1	1	Covered	T2,T3,T20

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T21
0	1	Covered	T2,T3,T32
1	0	Covered	T3,T20,T33

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T20,T33

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T34,T35,T36
1	1	Covered	T2,T3,T32

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T13

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T37,T38
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T8,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T40,T41
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T43,T44
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1171	0	0
CheckAccumTrig0_A	2147483647	2624	0	0
CheckAccumTrig1_A	2147483647	129	0	0
CheckClr_A	2147483647	1223	0	0
CheckEn_A	2147483647	1199728557	0	0
CheckPhase0_A	2147483647	3018	0	0
CheckPhase1_A	2147483647	2972	0	0
CheckPhase2_A	2147483647	2911	0	0
CheckPhase3_A	2147483647	2854	0	0
CheckTimeout0_A	2147483647	3603	0	0
CheckTimeoutSt1_A	2147483647	448189	0	0
CheckTimeoutSt2_A	2147483647	3183	0	0
CheckTimeoutStTrig_A	2147483647	291	0	0
ErrorStAllEscAsserted_A	2147483647	5796	0	0
ErrorStIsTerminal_A	2147483647	4836	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1171	0	0
T8	1583760	0	0	0
T9	78340	169	0	0
T10	186056	258	0	0
T11	0	172	0	0
T14	3797016	0	0	0
T15	2027812	0	0	0
T32	101972	0	0	0
T45	0	282	0	0
T46	0	290	0	0
T47	102336	0	0	0
T48	1606228	0	0	0
T49	2649408	0	0	0
T50	2028288	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2624	0	0
T1	91935	3	0	0
T2	440472	4	0	0
T3	1591000	22	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	3	0	0
T7	0	1	0	0
T8	0	1	0	0
T13	0	2	0	0
T14	0	8	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	156644	1	0	0
T18	5896	1	0	0
T19	256756	2	0	0
T20	44724	3	0	0
T21	46831	0	0	0
T22	0	5	0	0
T32	0	3	0	0
T47	0	4	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129	0	0
T3	795500	2	0	0
T4	32538	0	0	0
T5	1638284	0	0	0
T6	1030082	0	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	0	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T17	78322	0	0	0
T18	2948	0	0	0
T19	128378	0	0	0
T20	33543	1	0	0
T21	140493	0	0	0
T22	260949	0	0	0
T32	25493	0	0	0
T33	0	3	0	0
T39	0	1	0	0
T42	269703	0	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	771791	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	685798	0	0	0
T70	32883	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223	0	0
T2	220236	3	0	0
T3	1193250	5	0	0
T4	48807	0	0	0
T5	2457426	0	0	0
T6	1545123	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T14	949254	3	0	0
T15	506953	0	0	0
T17	117483	0	0	0
T18	4422	0	0	0
T19	192567	1	0	0
T20	33543	0	0	0
T21	140493	0	0	0
T22	86983	3	0	0
T32	25493	0	0	0
T33	0	5	0	0
T39	7160	1	0	0
T40	0	1	0	0
T47	25584	1	0	0
T51	330967	1	0	0
T52	350750	0	0	0
T53	0	4	0	0
T54	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	7	0	0
T78	23234	0	0	0
T79	1430	0	0	0
T80	192522	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1199728557	0	0
T1	122580	45360	0	0
T2	440472	248691	0	0
T3	1591000	1484831	0	0
T4	65076	4356	0	0
T5	3276568	1675688	0	0
T6	2060164	529587	0	0
T17	156644	116733	0	0
T18	5896	2528	0	0
T19	256756	195392	0	0
T20	44724	7886	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3018	0	0
T1	91935	3	0	0
T2	440472	5	0	0
T3	1591000	25	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	3	0	0
T8	0	1	0	0
T13	0	3	0	0
T14	0	8	0	0
T15	0	1	0	0
T16	0	2	0	0
T17	156644	1	0	0
T18	5896	1	0	0
T19	256756	2	0	0
T20	44724	4	0	0
T21	46831	0	0	0
T22	0	5	0	0
T32	0	4	0	0
T47	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2972	0	0
T1	91935	3	0	0
T2	440472	5	0	0
T3	1591000	24	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	3	0	0
T13	0	3	0	0
T14	0	8	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	156644	1	0	0
T18	5896	1	0	0
T19	256756	2	0	0
T20	44724	4	0	0
T21	46831	0	0	0
T22	0	5	0	0
T32	0	4	0	0
T47	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2911	0	0
T1	91935	3	0	0
T2	440472	5	0	0
T3	1591000	22	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	3	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	156644	1	0	0
T18	5896	1	0	0
T19	256756	2	0	0
T20	44724	4	0	0
T21	46831	0	0	0
T22	0	5	0	0
T32	0	4	0	0
T47	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2854	0	0
T1	91935	3	0	0
T2	440472	5	0	0
T3	1591000	22	0	0
T4	65076	0	0	0
T5	3276568	1	0	0
T6	2060164	3	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	156644	1	0	0
T18	5896	1	0	0
T19	256756	2	0	0
T20	44724	4	0	0
T21	46831	0	0	0
T22	0	5	0	0
T32	0	4	0	0
T47	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3603	0	0
T2	110118	1	0	0
T3	1193250	102	0	0
T4	48807	0	0	0
T5	2457426	0	0	0
T6	1545123	0	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	0	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T17	117483	0	0	0
T18	4422	0	0	0
T19	192567	0	0	0
T20	33543	1	0	0
T21	187324	3	0	0
T22	260949	1	0	0
T32	25493	1	0	0
T33	0	3	0	0
T40	0	2	0	0
T47	25584	1	0	0
T53	0	31	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T81	0	10	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448189	0	0
T2	110118	339	0	0
T3	1193250	6430	0	0
T4	48807	0	0	0
T5	2457426	0	0	0
T6	1545123	0	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	651	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T17	117483	0	0	0
T18	4422	0	0	0
T19	192567	0	0	0
T20	33543	0	0	0
T21	187324	470	0	0
T22	260949	152	0	0
T32	25493	104	0	0
T33	0	6	0	0
T40	0	324	0	0
T47	25584	467	0	0
T53	0	6096	0	0
T54	0	1	0	0
T55	0	30	0	0
T71	0	15	0	0
T73	0	146	0	0
T74	0	216	0	0
T81	0	1781	0	0
T82	0	974	0	0
T83	0	159	0	0
T84	0	116	0	0
T85	0	282	0	0
T86	0	897	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3183	0	0
T3	1193250	99	0	0
T4	48807	0	0	0
T5	2457426	0	0	0
T6	1545123	0	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	3	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T17	117483	0	0	0
T18	4422	0	0	0
T19	192567	0	0	0
T20	33543	0	0	0
T21	187324	3	0	0
T22	347932	1	0	0
T32	25493	0	0	0
T40	0	2	0	0
T47	25584	1	0	0
T53	0	29	0	0
T71	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T76	0	2	0	0
T81	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	3	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	2	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291	0	0
T2	110118	1	0	0
T3	795500	1	0	0
T4	32538	0	0	0
T5	1638284	0	0	0
T6	1030082	0	0	0
T15	506953	0	0	0
T17	78322	0	0	0
T18	2948	0	0	0
T19	128378	0	0	0
T20	22362	0	0	0
T21	93662	0	0	0
T22	86983	0	0	0
T32	25493	1	0	0
T37	0	2	0	0
T47	25584	0	0	0
T50	0	2	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	0	2	0	0
T74	720793	0	0	0
T81	496615	3	0	0
T82	21800	1	0	0
T83	38587	0	0	0
T86	0	3	0	0
T87	0	1	0	0
T89	0	3	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	10162	0	0	0
T99	12509	0	0	0
T100	22878	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5796	0	0
T8	1583760	0	0	0
T9	78340	764	0	0
T10	186056	1421	0	0
T11	0	754	0	0
T14	3797016	0	0	0
T15	2027812	0	0	0
T32	101972	0	0	0
T45	0	1414	0	0
T46	0	1443	0	0
T47	102336	0	0	0
T48	1606228	0	0	0
T49	2649408	0	0	0
T50	2028288	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4836	0	0
T8	1583760	0	0	0
T9	78340	644	0	0
T10	186056	1181	0	0
T11	0	634	0	0
T14	3797016	0	0	0
T15	2027812	0	0	0
T32	101972	0	0	0
T45	0	1174	0	0
T46	0	1203	0	0
T47	102336	0	0	0
T48	1606228	0	0	0
T49	2649408	0	0	0
T50	2028288	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	122580	122212	0	0
T2	440472	440120	0	0
T3	1591000	1590848	0	0
T4	65076	64484	0	0
T5	3276568	3276340	0	0
T6	2060164	2060128	0	0
T17	156644	156248	0	0
T18	5896	5664	0	0
T19	256756	256356	0	0
T20	44724	44436	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T19,T32
1	1	0	Covered	T3,T21,T22
1	1	1	Covered	T3,T20,T71

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T71,T73
0	1	Covered	T3,T89,T92
1	0	Covered	T20,T33,T55

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T71,T73
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T33,T55

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T71
1	0	Not Covered
1	1	Covered	T3,T89,T92

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T13

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T22,T78

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T22,T47

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T22
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T17

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T19,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T17,T19

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T71
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T33
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T71,T73
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T71,T73
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T101,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T74,T75
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T42,T70
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T43,T44,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	740771789	329	0	0
CheckAccumTrig0_A	740771789	989	0	0
CheckAccumTrig1_A	740771789	63	0	0
CheckClr_A	740771789	504	0	0
CheckEn_A	740599923	244433318	0	0
CheckPhase0_A	740771789	1115	0	0
CheckPhase1_A	740771789	1098	0	0
CheckPhase2_A	740771789	1068	0	0
CheckPhase3_A	740771789	1046	0	0
CheckTimeout0_A	740771789	770	0	0
CheckTimeoutSt1_A	740771789	87163	0	0
CheckTimeoutSt2_A	740771789	634	0	0
CheckTimeoutStTrig_A	740771789	73	0	0
ErrorStAllEscAsserted_A	740771789	1468	0	0
ErrorStIsTerminal_A	740771789	1228	0	0
u_state_regs_A	740771789	740596586	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	329	0	0
T8	395940	0	0	0
T9	19585	50	0	0
T10	46514	63	0	0
T11	0	58	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	67	0	0
T46	0	91	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	989	0	0
T1	30645	1	0	0
T2	110118	3	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	39161	1	0	0
T18	1474	0	0	0
T19	64189	2	0	0
T20	11181	0	0	0
T22	0	3	0	0
T32	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	63	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	0	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T32	25493	0	0	0
T33	0	3	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T66	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	504	0	0
T2	110118	2	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	1	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	0	3	0	0
T33	0	5	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740599923	244433318	0	0
T1	30645	14290	0	0
T2	110118	14296	0	0
T3	397750	822831	0	0
T4	16269	1083	0	0
T5	819142	807888	0	0
T6	515041	515032	0	0
T17	39161	1614	0	0
T18	1474	626	0	0
T19	64189	3128	0	0
T20	11181	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1115	0	0
T1	30645	1	0	0
T2	110118	3	0	0
T3	397750	9	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T8	0	1	0	0
T13	0	1	0	0
T17	39161	1	0	0
T18	1474	0	0	0
T19	64189	2	0	0
T20	11181	1	0	0
T22	0	3	0	0
T32	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1098	0	0
T1	30645	1	0	0
T2	110118	3	0	0
T3	397750	9	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	39161	1	0	0
T18	1474	0	0	0
T19	64189	2	0	0
T20	11181	1	0	0
T22	0	3	0	0
T32	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1068	0	0
T1	30645	1	0	0
T2	110118	3	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	39161	1	0	0
T18	1474	0	0	0
T19	64189	2	0	0
T20	11181	1	0	0
T22	0	3	0	0
T32	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1046	0	0
T1	30645	1	0	0
T2	110118	3	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	39161	1	0	0
T18	1474	0	0	0
T19	64189	2	0	0
T20	11181	1	0	0
T22	0	3	0	0
T32	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	770	0	0
T3	397750	2	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T33	0	3	0	0
T40	0	2	0	0
T71	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T81	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	87163	0	0
T3	397750	591	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T33	0	6	0	0
T40	0	324	0	0
T71	0	15	0	0
T73	0	146	0	0
T74	0	216	0	0
T81	0	264	0	0
T83	0	159	0	0
T84	0	116	0	0
T85	0	137	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	634	0	0
T3	397750	1	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T40	0	2	0	0
T53	0	1	0	0
T71	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T81	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	73	0	0
T3	397750	1	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T50	0	1	0	0
T63	0	2	0	0
T89	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1468	0	0
T8	395940	0	0	0
T9	19585	192	0	0
T10	46514	357	0	0
T11	0	201	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	348	0	0
T46	0	370	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1228	0	0
T8	395940	0	0	0
T9	19585	162	0	0
T10	46514	297	0	0
T11	0	171	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	288	0	0
T46	0	310	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	740596586	0	0
T1	30645	30553	0	0
T2	110118	110030	0	0
T3	397750	397712	0	0
T4	16269	16121	0	0
T5	819142	819085	0	0
T6	515041	515032	0	0
T17	39161	39062	0	0
T18	1474	1416	0	0
T19	64189	64089	0	0
T20	11181	11109	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T21
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T2,T3,T20
1	1	1	Covered	T3,T32,T47

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T32,T47
0	1	Covered	T32,T81,T82
1	0	Covered	T3,T53,T54

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T32,T47
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T53,T54

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T47
1	0	Not Covered
1	1	Covered	T32,T81,T82

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T3,T14,T15

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T20
1	Covered	T1,T3,T5

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T6,T22,T13

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T20,T14,T32

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T6,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T32,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T32,T81
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T32,T47
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T47,T81
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T104,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T38,T107,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T55,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T110,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T47,T51
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	740771789	308	0	0
CheckAccumTrig0_A	740771789	565	0	0
CheckAccumTrig1_A	740771789	26	0	0
CheckClr_A	740771789	255	0	0
CheckEn_A	740599923	297893954	0	0
CheckPhase0_A	740771789	661	0	0
CheckPhase1_A	740771789	655	0	0
CheckPhase2_A	740771789	641	0	0
CheckPhase3_A	740771789	627	0	0
CheckTimeout0_A	740771789	1084	0	0
CheckTimeoutSt1_A	740771789	130674	0	0
CheckTimeoutSt2_A	740771789	985	0	0
CheckTimeoutStTrig_A	740771789	73	0	0
ErrorStAllEscAsserted_A	740771789	1465	0	0
ErrorStIsTerminal_A	740771789	1225	0	0
u_state_regs_A	740771789	740596586	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	308	0	0
T8	395940	0	0	0
T9	19585	51	0	0
T10	46514	67	0	0
T11	0	30	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	80	0	0
T46	0	80	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	565	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T22	0	1	0	0
T47	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	26	0	0
T3	397750	1	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	255	0	0
T14	949254	3	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T39	7160	0	0	0
T40	0	1	0	0
T47	25584	1	0	0
T51	330967	1	0	0
T52	350750	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	7	0	0
T78	23234	0	0	0
T79	1430	0	0	0
T80	192522	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740599923	297893954	0	0
T1	30645	3190	0	0
T2	110118	110029	0	0
T3	397750	176522	0	0
T4	16269	1087	0	0
T5	819142	38697	0	0
T6	515041	9439	0	0
T17	39161	39061	0	0
T18	1474	630	0	0
T19	64189	64088	0	0
T20	11181	4055	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	661	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T22	0	1	0	0
T32	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	655	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T22	0	1	0	0
T32	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	641	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T22	0	1	0	0
T32	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	627	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	1	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T22	0	1	0	0
T32	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1084	0	0
T3	397750	6	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T32	0	1	0	0
T47	0	1	0	0
T53	0	25	0	0
T54	0	1	0	0
T55	0	1	0	0
T81	0	5	0	0
T82	0	2	0	0
T85	0	1	0	0
T86	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	130674	0	0
T3	397750	418	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T32	0	104	0	0
T47	0	467	0	0
T53	0	3756	0	0
T54	0	1	0	0
T55	0	30	0	0
T81	0	1058	0	0
T82	0	974	0	0
T85	0	145	0	0
T86	0	897	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	985	0	0
T3	397750	5	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T47	0	1	0	0
T53	0	23	0	0
T81	0	3	0	0
T82	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0
T88	0	3	0	0
T89	0	2	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	73	0	0
T15	506953	0	0	0
T32	25493	1	0	0
T37	0	1	0	0
T47	25584	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T74	720793	0	0	0
T81	496615	2	0	0
T82	21800	1	0	0
T83	38587	0	0	0
T86	0	3	0	0
T89	0	2	0	0
T91	0	1	0	0
T98	10162	0	0	0
T99	12509	0	0	0
T100	22878	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1465	0	0
T8	395940	0	0	0
T9	19585	190	0	0
T10	46514	349	0	0
T11	0	181	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	376	0	0
T46	0	369	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1225	0	0
T8	395940	0	0	0
T9	19585	160	0	0
T10	46514	289	0	0
T11	0	151	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	316	0	0
T46	0	309	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	740596586	0	0
T1	30645	30553	0	0
T2	110118	110030	0	0
T3	397750	397712	0	0
T4	16269	16121	0	0
T5	819142	819085	0	0
T6	515041	515032	0	0
T17	39161	39062	0	0
T18	1474	1416	0	0
T19	64189	64089	0	0
T20	11181	11109	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T17
1	0	1	Covered	T6,T51,T52
1	1	0	Covered	T2,T3,T20
1	1	1	Covered	T2,T3,T21

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T21
0	1	Covered	T2,T81,T87
1	0	Covered	T3,T39,T42

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T39,T42

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T36
1	1	Covered	T2,T81,T87

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T3,T51,T52

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T32
1	Covered	T6,T20,T22

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T3,T32

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T2,T16,T74

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T87

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T38,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T39,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T113,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T115,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T74
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	740771789	257	0	0
CheckAccumTrig0_A	740771789	545	0	0
CheckAccumTrig1_A	740771789	17	0	0
CheckClr_A	740771789	248	0	0
CheckEn_A	740599923	324745225	0	0
CheckPhase0_A	740771789	623	0	0
CheckPhase1_A	740771789	610	0	0
CheckPhase2_A	740771789	601	0	0
CheckPhase3_A	740771789	590	0	0
CheckTimeout0_A	740771789	909	0	0
CheckTimeoutSt1_A	740771789	125215	0	0
CheckTimeoutSt2_A	740771789	824	0	0
CheckTimeoutStTrig_A	740771789	68	0	0
ErrorStAllEscAsserted_A	740771789	1421	0	0
ErrorStIsTerminal_A	740771789	1181	0	0
u_state_regs_A	740771789	740596586	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	257	0	0
T8	395940	0	0	0
T9	19585	41	0	0
T10	46514	68	0	0
T11	0	34	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	56	0	0
T46	0	58	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	545	0	0
T2	110118	1	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	17	0	0
T3	397750	1	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	248	0	0
T2	110118	1	0	0
T3	397750	2	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T39	0	1	0	0
T41	0	10	0	0
T42	0	4	0	0
T53	0	2	0	0
T55	0	1	0	0
T74	0	1	0	0
T84	0	1	0	0
T86	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740599923	324745225	0	0
T1	30645	24649	0	0
T2	110118	14337	0	0
T3	397750	275937	0	0
T4	16269	1091	0	0
T5	819142	783534	0	0
T6	515041	2547	0	0
T17	39161	38029	0	0
T18	1474	634	0	0
T19	64189	64088	0	0
T20	11181	2655	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	623	0	0
T2	110118	2	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	610	0	0
T2	110118	2	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	601	0	0
T2	110118	2	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	590	0	0
T2	110118	2	0	0
T3	397750	3	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T21	46831	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	909	0	0
T2	110118	1	0	0
T3	397750	94	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	3	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	3	0	0
T22	0	1	0	0
T39	0	1	0	0
T53	0	6	0	0
T76	0	2	0	0
T81	0	3	0	0
T87	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	125215	0	0
T2	110118	339	0	0
T3	397750	5421	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	651	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	470	0	0
T22	0	152	0	0
T39	0	12	0	0
T53	0	2340	0	0
T76	0	144	0	0
T81	0	459	0	0
T87	0	179	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	824	0	0
T3	397750	93	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T13	0	3	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	3	0	0
T22	86983	1	0	0
T42	0	1	0	0
T53	0	5	0	0
T55	0	3	0	0
T76	0	2	0	0
T81	0	2	0	0
T87	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	68	0	0
T2	110118	1	0	0
T3	397750	0	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T37	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T81	0	1	0	0
T87	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1421	0	0
T8	395940	0	0	0
T9	19585	179	0	0
T10	46514	360	0	0
T11	0	172	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	347	0	0
T46	0	363	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1181	0	0
T8	395940	0	0	0
T9	19585	149	0	0
T10	46514	300	0	0
T11	0	142	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	287	0	0
T46	0	303	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	740596586	0	0
T1	30645	30553	0	0
T2	110118	110030	0	0
T3	397750	397712	0	0
T4	16269	16121	0	0
T5	819142	819085	0	0
T6	515041	515032	0	0
T17	39161	39062	0	0
T18	1474	1416	0	0
T19	64189	64089	0	0
T20	11181	11109	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T20
1	0	1	Covered	T3,T5,T18
1	1	0	Covered	T2,T3,T21
1	1	1	Covered	T21,T22,T13

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T13
0	1	Covered	T13,T81,T124
1	0	Covered	T42,T57,T62

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T22,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T57,T62

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T13
1	0	Covered	T34,T35,T125
1	1	Covered	T13,T81,T124

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T18,T20

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T18,T20
1	Covered	T1,T3,T6

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T16,T126

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T3,T13,T47

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T18,T20

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T18,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T81,T124
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T32
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T110,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T128,T111,T129
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T14,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T109,T117,T130
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T14,T51
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	740771789	277	0	0
CheckAccumTrig0_A	740771789	525	0	0
CheckAccumTrig1_A	740771789	23	0	0
CheckClr_A	740771789	216	0	0
CheckEn_A	740599923	332656060	0	0
CheckPhase0_A	740771789	619	0	0
CheckPhase1_A	740771789	609	0	0
CheckPhase2_A	740771789	601	0	0
CheckPhase3_A	740771789	591	0	0
CheckTimeout0_A	740771789	840	0	0
CheckTimeoutSt1_A	740771789	105137	0	0
CheckTimeoutSt2_A	740771789	740	0	0
CheckTimeoutStTrig_A	740771789	77	0	0
ErrorStAllEscAsserted_A	740771789	1442	0	0
ErrorStIsTerminal_A	740771789	1202	0	0
u_state_regs_A	740771789	740596586	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	277	0	0
T8	395940	0	0	0
T9	19585	27	0	0
T10	46514	60	0	0
T11	0	50	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	79	0	0
T46	0	61	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	525	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T7	0	1	0	0
T14	0	4	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	1	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T32	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	23	0	0
T42	269703	1	0	0
T43	201117	0	0	0
T55	771791	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T69	685798	0	0	0
T70	32883	0	0	0
T105	0	1	0	0
T117	0	2	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	76050	0	0	0
T137	56207	0	0	0
T138	3635	0	0	0
T139	194770	0	0	0
T140	86749	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	216	0	0
T3	397750	4	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	0	0	0
T7	0	1	0	0
T14	0	3	0	0
T17	39161	0	0	0
T18	1474	0	0	0
T19	64189	0	0	0
T20	11181	0	0	0
T21	46831	0	0	0
T22	86983	0	0	0
T42	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T74	0	2	0	0
T77	0	1	0	0
T81	0	1	0	0
T126	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740599923	332656060	0	0
T1	30645	3231	0	0
T2	110118	110029	0	0
T3	397750	209541	0	0
T4	16269	1095	0	0
T5	819142	45569	0	0
T6	515041	2569	0	0
T17	39161	38029	0	0
T18	1474	638	0	0
T19	64189	64088	0	0
T20	11181	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	619	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	1	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T32	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	609	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	8	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	1	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T32	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	601	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	7	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	1	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T32	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	591	0	0
T1	30645	1	0	0
T2	110118	0	0	0
T3	397750	7	0	0
T4	16269	0	0	0
T5	819142	0	0	0
T6	515041	1	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	39161	0	0	0
T18	1474	1	0	0
T19	64189	0	0	0
T20	11181	1	0	0
T32	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	840	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	1	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T21	46831	2	0	0
T22	86983	1	0	0
T32	25493	1	0	0
T42	0	2	0	0
T47	25584	0	0	0
T53	0	26	0	0
T55	0	1	0	0
T74	0	2	0	0
T81	0	6	0	0
T124	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	105137	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	217	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T21	46831	278	0	0
T22	86983	165	0	0
T32	25493	462	0	0
T42	0	154	0	0
T47	25584	0	0	0
T53	0	3604	0	0
T55	0	36	0	0
T74	0	245	0	0
T81	0	996	0	0
T124	0	459	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	740	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	0	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T21	46831	2	0	0
T22	86983	1	0	0
T32	25493	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T47	25584	0	0	0
T53	0	24	0	0
T55	0	1	0	0
T74	0	2	0	0
T81	0	4	0	0
T86	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	77	0	0
T7	406042	0	0	0
T8	395940	0	0	0
T9	19585	0	0	0
T13	418695	1	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T43	0	1	0	0
T47	25584	0	0	0
T53	0	2	0	0
T56	0	1	0	0
T81	496615	2	0	0
T98	10162	0	0	0
T124	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1442	0	0
T8	395940	0	0	0
T9	19585	203	0	0
T10	46514	355	0	0
T11	0	200	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	343	0	0
T46	0	341	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	1202	0	0
T8	395940	0	0	0
T9	19585	173	0	0
T10	46514	295	0	0
T11	0	170	0	0
T14	949254	0	0	0
T15	506953	0	0	0
T32	25493	0	0	0
T45	0	283	0	0
T46	0	281	0	0
T47	25584	0	0	0
T48	401557	0	0	0
T49	662352	0	0	0
T50	507072	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740771789	740596586	0	0
T1	30645	30553	0	0
T2	110118	110030	0	0
T3	397750	397712	0	0
T4	16269	16121	0	0
T5	819142	819085	0	0
T6	515041	515032	0	0
T17	39161	39062	0	0
T18	1474	1416	0	0
T19	64189	64089	0	0
T20	11181	11109	0	0