Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74405935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36546666

1

T15

3914

T27

57

T28

4103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16633072	1			T15	1803		T27	16		T28	1833
values[0x0]	45461364	1			T15	1067		T27	29		T28	1120
values[0x1]	48858165	1			T15	1045		T27	243		T28	1150

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62888667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48063934

1

T15

3914

T27

225

T28

4103

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	355883	1			T15	25		T28	10		T31	28
valid_sources[0x01]	348573	1			T15	2		T27	2		T28	9
valid_sources[0x02]	358820	1			T15	15		T28	11		T30	1
valid_sources[0x03]	579100	1			T27	2		T28	24		T31	28
valid_sources[0x04]	361757	1			T15	16		T28	27		T31	29
valid_sources[0x05]	353002	1			T15	23		T27	2		T28	27
valid_sources[0x06]	819943	1			T15	28		T28	20		T31	23
valid_sources[0x07]	366871	1			T15	26		T27	4		T28	13
valid_sources[0x08]	630012	1			T15	11		T27	3		T28	6
valid_sources[0x09]	351841	1			T27	1		T28	32		T31	27
valid_sources[0x0a]	357113	1			T15	25		T27	5		T28	39
valid_sources[0x0b]	365550	1			T15	10		T27	1		T28	9
valid_sources[0x0c]	361006	1			T15	10		T28	17		T31	39
valid_sources[0x0d]	356067	1			T27	2		T28	23		T31	32
valid_sources[0x0e]	762599	1			T28	23		T31	27		T32	23
valid_sources[0x0f]	354396	1			T27	1		T28	4		T31	30
valid_sources[0x10]	358466	1			T15	25		T27	2		T28	15
valid_sources[0x11]	362064	1			T15	22		T28	14		T31	31
valid_sources[0x12]	383198	1			T15	4		T27	2		T28	13
valid_sources[0x13]	359236	1			T15	7		T28	20		T31	20
valid_sources[0x14]	359164	1			T15	19		T28	17		T31	34
valid_sources[0x15]	1102724	1			T27	1		T28	7		T31	28
valid_sources[0x16]	356019	1			T28	19		T31	32		T32	4
valid_sources[0x17]	713940	1			T27	1		T28	11		T30	1
valid_sources[0x18]	368858	1			T27	2		T28	16		T31	32
valid_sources[0x19]	355115	1			T15	21		T28	9		T31	31
valid_sources[0x1a]	368850	1			T15	7		T27	3		T28	9
valid_sources[0x1b]	369974	1			T15	16		T27	1		T28	33
valid_sources[0x1c]	353109	1			T27	2		T28	10		T31	27
valid_sources[0x1d]	356026	1			T27	1		T28	23		T31	40
valid_sources[0x1e]	370957	1			T15	17		T27	2		T28	11
valid_sources[0x1f]	357546	1			T15	14		T28	34		T31	25
valid_sources[0x20]	714817	1			T15	1		T27	1		T28	7
valid_sources[0x21]	369852	1			T15	16		T27	4		T28	14
valid_sources[0x22]	352995	1			T15	11		T27	2		T28	15
valid_sources[0x23]	361908	1			T15	36		T28	22		T31	27
valid_sources[0x24]	356268	1			T15	2		T27	3		T28	21
valid_sources[0x25]	355001	1			T15	35		T28	8		T31	25
valid_sources[0x26]	360446	1			T15	42		T28	17		T30	1
valid_sources[0x27]	590863	1			T15	6		T27	1		T28	18
valid_sources[0x28]	940832	1			T27	1		T28	16		T31	27
valid_sources[0x29]	357453	1			T27	2		T28	11		T31	31
valid_sources[0x2a]	365273	1			T28	17		T31	31		T33	27
valid_sources[0x2b]	361409	1			T27	1		T28	13		T31	29
valid_sources[0x2c]	370449	1			T28	8		T31	30		T33	17
valid_sources[0x2d]	358736	1			T15	8		T27	1		T28	21
valid_sources[0x2e]	758139	1			T15	17		T28	6		T31	27
valid_sources[0x2f]	364717	1			T15	50		T27	1		T28	16
valid_sources[0x30]	366235	1			T15	28		T27	3		T28	16
valid_sources[0x31]	622155	1			T15	32		T27	5		T28	16
valid_sources[0x32]	360094	1			T15	4		T27	2		T28	6
valid_sources[0x33]	371969	1			T15	21		T27	3		T28	13
valid_sources[0x34]	357584	1			T15	19		T27	3		T28	27
valid_sources[0x35]	392321	1			T27	2		T28	12		T31	32
valid_sources[0x36]	381155	1			T15	18		T27	2		T28	27
valid_sources[0x37]	361768	1			T15	8		T27	1		T28	4
valid_sources[0x38]	357852	1			T15	43		T27	1		T28	26
valid_sources[0x39]	359635	1			T27	2		T28	23		T31	28
valid_sources[0x3a]	363561	1			T15	31		T28	25		T31	26
valid_sources[0x3b]	652098	1			T15	22		T27	1		T28	12
valid_sources[0x3c]	358147	1			T28	8		T31	28		T33	17
valid_sources[0x3d]	423236	1			T27	1		T28	11		T31	20
valid_sources[0x3e]	375631	1			T28	17		T31	36		T33	38
valid_sources[0x3f]	386838	1			T15	37		T27	1		T28	17
valid_sources[0x40]	357127	1			T15	10		T27	1		T28	11
valid_sources[0x41]	369726	1			T28	14		T31	46		T33	28
valid_sources[0x42]	355747	1			T15	29		T27	1		T28	18
valid_sources[0x43]	363309	1			T15	46		T28	8		T31	37
valid_sources[0x44]	362833	1			T27	1		T28	13		T31	26
valid_sources[0x45]	368025	1			T15	16		T27	1		T28	24
valid_sources[0x46]	358620	1			T15	18		T27	2		T28	12
valid_sources[0x47]	356512	1			T15	16		T28	13		T31	44
valid_sources[0x48]	354825	1			T15	22		T27	1		T28	31
valid_sources[0x49]	367915	1			T15	30		T27	1		T28	6
valid_sources[0x4a]	1006341	1			T15	18		T28	8		T31	30
valid_sources[0x4b]	355867	1			T15	28		T27	1		T28	10
valid_sources[0x4c]	359772	1			T15	5		T27	2		T28	6
valid_sources[0x4d]	360027	1			T27	3		T28	8		T31	28
valid_sources[0x4e]	357966	1			T15	18		T27	1		T28	5
valid_sources[0x4f]	354036	1			T15	21		T27	1		T28	14
valid_sources[0x50]	828438	1			T15	7		T27	2		T28	26
valid_sources[0x51]	353728	1			T15	13		T28	14		T31	25
valid_sources[0x52]	360404	1			T15	30		T27	1		T28	12
valid_sources[0x53]	516019	1			T15	15		T27	2		T28	27
valid_sources[0x54]	359754	1			T15	14		T28	11		T31	29
valid_sources[0x55]	361218	1			T28	18		T31	28		T33	16
valid_sources[0x56]	725247	1			T15	2		T27	1		T28	14
valid_sources[0x57]	838954	1			T15	15		T27	1		T28	30
valid_sources[0x58]	358211	1			T15	42		T28	8		T31	29
valid_sources[0x59]	362725	1			T15	18		T27	1		T28	10
valid_sources[0x5a]	353603	1			T15	11		T27	1		T28	22
valid_sources[0x5b]	690724	1			T15	3		T28	12		T31	30
valid_sources[0x5c]	813256	1			T15	12		T28	5		T31	31
valid_sources[0x5d]	360326	1			T15	20		T28	16		T31	26
valid_sources[0x5e]	562252	1			T15	6		T28	9		T31	44
valid_sources[0x5f]	372180	1			T15	3		T28	31		T31	38
valid_sources[0x60]	357906	1			T15	33		T27	2		T28	4
valid_sources[0x61]	375448	1			T15	1		T27	2		T28	18
valid_sources[0x62]	810872	1			T15	4		T27	1		T28	13
valid_sources[0x63]	352845	1			T15	9		T27	1		T28	32
valid_sources[0x64]	356152	1			T27	2		T28	17		T31	34
valid_sources[0x65]	356725	1			T15	27		T27	2		T28	14
valid_sources[0x66]	362247	1			T15	22		T28	21		T30	1
valid_sources[0x67]	364094	1			T28	18		T31	30		T33	20
valid_sources[0x68]	351942	1			T27	3		T28	27		T30	1
valid_sources[0x69]	352036	1			T15	12		T28	24		T30	1
valid_sources[0x6a]	376040	1			T15	28		T28	14		T31	29
valid_sources[0x6b]	737425	1			T15	63		T28	11		T31	35
valid_sources[0x6c]	363003	1			T15	18		T27	2		T28	21
valid_sources[0x6d]	355279	1			T15	33		T28	22		T31	31
valid_sources[0x6e]	359172	1			T15	21		T27	3		T28	25
valid_sources[0x6f]	365289	1			T15	21		T27	1		T28	9
valid_sources[0x70]	353057	1			T15	28		T27	2		T28	16
valid_sources[0x71]	361860	1			T27	3		T28	17		T31	34
valid_sources[0x72]	390746	1			T15	1		T27	1		T28	12
valid_sources[0x73]	881798	1			T15	17		T27	1		T28	21
valid_sources[0x74]	369094	1			T15	20		T27	1		T28	8
valid_sources[0x75]	364501	1			T15	23		T27	1		T28	4
valid_sources[0x76]	365378	1			T15	16		T27	1		T28	13
valid_sources[0x77]	376492	1			T15	21		T27	2		T28	24
valid_sources[0x78]	364664	1			T15	8		T28	7		T31	41
valid_sources[0x79]	357876	1			T15	34		T27	2		T28	15
valid_sources[0x7a]	364348	1			T15	25		T28	7		T30	2
valid_sources[0x7b]	357538	1			T15	8		T27	2		T28	18
valid_sources[0x7c]	359383	1			T15	14		T27	2		T28	27
valid_sources[0x7d]	368053	1			T15	9		T27	2		T28	15
valid_sources[0x7e]	366065	1			T15	27		T27	2		T28	18
valid_sources[0x7f]	609479	1			T15	3		T27	3		T28	14
valid_sources[0x80]	375384	1			T15	40		T27	1		T28	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8403240

1

T15

1802

T27

15

T28

1833

values[0x0]

all_enables

biggest_size

17658279

1

T15

1067

T27

27

T28

1120

values[0x1]

all_enables

biggest_size

10485147

1

T15

1045

T27

15

T28

1150