Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T188,T189
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	17625	0	0
DisabledNoTrigBkwd_A	2147483647	912583	0	0
DisabledNoTrigFwd_A	2147483647	1638887538	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17625	0	0
T11	196775	0	0	0
T38	578009	0	0	0
T39	33118	0	0	0
T58	614807	0	0	0
T59	38506	0	0	0
T88	26094	0	0	0
T187	0	778	0	0
T188	1609	740	0	0
T189	894	222	0	0
T190	1278	431	0	0
T191	3436	1101	0	0
T192	9418	1264	0	0
T193	4006	623	0	0
T194	0	1637	0	0
T195	0	838	0	0
T196	0	576	0	0
T197	1454	620	0	0
T198	0	565	0	0
T199	3516	1182	0	0
T200	0	219	0	0
T201	0	1794	0	0
T202	0	438	0	0
T203	0	1614	0	0
T204	0	827	0	0
T205	0	969	0	0
T206	0	1187	0	0
T207	30325	0	0	0
T208	125434	0	0	0
T209	363276	0	0	0
T210	102562	0	0	0
T211	252962	0	0	0
T212	58140	0	0	0
T213	11613	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	912583	0	0
T1	62553	12	0	0
T2	1979872	2930	0	0
T3	322192	18	0	0
T4	49764	0	0	0
T5	1106472	5996	0	0
T6	3840428	2287	0	0
T7	0	434	0	0
T16	0	1397	0	0
T17	0	4569	0	0
T19	0	351	0	0
T20	0	72	0	0
T21	2676592	817	0	0
T22	128680	0	0	0
T23	83644	18	0	0
T24	86764	0	0	0
T25	11880	0	0	0
T36	0	1025	0	0
T52	0	31	0	0
T53	0	686	0	0
T54	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1638887538	0	0
T1	83404	53767	0	0
T2	1979872	1694166	0	0
T3	322192	241828	0	0
T4	49764	3428	0	0
T5	1106472	295947	0	0
T6	3840428	1918484	0	0
T21	2676592	1106497	0	0
T22	128680	128300	0	0
T23	83644	58850	0	0
T24	86764	78911	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T190,T196
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	757565810	3541	0	0
DisabledNoTrigBkwd_A	757565810	336756	0	0
DisabledNoTrigFwd_A	757565810	351442374	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	3541	0	0
T11	196775	0	0	0
T38	578009	0	0	0
T39	33118	0	0	0
T58	614807	0	0	0
T59	38506	0	0	0
T188	1609	740	0	0
T189	894	0	0	0
T190	1278	431	0	0
T196	0	576	0	0
T201	0	1794	0	0
T207	30325	0	0	0
T208	125434	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	336756	0	0
T1	20851	3	0	0
T2	494968	893	0	0
T3	80548	18	0	0
T4	12441	0	0	0
T5	276618	1897	0	0
T6	960107	1155	0	0
T17	0	257	0	0
T21	669148	84	0	0
T22	32170	0	0	0
T23	20911	18	0	0
T24	21691	0	0	0
T36	0	961	0	0
T52	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	351442374	0	0
T1	20851	17293	0	0
T2	494968	912811	0	0
T3	80548	589	0	0
T4	12441	851	0	0
T5	276618	14880	0	0
T6	960107	582	0	0
T21	669148	179820	0	0
T22	32170	32075	0	0
T23	20911	6195	0	0
T24	21691	21613	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T191,T197,T199
1	1	Covered	T1,T2,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	757565810	2903	0	0
DisabledNoTrigBkwd_A	757565810	190862	0	0
DisabledNoTrigFwd_A	757565810	428081339	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	2903	0	0
T88	13047	0	0	0
T191	3436	1101	0	0
T192	4709	0	0	0
T197	1454	620	0	0
T199	3516	1182	0	0
T209	363276	0	0	0
T210	102562	0	0	0
T211	126481	0	0	0
T212	29070	0	0	0
T213	11613	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	190862	0	0
T1	20851	7	0	0
T2	494968	169	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	1956	0	0
T6	960107	1129	0	0
T7	0	434	0	0
T16	0	2	0	0
T17	0	2042	0	0
T21	669148	530	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	43	0	0
T52	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	428081339	0	0
T1	20851	9555	0	0
T2	494968	427127	0	0
T3	80548	80413	0	0
T4	12441	855	0	0
T5	276618	2212	0	0
T6	960107	586	0	0
T21	669148	110124	0	0
T22	32170	32075	0	0
T23	20911	10949	0	0
T24	21691	21613	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T21
1	0	Covered	T1,T2,T21
1	1	Covered	T2,T21,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T193,T194
1	1	Covered	T2,T21,T6

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T21,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	757565810	7153	0	0
DisabledNoTrigBkwd_A	757565810	220060	0	0
DisabledNoTrigFwd_A	757565810	395396141	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	7153	0	0
T88	13047	0	0	0
T96	135731	0	0	0
T102	139739	0	0	0
T112	11029	0	0	0
T192	4709	1264	0	0
T193	4006	623	0	0
T194	0	1637	0	0
T200	0	219	0	0
T203	0	1614	0	0
T204	0	827	0	0
T205	0	969	0	0
T211	126481	0	0	0
T212	29070	0	0	0
T214	134072	0	0	0
T215	113107	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	220060	0	0
T2	494968	1486	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	3	0	0
T16	0	1393	0	0
T17	0	1153	0	0
T19	0	321	0	0
T20	0	58	0	0
T21	669148	202	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	12	0	0
T53	0	38	0	0
T54	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	395396141	0	0
T1	20851	20792	0	0
T2	494968	172844	0	0
T3	80548	80413	0	0
T4	12441	859	0	0
T5	276618	276610	0	0
T6	960107	957277	0	0
T21	669148	152002	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	14072	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T21

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T189,T195
1	1	Covered	T1,T2,T21

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	757565810	4028	0	0
DisabledNoTrigBkwd_A	757565810	164905	0	0
DisabledNoTrigFwd_A	757565810	463967684	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	4028	0	0
T55	217319	0	0	0
T56	898711	0	0	0
T187	4185	778	0	0
T189	894	222	0	0
T195	1676	838	0	0
T198	0	565	0	0
T202	0	438	0	0
T206	0	1187	0	0
T216	197617	0	0	0
T217	176170	0	0	0
T218	2238	0	0	0
T219	15437	0	0	0
T220	18083	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	164905	0	0
T1	20851	2	0	0
T2	494968	382	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	2143	0	0
T6	960107	0	0	0
T16	0	2	0	0
T17	0	1117	0	0
T19	0	30	0	0
T20	0	14	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	9	0	0
T53	0	648	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	463967684	0	0
T1	20851	6127	0	0
T2	494968	181384	0	0
T3	80548	80413	0	0
T4	12441	863	0	0
T5	276618	2245	0	0
T6	960107	960039	0	0
T21	669148	664551	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	21613	0	0