Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T21
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T21,T24
1	1	1	Covered	T2,T21,T24

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T24
0	1	Covered	T2,T21,T36
1	0	Covered	T2,T16,T17

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T21,T24
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T17

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T24
1	0	Not Covered
1	1	Covered	T2,T21,T36

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T2,T3,T21

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T21

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T17,T37
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T19,T38
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T39,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T17,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1213	0	0
CheckAccumTrig0_A	2147483647	2736	0	0
CheckAccumTrig1_A	2147483647	156	0	0
CheckClr_A	2147483647	1369	0	0
CheckEn_A	2147483647	1329322141	0	0
CheckPhase0_A	2147483647	3153	0	0
CheckPhase1_A	2147483647	3093	0	0
CheckPhase2_A	2147483647	3025	0	0
CheckPhase3_A	2147483647	2977	0	0
CheckTimeout0_A	2147483647	4717	0	0
CheckTimeoutSt1_A	2147483647	530785	0	0
CheckTimeoutSt2_A	2147483647	4255	0	0
CheckTimeoutStTrig_A	2147483647	306	0	0
ErrorStAllEscAsserted_A	2147483647	5832	0	0
ErrorStIsTerminal_A	2147483647	4872	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1213	0	0
T12	180952	299	0	0
T13	0	307	0	0
T14	0	168	0	0
T41	0	150	0	0
T42	0	289	0	0
T43	1390184	0	0	0
T44	447476	0	0	0
T45	76148	0	0	0
T46	1495760	0	0	0
T47	1243420	0	0	0
T48	1156996	0	0	0
T49	101792	0	0	0
T50	153192	0	0	0
T51	284156	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2736	0	0
T1	62553	4	0	0
T2	1979872	32	0	0
T3	322192	1	0	0
T4	49764	0	0	0
T5	1106472	15	0	0
T6	3840428	3	0	0
T7	0	1	0	0
T16	0	3	0	0
T17	0	36	0	0
T19	0	13	0	0
T20	0	3	0	0
T21	2676592	6	0	0
T22	128680	0	0	0
T23	83644	1	0	0
T24	86764	0	0	0
T25	11880	0	0	0
T36	0	3	0	0
T52	0	2	0	0
T53	0	7	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	156	0	0
T2	1484904	3	0	0
T3	241644	0	0	0
T4	37323	0	0	0
T5	829854	0	0	0
T6	2880321	0	0	0
T8	600537	0	0	0
T9	324455	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	210118	0	0	0
T20	372320	1	0	0
T21	2007444	0	0	0
T22	96510	0	0	0
T23	62733	0	0	0
T24	65073	0	0	0
T25	35640	0	0	0
T26	61005	1	0	0
T37	0	4	0	0
T38	0	2	0	0
T53	130438	0	0	0
T54	77447	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	100412	0	0	0
T70	233906	0	0	0
T71	69524	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1369	0	0
T1	41702	2	0	0
T2	1979872	17	0	0
T3	322192	0	0	0
T4	49764	0	0	0
T5	1106472	12	0	0
T6	3840428	0	0	0
T16	0	3	0	0
T17	0	19	0	0
T19	0	10	0	0
T20	0	9	0	0
T21	2676592	3	0	0
T22	128680	0	0	0
T23	83644	0	0	0
T24	86764	0	0	0
T25	23760	0	0	0
T36	0	1	0	0
T52	0	4	0	0
T53	0	9	0	0
T54	0	1	0	0
T58	0	4	0	0
T69	0	3	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329322141	0	0
T1	83404	53765	0	0
T2	1979872	1422936	0	0
T3	322192	241825	0	0
T4	49764	3424	0	0
T5	1106472	295946	0	0
T6	3840428	963613	0	0
T21	2676592	1006553	0	0
T22	128680	128296	0	0
T23	83644	58848	0	0
T24	86764	78907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3153	0	0
T1	62553	4	0	0
T2	1979872	38	0	0
T3	322192	1	0	0
T4	49764	0	0	0
T5	1106472	15	0	0
T6	3840428	3	0	0
T7	0	1	0	0
T16	0	4	0	0
T17	0	39	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	2676592	8	0	0
T22	128680	0	0	0
T23	83644	1	0	0
T24	86764	0	0	0
T25	11880	1	0	0
T36	0	5	0	0
T52	0	3	0	0
T53	0	8	0	0
T54	0	1	0	0
T72	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3093	0	0
T1	62553	4	0	0
T2	1979872	37	0	0
T3	322192	1	0	0
T4	49764	0	0	0
T5	1106472	15	0	0
T6	3840428	3	0	0
T7	0	1	0	0
T16	0	4	0	0
T17	0	39	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	2676592	8	0	0
T22	128680	0	0	0
T23	83644	1	0	0
T24	86764	0	0	0
T25	11880	1	0	0
T36	0	5	0	0
T52	0	3	0	0
T53	0	8	0	0
T54	0	1	0	0
T72	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3025	0	0
T1	62553	4	0	0
T2	1979872	36	0	0
T3	322192	1	0	0
T4	49764	0	0	0
T5	1106472	15	0	0
T6	3840428	3	0	0
T7	0	1	0	0
T16	0	4	0	0
T17	0	39	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	2676592	8	0	0
T22	128680	0	0	0
T23	83644	1	0	0
T24	86764	0	0	0
T25	11880	1	0	0
T36	0	5	0	0
T52	0	3	0	0
T53	0	8	0	0
T54	0	1	0	0
T72	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2977	0	0
T1	62553	4	0	0
T2	1979872	35	0	0
T3	322192	1	0	0
T4	49764	0	0	0
T5	1106472	15	0	0
T6	3840428	3	0	0
T7	0	1	0	0
T16	0	4	0	0
T17	0	37	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	2676592	8	0	0
T22	128680	0	0	0
T23	83644	1	0	0
T24	86764	0	0	0
T25	11880	1	0	0
T36	0	5	0	0
T52	0	3	0	0
T53	0	8	0	0
T54	0	1	0	0
T72	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4717	0	0
T2	1979872	14	0	0
T3	322192	0	0	0
T4	49764	0	0	0
T5	1106472	0	0	0
T6	3840428	0	0	0
T16	0	4	0	0
T17	0	13	0	0
T19	0	21	0	0
T20	0	78	0	0
T21	2676592	19	0	0
T22	128680	0	0	0
T23	83644	0	0	0
T24	86764	1	0	0
T25	47520	3	0	0
T26	0	1	0	0
T36	0	3	0	0
T52	0	6	0	0
T53	0	13	0	0
T54	0	1	0	0
T55	0	9	0	0
T71	0	5	0	0
T72	0	7	0	0
T73	0	7	0	0
T79	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	530785	0	0
T2	1979872	2837	0	0
T3	322192	0	0	0
T4	49764	0	0	0
T5	1106472	0	0	0
T6	3840428	0	0	0
T16	0	172	0	0
T17	0	579	0	0
T19	0	2474	0	0
T20	0	9177	0	0
T21	2676592	3067	0	0
T22	128680	0	0	0
T23	83644	0	0	0
T24	86764	148	0	0
T25	47520	162	0	0
T26	0	9	0	0
T36	0	1737	0	0
T52	0	498	0	0
T53	0	1243	0	0
T54	0	185	0	0
T55	0	1809	0	0
T71	0	599	0	0
T72	0	1029	0	0
T73	0	1459	0	0
T79	0	551	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4255	0	0
T2	989936	8	0	0
T3	161096	0	0	0
T4	24882	0	0	0
T5	1106472	0	0	0
T6	3840428	0	0	0
T7	758216	0	0	0
T16	1316914	3	0	0
T17	0	8	0	0
T19	0	21	0	0
T20	0	78	0	0
T21	2676592	16	0	0
T22	128680	0	0	0
T23	83644	0	0	0
T24	86764	1	0	0
T25	47520	2	0	0
T36	140636	1	0	0
T52	0	3	0	0
T53	0	10	0	0
T54	0	1	0	0
T55	0	9	0	0
T71	0	15	0	0
T72	0	4	0	0
T73	0	6	0	0
T74	0	1	0	0
T75	0	2	0	0
T79	0	4	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	306	0	0
T2	1484904	3	0	0
T3	241644	0	0	0
T4	37323	0	0	0
T5	829854	0	0	0
T6	2880321	0	0	0
T7	379108	0	0	0
T16	658457	0	0	0
T17	380668	2	0	0
T18	46012	0	0	0
T21	2007444	3	0	0
T22	96510	0	0	0
T23	62733	0	0	0
T24	65073	0	0	0
T25	47520	0	0	0
T36	70318	2	0	0
T38	0	6	0	0
T44	0	8	0	0
T45	0	1	0	0
T47	0	4	0	0
T49	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T72	25620	3	0	0
T73	28377	1	0	0
T75	0	3	0	0
T79	39217	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	515233	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5832	0	0
T12	180952	1498	0	0
T13	0	1411	0	0
T14	0	753	0	0
T41	0	713	0	0
T42	0	1457	0	0
T43	1390184	0	0	0
T44	447476	0	0	0
T45	76148	0	0	0
T46	1495760	0	0	0
T47	1243420	0	0	0
T48	1156996	0	0	0
T49	101792	0	0	0
T50	153192	0	0	0
T51	284156	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4872	0	0
T12	180952	1258	0	0
T13	0	1171	0	0
T14	0	633	0	0
T41	0	593	0	0
T42	0	1217	0	0
T43	1390184	0	0	0
T44	447476	0	0	0
T45	76148	0	0	0
T46	1495760	0	0	0
T47	1243420	0	0	0
T48	1156996	0	0	0
T49	101792	0	0	0
T50	153192	0	0	0
T51	284156	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	83404	83168	0	0
T2	1979872	1979724	0	0
T3	322192	321652	0	0
T4	49764	49148	0	0
T5	1106472	1106440	0	0
T6	3840428	3840156	0	0
T21	2676592	2676556	0	0
T22	128680	128300	0	0
T23	83644	83412	0	0
T24	86764	86452	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T21
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T21,T24
1	1	1	Covered	T2,T25,T72

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T72
0	1	Covered	T2,T72,T55
1	0	Covered	T2,T17,T26

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T25,T72
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T17,T26

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T72
1	0	Not Covered
1	1	Covered	T2,T72,T55

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T23,T36

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T2,T3,T21

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T21,T17

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T21
1	Covered	T1,T2,T21

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T72
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T72,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T72
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T72
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T87,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T19,T38
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T39,T40,T60
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T19,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T21,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	757565810	339	0	0
CheckAccumTrig0_A	757565810	1036	0	0
CheckAccumTrig1_A	757565810	75	0	0
CheckClr_A	757565810	571	0	0
CheckEn_A	757331867	285611615	0	0
CheckPhase0_A	757565810	1170	0	0
CheckPhase1_A	757565810	1142	0	0
CheckPhase2_A	757565810	1114	0	0
CheckPhase3_A	757565810	1093	0	0
CheckTimeout0_A	757565810	1336	0	0
CheckTimeoutSt1_A	757565810	146339	0	0
CheckTimeoutSt2_A	757565810	1186	0	0
CheckTimeoutStTrig_A	757565810	75	0	0
ErrorStAllEscAsserted_A	757565810	1475	0	0
ErrorStIsTerminal_A	757565810	1235	0	0
u_state_regs_A	757565810	757389604	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	339	0	0
T12	45238	79	0	0
T13	0	96	0	0
T14	0	46	0	0
T41	0	36	0	0
T42	0	82	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1036	0	0
T1	20851	1	0	0
T2	494968	7	0	0
T3	80548	1	0	0
T4	12441	0	0	0
T5	276618	2	0	0
T6	960107	1	0	0
T17	0	15	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	1	0	0
T24	21691	0	0	0
T36	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	75	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T26	0	1	0	0
T37	0	4	0	0
T38	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	571	0	0
T2	494968	3	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	1	0	0
T6	960107	0	0	0
T17	0	10	0	0
T19	0	5	0	0
T20	0	6	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T53	0	3	0	0
T72	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757331867	285611615	0	0
T1	20851	17293	0	0
T2	494968	807129	0	0
T3	80548	589	0	0
T4	12441	850	0	0
T5	276618	14880	0	0
T6	960107	582	0	0
T21	669148	179224	0	0
T22	32170	32074	0	0
T23	20911	6195	0	0
T24	21691	21612	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1170	0	0
T1	20851	1	0	0
T2	494968	9	0	0
T3	80548	1	0	0
T4	12441	0	0	0
T5	276618	2	0	0
T6	960107	1	0	0
T17	0	16	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	1	0	0
T24	21691	0	0	0
T36	0	1	0	0
T72	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1142	0	0
T1	20851	1	0	0
T2	494968	8	0	0
T3	80548	1	0	0
T4	12441	0	0	0
T5	276618	2	0	0
T6	960107	1	0	0
T17	0	16	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	1	0	0
T24	21691	0	0	0
T36	0	1	0	0
T72	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1114	0	0
T1	20851	1	0	0
T2	494968	8	0	0
T3	80548	1	0	0
T4	12441	0	0	0
T5	276618	2	0	0
T6	960107	1	0	0
T17	0	16	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	1	0	0
T24	21691	0	0	0
T36	0	1	0	0
T72	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1093	0	0
T1	20851	1	0	0
T2	494968	8	0	0
T3	80548	1	0	0
T4	12441	0	0	0
T5	276618	2	0	0
T6	960107	1	0	0
T17	0	15	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	1	0	0
T24	21691	0	0	0
T36	0	1	0	0
T72	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1336	0	0
T2	494968	9	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	2	0	0
T20	0	76	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	2	0	0
T26	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T72	0	3	0	0
T73	0	1	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	146339	0	0
T2	494968	1634	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	56	0	0
T20	0	8827	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	106	0	0
T26	0	9	0	0
T53	0	93	0	0
T54	0	185	0	0
T72	0	446	0	0
T73	0	253	0	0
T79	0	161	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1186	0	0
T2	494968	7	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	1	0	0
T20	0	75	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	75	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T38	0	6	0	0
T44	0	7	0	0
T55	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1475	0	0
T12	45238	402	0	0
T13	0	319	0	0
T14	0	201	0	0
T41	0	178	0	0
T42	0	375	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1235	0	0
T12	45238	342	0	0
T13	0	259	0	0
T14	0	171	0	0
T41	0	148	0	0
T42	0	315	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	757389604	0	0
T1	20851	20792	0	0
T2	494968	494931	0	0
T3	80548	80413	0	0
T4	12441	12287	0	0
T5	276618	276610	0	0
T6	960107	960039	0	0
T21	669148	669139	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	21613	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T21
1	0	1	Covered	T2,T7,T86
1	1	0	Covered	T2,T21,T24
1	1	1	Covered	T2,T21,T16

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T16
0	1	Covered	T2,T36,T72
1	0	Covered	T2,T17,T38

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T21,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T17,T38

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T16
1	0	Not Covered
1	1	Covered	T2,T36,T72

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T1,T2,T5

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T2,T36,T17

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T21,T16

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T1,T2,T6

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T36,T72
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T16,T36
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T89,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T90,T91,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T93,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T95,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	757565810	309	0	0
CheckAccumTrig0_A	757565810	555	0	0
CheckAccumTrig1_A	757565810	28	0	0
CheckClr_A	757565810	255	0	0
CheckEn_A	757331867	343965398	0	0
CheckPhase0_A	757565810	646	0	0
CheckPhase1_A	757565810	635	0	0
CheckPhase2_A	757565810	626	0	0
CheckPhase3_A	757565810	613	0	0
CheckTimeout0_A	757565810	1155	0	0
CheckTimeoutSt1_A	757565810	133189	0	0
CheckTimeoutSt2_A	757565810	1055	0	0
CheckTimeoutStTrig_A	757565810	72	0	0
ErrorStAllEscAsserted_A	757565810	1444	0	0
ErrorStIsTerminal_A	757565810	1204	0	0
u_state_regs_A	757565810	757389604	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	309	0	0
T12	45238	82	0	0
T13	0	62	0	0
T14	0	46	0	0
T41	0	43	0	0
T42	0	76	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	555	0	0
T1	20851	2	0	0
T2	494968	15	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	4	0	0
T6	960107	1	0	0
T7	0	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	28	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	2	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T38	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	255	0	0
T1	20851	1	0	0
T2	494968	12	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	3	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	5	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757331867	343965398	0	0
T1	20851	9555	0	0
T2	494968	345686	0	0
T3	80548	80412	0	0
T4	12441	854	0	0
T5	276618	2212	0	0
T6	960107	586	0	0
T21	669148	110124	0	0
T22	32170	32074	0	0
T23	20911	10949	0	0
T24	21691	21612	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	646	0	0
T1	20851	2	0	0
T2	494968	17	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	4	0	0
T6	960107	1	0	0
T7	0	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	2	0	0
T72	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	635	0	0
T1	20851	2	0	0
T2	494968	17	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	4	0	0
T6	960107	1	0	0
T7	0	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	2	0	0
T72	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	626	0	0
T1	20851	2	0	0
T2	494968	16	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	4	0	0
T6	960107	1	0	0
T7	0	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	2	0	0
T72	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	613	0	0
T1	20851	2	0	0
T2	494968	15	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	4	0	0
T6	960107	1	0	0
T7	0	1	0	0
T16	0	1	0	0
T17	0	8	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	2	0	0
T72	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1155	0	0
T2	494968	2	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	7	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	9	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	3	0	0
T53	0	1	0	0
T72	0	3	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	133189	0	0
T2	494968	938	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	44	0	0
T17	0	307	0	0
T19	0	609	0	0
T20	0	350	0	0
T21	669148	939	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1737	0	0
T53	0	16	0	0
T72	0	381	0	0
T73	0	357	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1055	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T7	379108	0	0	0
T16	658457	1	0	0
T17	0	5	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	9	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	70318	1	0	0
T71	0	6	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	72	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T59	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1444	0	0
T12	45238	338	0	0
T13	0	338	0	0
T14	0	183	0	0
T41	0	203	0	0
T42	0	382	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1204	0	0
T12	45238	278	0	0
T13	0	278	0	0
T14	0	153	0	0
T41	0	173	0	0
T42	0	322	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	757389604	0	0
T1	20851	20792	0	0
T2	494968	494931	0	0
T3	80548	80413	0	0
T4	12441	12287	0	0
T5	276618	276610	0	0
T6	960107	960039	0	0
T21	669148	669139	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	21613	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T21,T6

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T21,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T21,T24
1	0	1	Covered	T2,T17,T53
1	1	0	Covered	T2,T21,T24
1	1	1	Covered	T2,T21,T24

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T24
0	1	Covered	T2,T21,T17
1	0	Covered	T2,T16,T56

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T21,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T56

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T24
1	0	Not Covered
1	1	Covered	T2,T21,T17

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T6
1	Covered	T2,T21,T17

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T6
1	Covered	T16,T36,T17

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T16
1	Covered	T2,T6,T16

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T6
1	Covered	T2,T21,T17

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T17

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T36

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T24,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T97,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T21,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T21,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T89,T99,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T21,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T21,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T100,T101,T102
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T21,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T21,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T103,T104,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T21,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T21,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T21,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T21,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	757565810	278	0	0
CheckAccumTrig0_A	757565810	610	0	0
CheckAccumTrig1_A	757565810	26	0	0
CheckClr_A	757565810	287	0	0
CheckEn_A	757331867	317619368	0	0
CheckPhase0_A	757565810	704	0	0
CheckPhase1_A	757565810	693	0	0
CheckPhase2_A	757565810	675	0	0
CheckPhase3_A	757565810	668	0	0
CheckTimeout0_A	757565810	1286	0	0
CheckTimeoutSt1_A	757565810	138809	0	0
CheckTimeoutSt2_A	757565810	1180	0	0
CheckTimeoutStTrig_A	757565810	80	0	0
ErrorStAllEscAsserted_A	757565810	1451	0	0
ErrorStIsTerminal_A	757565810	1211	0	0
u_state_regs_A	757565810	757389604	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	278	0	0
T12	45238	58	0	0
T13	0	80	0	0
T14	0	40	0	0
T41	0	31	0	0
T42	0	69	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	610	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1	0	0
T53	0	4	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	26	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	1	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T92	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	287	0	0
T2	494968	2	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	4	0	0
T19	0	1	0	0
T21	669148	2	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T53	0	3	0	0
T54	0	1	0	0
T58	0	4	0	0
T76	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757331867	317619368	0	0
T1	20851	20791	0	0
T2	494968	121348	0	0
T3	80548	80412	0	0
T4	12441	858	0	0
T5	276618	276609	0	0
T6	960107	2407	0	0
T21	669148	145992	0	0
T22	32170	32074	0	0
T23	20911	20852	0	0
T24	21691	14071	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	704	0	0
T2	494968	7	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	1	0	0
T16	0	2	0	0
T17	0	11	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	693	0	0
T2	494968	7	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	1	0	0
T16	0	2	0	0
T17	0	11	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	675	0	0
T2	494968	7	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	1	0	0
T16	0	2	0	0
T17	0	11	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	668	0	0
T2	494968	7	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	1	0	0
T16	0	2	0	0
T17	0	11	0	0
T19	0	6	0	0
T20	0	2	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T36	0	1	0	0
T53	0	5	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1286	0	0
T2	494968	2	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	3	0	0
T17	0	2	0	0
T19	0	13	0	0
T21	669148	8	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	1	0	0
T25	11880	0	0	0
T53	0	6	0	0
T55	0	9	0	0
T71	0	5	0	0
T79	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	138809	0	0
T2	494968	43	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T16	0	128	0	0
T17	0	20	0	0
T19	0	1675	0	0
T21	669148	1860	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	148	0	0
T25	11880	0	0	0
T53	0	607	0	0
T55	0	1809	0	0
T71	0	599	0	0
T79	0	131	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1180	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T7	379108	0	0	0
T16	658457	2	0	0
T19	0	13	0	0
T21	669148	5	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	1	0	0
T25	11880	0	0	0
T36	70318	0	0	0
T53	0	5	0	0
T55	0	9	0	0
T71	0	5	0	0
T75	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	80	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	2	0	0
T21	669148	3	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T40	0	1	0	0
T47	0	4	0	0
T53	0	1	0	0
T58	0	1	0	0
T75	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1451	0	0
T12	45238	361	0	0
T13	0	372	0	0
T14	0	196	0	0
T41	0	152	0	0
T42	0	370	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1211	0	0
T12	45238	301	0	0
T13	0	312	0	0
T14	0	166	0	0
T41	0	122	0	0
T42	0	310	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	757389604	0	0
T1	20851	20792	0	0
T2	494968	494931	0	0
T3	80548	80413	0	0
T4	12441	12287	0	0
T5	276618	276610	0	0
T6	960107	960039	0	0
T21	669148	669139	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	21613	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T21

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T21,T25
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T2,T21,T24
1	1	1	Covered	T2,T21,T25

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T25
0	1	Covered	T25,T52,T20
1	0	Covered	T53,T55,T56

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T21,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T53,T55,T56

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T25
1	0	Not Covered
1	1	Covered	T25,T52,T20

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T2,T53,T19

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T2,T5,T25

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T5
1	Covered	T1,T16,T17

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T2,T21,T19

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T25

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T21,T53

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T15
IdleSt	175	Covered	T15
Phase0St	146	Covered	T15
Phase1St	192	Covered	T15
Phase2St	209	Covered	T15
Phase3St	227	Covered	T15
TerminalSt	243	Covered	T15
TimeoutSt	153	Covered	T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T15
IdleSt->Phase0St	146	Covered	T15
IdleSt->TimeoutSt	153	Covered	T15
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T15
Phase0St->Phase1St	192	Covered	T15
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T15
Phase1St->Phase2St	209	Covered	T15
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T15
Phase2St->Phase3St	227	Covered	T15
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T15
Phase3St->TerminalSt	243	Covered	T15
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T15
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T15
TimeoutSt->Phase0St	166	Covered	T15

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T52,T53
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T72
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T77,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T89,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T48,T111,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T114,T115,T66
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	757565810	287	0	0
CheckAccumTrig0_A	757565810	535	0	0
CheckAccumTrig1_A	757565810	27	0	0
CheckClr_A	757565810	256	0	0
CheckEn_A	757331867	382125760	0	0
CheckPhase0_A	757565810	633	0	0
CheckPhase1_A	757565810	623	0	0
CheckPhase2_A	757565810	610	0	0
CheckPhase3_A	757565810	603	0	0
CheckTimeout0_A	757565810	940	0	0
CheckTimeoutSt1_A	757565810	112448	0	0
CheckTimeoutSt2_A	757565810	834	0	0
CheckTimeoutStTrig_A	757565810	79	0	0
ErrorStAllEscAsserted_A	757565810	1462	0	0
ErrorStIsTerminal_A	757565810	1222	0	0
u_state_regs_A	757565810	757389604	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	287	0	0
T12	45238	80	0	0
T13	0	69	0	0
T14	0	36	0	0
T41	0	40	0	0
T42	0	62	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	535	0	0
T1	20851	1	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	9	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	0	7	0	0
T20	0	1	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T36	0	1	0	0
T53	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	27	0	0
T8	600537	0	0	0
T9	324455	0	0	0
T19	210118	0	0	0
T20	372320	0	0	0
T26	61005	0	0	0
T47	0	1	0	0
T53	130438	1	0	0
T54	77447	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	100412	0	0	0
T70	233906	0	0	0
T71	69524	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	256	0	0
T1	20851	1	0	0
T2	494968	0	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	8	0	0
T6	960107	0	0	0
T16	0	1	0	0
T19	0	4	0	0
T20	0	3	0	0
T21	669148	0	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T52	0	3	0	0
T53	0	2	0	0
T56	0	2	0	0
T69	0	3	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757331867	382125760	0	0
T1	20851	6126	0	0
T2	494968	148773	0	0
T3	80548	80412	0	0
T4	12441	862	0	0
T5	276618	2245	0	0
T6	960107	960038	0	0
T21	669148	571213	0	0
T22	32170	32074	0	0
T23	20911	20852	0	0
T24	21691	21612	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	633	0	0
T1	20851	1	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	9	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	623	0	0
T1	20851	1	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	9	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	610	0	0
T1	20851	1	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	9	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	603	0	0
T1	20851	1	0	0
T2	494968	5	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	9	0	0
T6	960107	0	0	0
T16	0	1	0	0
T17	0	3	0	0
T21	669148	1	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	940	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T21	669148	2	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	1	0	0
T52	0	6	0	0
T53	0	4	0	0
T72	0	1	0	0
T73	0	4	0	0
T79	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	112448	0	0
T2	494968	222	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	196	0	0
T19	0	190	0	0
T21	669148	268	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	56	0	0
T52	0	498	0	0
T53	0	527	0	0
T72	0	202	0	0
T73	0	849	0	0
T79	0	259	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	834	0	0
T2	494968	1	0	0
T3	80548	0	0	0
T4	12441	0	0	0
T5	276618	0	0	0
T6	960107	0	0	0
T17	0	2	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	669148	2	0	0
T22	32170	0	0	0
T23	20911	0	0	0
T24	21691	0	0	0
T25	11880	0	0	0
T52	0	3	0	0
T53	0	3	0	0
T72	0	1	0	0
T73	0	4	0	0
T79	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	79	0	0
T7	379108	0	0	0
T16	658457	0	0	0
T17	380668	0	0	0
T18	46012	0	0	0
T20	0	4	0	0
T25	11880	1	0	0
T36	70318	0	0	0
T38	0	2	0	0
T52	0	3	0	0
T72	25620	0	0	0
T73	28377	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T79	39217	0	0	0
T85	0	4	0	0
T86	515233	0	0	0
T111	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1462	0	0
T12	45238	397	0	0
T13	0	382	0	0
T14	0	173	0	0
T41	0	180	0	0
T42	0	330	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	1222	0	0
T12	45238	337	0	0
T13	0	322	0	0
T14	0	143	0	0
T41	0	150	0	0
T42	0	270	0	0
T43	347546	0	0	0
T44	111869	0	0	0
T45	19037	0	0	0
T46	373940	0	0	0
T47	310855	0	0	0
T48	289249	0	0	0
T49	25448	0	0	0
T50	38298	0	0	0
T51	71039	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757565810	757389604	0	0
T1	20851	20792	0	0
T2	494968	494931	0	0
T3	80548	80413	0	0
T4	12441	12287	0	0
T5	276618	276610	0	0
T6	960107	960039	0	0
T21	669148	669139	0	0
T22	32170	32075	0	0
T23	20911	20853	0	0
T24	21691	21613	0	0