Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65411666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32007591

1

T12

4057

T22

6

T23

4240

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14691402	1			T12	1831		T22	11		T23	5547
values[0x0]	40013722	1			T12	1091		T22	4		T23	4012
values[0x1]	42714133	1			T12	1136		T22	7		T23	4015

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55462435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41956822

1

T12

4058

T22

8

T23

6106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	310237	1			T12	7		T23	44		T24	2
valid_sources[0x01]	304469	1			T12	14		T23	56		T24	11
valid_sources[0x02]	313467	1			T12	10		T23	57		T24	2
valid_sources[0x03]	311691	1			T12	12		T23	50		T24	6
valid_sources[0x04]	320317	1			T12	19		T23	58		T24	2
valid_sources[0x05]	312588	1			T12	28		T23	53		T24	8
valid_sources[0x06]	311060	1			T12	15		T23	56		T24	2
valid_sources[0x07]	317282	1			T12	15		T23	43		T24	10
valid_sources[0x08]	303896	1			T12	21		T23	51		T24	11
valid_sources[0x09]	301176	1			T12	18		T23	47		T24	3
valid_sources[0x0a]	300147	1			T12	16		T23	46		T24	9
valid_sources[0x0b]	742105	1			T12	11		T23	35		T24	10
valid_sources[0x0c]	328532	1			T12	19		T23	42		T24	4
valid_sources[0x0d]	302366	1			T12	4		T23	58		T25	4
valid_sources[0x0e]	523953	1			T12	13		T23	55		T24	1
valid_sources[0x0f]	311427	1			T12	16		T23	69		T24	2
valid_sources[0x10]	588807	1			T12	21		T23	51		T24	1
valid_sources[0x11]	313494	1			T12	13		T23	46		T24	4
valid_sources[0x12]	311047	1			T12	23		T23	39		T24	5
valid_sources[0x13]	301818	1			T12	13		T23	44		T24	4
valid_sources[0x14]	316992	1			T12	9		T23	43		T24	5
valid_sources[0x15]	886062	1			T12	37		T23	55		T24	2
valid_sources[0x16]	310918	1			T12	11		T23	44		T24	3
valid_sources[0x17]	664152	1			T12	6		T23	49		T24	7
valid_sources[0x18]	310335	1			T12	14		T23	50		T24	3
valid_sources[0x19]	314292	1			T12	27		T23	48		T24	8
valid_sources[0x1a]	302073	1			T12	10		T23	53		T24	5
valid_sources[0x1b]	306026	1			T12	11		T23	47		T24	6
valid_sources[0x1c]	780987	1			T12	8		T23	41		T24	8
valid_sources[0x1d]	325507	1			T12	33		T23	46		T24	8
valid_sources[0x1e]	305015	1			T12	8		T23	50		T24	5
valid_sources[0x1f]	312892	1			T12	19		T23	51		T24	10
valid_sources[0x20]	581346	1			T12	20		T23	44		T24	2
valid_sources[0x21]	599269	1			T12	19		T23	62		T24	5
valid_sources[0x22]	321894	1			T12	15		T23	54		T24	8
valid_sources[0x23]	306980	1			T12	16		T23	53		T24	7
valid_sources[0x24]	312785	1			T12	14		T23	53		T24	5
valid_sources[0x25]	308327	1			T12	18		T23	67		T24	7
valid_sources[0x26]	331454	1			T12	13		T23	46		T24	5
valid_sources[0x27]	318494	1			T12	15		T23	64		T24	5
valid_sources[0x28]	309476	1			T12	23		T23	55		T24	7
valid_sources[0x29]	312736	1			T12	21		T23	62		T24	6
valid_sources[0x2a]	307438	1			T12	28		T23	69		T24	2
valid_sources[0x2b]	317311	1			T12	20		T23	42		T24	7
valid_sources[0x2c]	309439	1			T12	21		T23	51		T24	1
valid_sources[0x2d]	307987	1			T12	15		T23	45		T24	3
valid_sources[0x2e]	592519	1			T12	12		T23	54		T24	11
valid_sources[0x2f]	310815	1			T12	16		T23	56		T24	4
valid_sources[0x30]	675549	1			T12	13		T23	43		T24	16
valid_sources[0x31]	309261	1			T12	12		T23	58		T24	3
valid_sources[0x32]	305245	1			T12	18		T23	51		T24	6
valid_sources[0x33]	305129	1			T12	14		T23	49		T24	6
valid_sources[0x34]	315568	1			T12	6		T23	61		T24	7
valid_sources[0x35]	315029	1			T12	15		T23	41		T24	8
valid_sources[0x36]	317613	1			T12	26		T23	49		T24	5
valid_sources[0x37]	699877	1			T12	23		T23	51		T24	3
valid_sources[0x38]	309489	1			T12	23		T23	54		T24	4
valid_sources[0x39]	317853	1			T12	12		T23	61		T24	16
valid_sources[0x3a]	324517	1			T12	26		T23	48		T24	4
valid_sources[0x3b]	313997	1			T12	9		T23	50		T24	4
valid_sources[0x3c]	304764	1			T12	15		T23	55		T24	4
valid_sources[0x3d]	303391	1			T12	21		T23	43		T24	7
valid_sources[0x3e]	304816	1			T12	6		T23	45		T24	3
valid_sources[0x3f]	301313	1			T12	21		T23	51		T24	4
valid_sources[0x40]	351800	1			T12	16		T23	61		T24	5
valid_sources[0x41]	310012	1			T12	18		T23	52		T24	7
valid_sources[0x42]	315573	1			T12	12		T23	61		T24	7
valid_sources[0x43]	313758	1			T12	11		T23	55		T24	3
valid_sources[0x44]	616355	1			T12	19		T23	41		T24	2
valid_sources[0x45]	310247	1			T12	18		T23	51		T24	2
valid_sources[0x46]	313827	1			T12	11		T23	66		T24	3
valid_sources[0x47]	309645	1			T12	12		T23	55		T24	6
valid_sources[0x48]	310528	1			T12	3		T23	53		T24	1
valid_sources[0x49]	306495	1			T12	18		T23	61		T24	1
valid_sources[0x4a]	297594	1			T12	13		T23	42		T24	8
valid_sources[0x4b]	321036	1			T12	12		T23	51		T24	3
valid_sources[0x4c]	309460	1			T12	18		T23	52		T24	7
valid_sources[0x4d]	306691	1			T12	21		T23	65		T24	4
valid_sources[0x4e]	309498	1			T12	20		T23	57		T24	2
valid_sources[0x4f]	306424	1			T12	20		T23	59		T24	4
valid_sources[0x50]	308292	1			T12	16		T23	62		T24	5
valid_sources[0x51]	797499	1			T12	23		T23	50		T24	3
valid_sources[0x52]	313947	1			T12	5		T23	49		T24	5
valid_sources[0x53]	310397	1			T12	18		T23	50		T24	6
valid_sources[0x54]	338396	1			T12	23		T23	59		T24	6
valid_sources[0x55]	325487	1			T12	13		T23	44		T24	8
valid_sources[0x56]	328336	1			T12	28		T23	59		T24	4
valid_sources[0x57]	321676	1			T12	14		T23	43		T24	6
valid_sources[0x58]	326167	1			T12	19		T23	41		T24	3
valid_sources[0x59]	326709	1			T12	19		T23	49		T24	7
valid_sources[0x5a]	310388	1			T12	6		T23	57		T24	4
valid_sources[0x5b]	334028	1			T12	17		T23	60		T24	2
valid_sources[0x5c]	321576	1			T12	19		T23	53		T24	4
valid_sources[0x5d]	840947	1			T12	14		T23	58		T24	2
valid_sources[0x5e]	315028	1			T12	19		T23	39		T24	4
valid_sources[0x5f]	319456	1			T12	14		T23	54		T24	5
valid_sources[0x60]	305772	1			T12	7		T23	49		T24	6
valid_sources[0x61]	530662	1			T12	18		T22	22		T23	59
valid_sources[0x62]	313982	1			T12	12		T23	62		T24	2
valid_sources[0x63]	301572	1			T12	13		T23	65		T24	1
valid_sources[0x64]	299919	1			T12	11		T23	64		T24	6
valid_sources[0x65]	707407	1			T12	8		T23	49		T24	4
valid_sources[0x66]	304065	1			T12	13		T23	54		T24	7
valid_sources[0x67]	308919	1			T12	28		T23	57		T24	3
valid_sources[0x68]	305433	1			T12	11		T23	53		T24	7
valid_sources[0x69]	321132	1			T12	13		T23	56		T24	6
valid_sources[0x6a]	310493	1			T12	14		T23	49		T24	4
valid_sources[0x6b]	308833	1			T12	35		T23	58		T24	8
valid_sources[0x6c]	1251209	1			T12	9		T23	58		T24	7
valid_sources[0x6d]	302074	1			T12	11		T23	54		T24	7
valid_sources[0x6e]	321551	1			T12	11		T23	64		T24	5
valid_sources[0x6f]	322607	1			T12	7		T23	57		T24	5
valid_sources[0x70]	299210	1			T12	10		T23	51		T24	5
valid_sources[0x71]	442718	1			T12	6		T23	51		T24	4
valid_sources[0x72]	307766	1			T12	18		T23	48		T24	6
valid_sources[0x73]	777401	1			T12	13		T23	59		T24	2
valid_sources[0x74]	312848	1			T12	19		T23	77		T24	11
valid_sources[0x75]	312949	1			T12	25		T23	57		T24	5
valid_sources[0x76]	972698	1			T12	17		T23	46		T24	5
valid_sources[0x77]	313231	1			T12	10		T23	50		T24	5
valid_sources[0x78]	316872	1			T12	9		T23	49		T24	9
valid_sources[0x79]	315936	1			T12	14		T23	68		T24	3
valid_sources[0x7a]	317391	1			T12	11		T23	47		T24	10
valid_sources[0x7b]	317459	1			T12	17		T23	51		T24	3
valid_sources[0x7c]	600526	1			T12	13		T23	44		T24	9
valid_sources[0x7d]	316777	1			T12	15		T23	47		T25	4
valid_sources[0x7e]	322516	1			T12	16		T23	35		T24	4
valid_sources[0x7f]	306393	1			T12	20		T23	60		T24	8
valid_sources[0x80]	320954	1			T12	10		T23	63		T24	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7385713

1

T12

1830

T22

5

T23

1485

values[0x0]

all_enables

biggest_size

15470174

1

T12

1091

T22

1

T23

1707

values[0x1]

all_enables

biggest_size

9151704

1

T12

1136

T23

1048

T24

105