Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T74,T117
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13954	0	0
DisabledNoTrigBkwd_A	2147483647	791197	0	0
DisabledNoTrigFwd_A	2147483647	1619346873	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13954	0	0
T4	283164	0	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T13	111079	0	0	0
T18	2014	1056	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T55	11394	0	0	0
T74	4684	1009	0	0
T117	0	874	0	0
T218	0	910	0	0
T219	0	499	0	0
T220	0	1357	0	0
T221	0	369	0	0
T222	0	246	0	0
T223	0	988	0	0
T224	3305	505	0	0
T225	1521	631	0	0
T226	0	238	0	0
T227	0	1266	0	0
T228	0	517	0	0
T229	0	559	0	0
T230	0	753	0	0
T231	0	1047	0	0
T232	0	392	0	0
T233	0	325	0	0
T234	0	413	0	0
T235	115895	0	0	0
T236	247543	0	0	0
T237	14062	0	0	0
T238	53706	0	0	0
T239	110719	0	0	0
T240	88137	0	0	0
T241	80968	0	0	0
T242	83709	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	791197	0	0
T1	47556	22	0	0
T2	384438	6	0	0
T3	243354	0	0	0
T4	1132656	1621	0	0
T5	22971	8	0	0
T6	1586388	3847	0	0
T7	100011	1	0	0
T8	0	22	0	0
T13	111079	7194	0	0
T15	0	665	0	0
T16	0	1665	0	0
T17	41142	0	0	0
T18	6042	36	0	0
T19	69752	0	0	0
T20	99044	0	0	0
T21	22344	0	0	0
T32	54831	33	0	0
T33	0	50	0	0
T34	0	3565	0	0
T40	0	760	0	0
T51	0	153	0	0
T52	0	307	0	0
T53	0	129	0	0
T54	0	1430	0	0
T55	11394	0	0	0
T56	8320	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619346873	0	0
T1	63408	29669	0	0
T2	512584	340214	0	0
T3	324472	162919	0	0
T4	1132656	859070	0	0
T5	30628	16691	0	0
T6	1586388	815085	0	0
T17	54856	38502	0	0
T18	8056	3032	0	0
T19	69752	44320	0	0
T20	99044	28640	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T224,T225,T227
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	741519896	4254	0	0
DisabledNoTrigBkwd_A	741519896	259832	0	0
DisabledNoTrigFwd_A	741519896	339603642	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	4254	0	0
T224	3305	505	0	0
T225	1521	631	0	0
T227	0	1266	0	0
T231	0	1047	0	0
T232	0	392	0	0
T234	0	413	0	0
T235	115895	0	0	0
T236	247543	0	0	0
T237	14062	0	0	0
T238	53706	0	0	0
T239	110719	0	0	0
T240	88137	0	0	0
T241	80968	0	0	0
T242	83709	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	259832	0	0
T1	15852	7	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	7	0	0
T5	7657	0	0	0
T6	396597	2672	0	0
T13	0	2580	0	0
T15	0	200	0	0
T16	0	1108	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	33	0	0
T33	0	18	0	0
T34	0	115	0	0
T52	0	159	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	339603642	0	0
T1	15852	4916	0	0
T2	128146	122934	0	0
T3	81118	3100	0	0
T4	283164	282219	0	0
T5	7657	3013	0	0
T6	396597	15336	0	0
T17	13714	13641	0	0
T18	2014	752	0	0
T19	17438	6914	0	0
T20	24761	594	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T228
1	1	Covered	T1,T2,T5

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	741519896	1573	0	0
DisabledNoTrigBkwd_A	741519896	166037	0	0
DisabledNoTrigFwd_A	741519896	435021886	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1573	0	0
T4	283164	0	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T13	111079	0	0	0
T18	2014	1056	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T55	11394	0	0	0
T228	0	517	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	166037	0	0
T1	15852	5	0	0
T2	128146	6	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	8	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	1449	0	0
T15	0	231	0	0
T16	0	370	0	0
T17	13714	0	0	0
T18	2014	36	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T34	0	422	0	0
T51	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	435021886	0	0
T1	15852	11162	0	0
T2	128146	3156	0	0
T3	81118	81059	0	0
T4	283164	282782	0	0
T5	7657	3027	0	0
T6	396597	396087	0	0
T17	13714	5615	0	0
T18	2014	756	0	0
T19	17438	2642	0	0
T20	24761	2750	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T117,T219
1	1	Covered	T1,T3,T5

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	741519896	3370	0	0
DisabledNoTrigBkwd_A	741519896	181420	0	0
DisabledNoTrigFwd_A	741519896	430430158	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	3370	0	0
T57	905277	0	0	0
T74	4684	1009	0	0
T75	279272	0	0	0
T76	14693	0	0	0
T78	389780	0	0	0
T86	20013	0	0	0
T88	16419	0	0	0
T117	0	874	0	0
T133	388058	0	0	0
T134	110682	0	0	0
T219	0	499	0	0
T223	0	988	0	0
T243	87458	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	181420	0	0
T1	15852	10	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	15	0	0
T5	7657	0	0	0
T6	396597	1175	0	0
T8	0	21	0	0
T13	0	1718	0	0
T16	0	59	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	21	0	0
T34	0	1503	0	0
T52	0	148	0	0
T53	0	129	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	430430158	0	0
T1	15852	2736	0	0
T2	128146	95033	0	0
T3	81118	75588	0	0
T4	283164	281518	0	0
T5	7657	3052	0	0
T6	396597	7075	0	0
T17	13714	13641	0	0
T18	2014	760	0	0
T19	17438	17382	0	0
T20	24761	24690	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T220,T221
1	1	Covered	T1,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	741519896	4757	0	0
DisabledNoTrigBkwd_A	741519896	183908	0	0
DisabledNoTrigFwd_A	741519896	414291187	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	4757	0	0
T64	238464	0	0	0
T94	39379	0	0	0
T104	256356	0	0	0
T124	105230	0	0	0
T218	3985	910	0	0
T220	5119	1357	0	0
T221	0	369	0	0
T222	0	246	0	0
T226	0	238	0	0
T229	0	559	0	0
T230	0	753	0	0
T233	0	325	0	0
T244	57008	0	0	0
T245	71287	0	0	0
T246	450173	0	0	0
T247	57257	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	183908	0	0
T4	283164	1599	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T8	0	1	0	0
T13	111079	1447	0	0
T15	0	234	0	0
T16	0	128	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T33	0	11	0	0
T34	0	1525	0	0
T40	0	760	0	0
T51	0	145	0	0
T54	0	1430	0	0
T55	11394	0	0	0
T56	8320	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	414291187	0	0
T1	15852	10855	0	0
T2	128146	119091	0	0
T3	81118	3172	0	0
T4	283164	12551	0	0
T5	7657	7599	0	0
T6	396597	396587	0	0
T17	13714	5605	0	0
T18	2014	764	0	0
T19	17438	17382	0	0
T20	24761	606	0	0