Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T31
1	1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T2,T18,T20
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T3,T5

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T19
1	0	Covered	T32,T33,T34

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T32,T33,T34

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T1,T5,T19

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T18,T4,T6

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T7,T13,T33

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T5,T4

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T18
1	Covered	T1,T2,T5

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T18,T4

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T5,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T5

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Not Covered
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Not Covered
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Not Covered
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Not Covered
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Not Covered
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Not Covered
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T19,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T13,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T36,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T38,T39
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T40,T41
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T32,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1274	0	0
CheckAccumTrig0_A	2147483647	2463	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1101	0	0
CheckEn_A	2147483647	1271885647	0	0
CheckPhase0_A	2147483647	2800	0	0
CheckPhase1_A	2147483647	2738	0	0
CheckPhase2_A	2147483647	2688	0	0
CheckPhase3_A	2147483647	2641	0	0
CheckTimeout0_A	2147483647	3725	0	0
CheckTimeoutSt1_A	2147483647	418667	0	0
CheckTimeoutSt2_A	2147483647	3345	0	0
CheckTimeoutStTrig_A	2147483647	265	0	0
ErrorStAllEscAsserted_A	2147483647	6435	0	0
ErrorStIsTerminal_A	2147483647	5355	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1274	0	0
T9	83740	120	0	0
T10	0	258	0	0
T11	0	302	0	0
T38	512640	0	0	0
T41	716396	0	0	0
T42	0	310	0	0
T43	0	284	0	0
T44	7828	0	0	0
T45	970100	0	0	0
T46	18380	0	0	0
T47	42892	0	0	0
T48	60884	0	0	0
T49	2378168	0	0	0
T50	302628	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2463	0	0
T1	47556	3	0	0
T2	384438	1	0	0
T3	243354	0	0	0
T4	1132656	3	0	0
T5	22971	1	0	0
T6	1586388	2	0	0
T7	100011	1	0	0
T8	0	2	0	0
T13	111079	25	0	0
T15	0	4	0	0
T16	0	23	0	0
T17	41142	0	0	0
T18	6042	1	0	0
T19	69752	0	0	0
T20	99044	0	0	0
T21	22344	0	0	0
T32	54831	2	0	0
T33	0	2	0	0
T34	0	12	0	0
T40	0	2	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	0	0	0
T14	992682	0	0	0
T15	568588	0	0	0
T32	54831	2	0	0
T33	102506	1	0	0
T34	337325	1	0	0
T35	0	2	0	0
T39	0	1	0	0
T40	971778	0	0	0
T53	263798	0	0	0
T54	305070	2	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T57	905277	1	0	0
T58	14240	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	75664	0	0	0
T73	630556	0	0	0
T74	4684	0	0	0
T75	279272	0	0	0
T76	14693	0	0	0
T77	38149	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1101	0	0
T7	200022	1	0	0
T8	452781	0	0	0
T13	333237	8	0	0
T14	1489023	0	0	0
T15	1137176	0	0	0
T16	306102	13	0	0
T21	22344	1	0	0
T32	109662	3	0	0
T33	153759	0	0	0
T34	337325	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	1943556	1	0	0
T41	0	5	0	0
T51	72451	0	0	0
T52	134287	0	0	0
T53	263798	0	0	0
T54	305070	1	0	0
T55	34182	0	0	0
T56	24960	0	0	0
T59	0	1	0	0
T72	151328	0	0	0
T73	0	2	0	0
T75	0	4	0	0
T78	0	1	0	0
T79	0	3	0	0
T80	0	2	0	0
T81	0	3	0	0
T82	0	1	0	0
T83	0	7	0	0
T84	0	1	0	0
T85	27123	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1271885647	0	0
T1	63408	13965	0	0
T2	512584	340214	0	0
T3	324472	162917	0	0
T4	1132656	300607	0	0
T5	30628	16690	0	0
T6	1586388	801792	0	0
T17	54856	38498	0	0
T18	8056	3032	0	0
T19	69752	44318	0	0
T20	99044	28639	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2800	0	0
T1	63408	4	0	0
T2	512584	1	0	0
T3	324472	0	0	0
T4	1132656	3	0	0
T5	30628	2	0	0
T6	1586388	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T13	0	26	0	0
T15	0	4	0	0
T16	0	16	0	0
T17	54856	0	0	0
T18	8056	1	0	0
T19	69752	1	0	0
T20	99044	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T33	0	3	0	0
T34	0	7	0	0
T40	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2738	0	0
T1	63408	4	0	0
T2	512584	1	0	0
T3	324472	0	0	0
T4	1132656	3	0	0
T5	30628	2	0	0
T6	1586388	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T13	0	25	0	0
T15	0	4	0	0
T16	0	16	0	0
T17	54856	0	0	0
T18	8056	1	0	0
T19	69752	1	0	0
T20	99044	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T33	0	3	0	0
T34	0	7	0	0
T40	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2688	0	0
T1	63408	4	0	0
T2	512584	1	0	0
T3	324472	0	0	0
T4	1132656	3	0	0
T5	30628	2	0	0
T6	1586388	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T13	0	24	0	0
T15	0	4	0	0
T16	0	16	0	0
T17	54856	0	0	0
T18	8056	1	0	0
T19	69752	1	0	0
T20	99044	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T33	0	3	0	0
T34	0	7	0	0
T40	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T1	63408	4	0	0
T2	512584	1	0	0
T3	324472	0	0	0
T4	1132656	3	0	0
T5	30628	2	0	0
T6	1586388	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T13	0	24	0	0
T15	0	4	0	0
T16	0	15	0	0
T17	54856	0	0	0
T18	8056	1	0	0
T19	69752	1	0	0
T20	99044	0	0	0
T21	0	1	0	0
T32	0	3	0	0
T33	0	3	0	0
T34	0	7	0	0
T40	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3725	0	0
T1	47556	3	0	0
T2	384438	0	0	0
T3	243354	16	0	0
T4	849492	0	0	0
T5	22971	1	0	0
T6	1586388	0	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	17	0	0
T17	41142	0	0	0
T18	6042	0	0	0
T19	69752	3	0	0
T20	99044	0	0	0
T21	22344	1	0	0
T32	54831	2	0	0
T33	0	5	0	0
T34	0	3	0	0
T38	0	2	0	0
T54	0	64	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T58	0	2	0	0
T75	0	7	0	0
T79	0	5	0	0
T83	0	6	0	0
T84	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	418667	0	0
T1	47556	337	0	0
T2	384438	0	0	0
T3	243354	2709	0	0
T4	849492	0	0	0
T5	22971	123	0	0
T6	1586388	0	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	1875	0	0
T17	41142	0	0	0
T18	6042	0	0	0
T19	69752	119	0	0
T20	99044	0	0	0
T21	22344	115	0	0
T32	54831	9	0	0
T33	0	442	0	0
T34	0	639	0	0
T38	0	72	0	0
T41	0	514	0	0
T54	0	3622	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T75	0	705	0	0
T79	0	2082	0	0
T83	0	3172	0	0
T84	0	73	0	0
T86	0	1283	0	0
T87	0	17	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3345	0	0
T1	31704	2	0	0
T2	256292	0	0	0
T3	243354	16	0	0
T4	849492	0	0	0
T5	22971	0	0	0
T6	1189791	0	0	0
T8	150927	0	0	0
T13	111079	14	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T17	41142	0	0	0
T18	6042	0	0	0
T19	52314	2	0	0
T20	74283	0	0	0
T21	22344	0	0	0
T33	51253	4	0	0
T35	0	15	0	0
T38	0	2	0	0
T41	0	17	0	0
T54	152535	61	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T57	0	2	0	0
T59	0	2	0	0
T60	0	1	0	0
T73	630556	0	0	0
T74	4684	0	0	0
T75	0	5	0	0
T79	0	11	0	0
T83	0	7	0	0
T84	0	1	0	0
T87	0	28	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	265	0	0
T1	15852	1	0	0
T4	566328	0	0	0
T5	15314	1	0	0
T6	1189791	0	0	0
T7	200022	0	0	0
T8	301854	0	0	0
T13	222158	3	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T17	27428	0	0	0
T18	4028	0	0	0
T19	52314	1	0	0
T20	74283	0	0	0
T21	44688	1	0	0
T32	109662	0	0	0
T33	51253	0	0	0
T34	0	2	0	0
T35	0	3	0	0
T39	0	1	0	0
T41	0	2	0	0
T54	0	1	0	0
T55	22788	0	0	0
T56	16640	0	0	0
T57	905277	0	0	0
T62	0	6	0	0
T75	279272	2	0	0
T76	14693	0	0	0
T79	0	2	0	0
T83	0	11	0	0
T86	0	2	0	0
T87	0	1	0	0
T92	0	1	0	0
T93	0	3	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6435	0	0
T9	83740	703	0	0
T10	0	1474	0	0
T11	0	1440	0	0
T38	512640	0	0	0
T41	716396	0	0	0
T42	0	1409	0	0
T43	0	1409	0	0
T44	7828	0	0	0
T45	970100	0	0	0
T46	18380	0	0	0
T47	42892	0	0	0
T48	60884	0	0	0
T49	2378168	0	0	0
T50	302628	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5355	0	0
T9	83740	583	0	0
T10	0	1234	0	0
T11	0	1200	0	0
T38	512640	0	0	0
T41	716396	0	0	0
T42	0	1169	0	0
T43	0	1169	0	0
T44	7828	0	0	0
T45	970100	0	0	0
T46	18380	0	0	0
T47	42892	0	0	0
T48	60884	0	0	0
T49	2378168	0	0	0
T50	302628	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	63408	63112	0	0
T2	512584	512560	0	0
T3	324472	324236	0	0
T4	1132656	1132616	0	0
T5	30628	30396	0	0
T6	1586388	1586348	0	0
T17	54856	54564	0	0
T18	8056	7832	0	0
T19	69752	69528	0	0
T20	99044	98760	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T2,T20,T32
1	1	0	Covered	T1,T17,T19
1	1	1	Covered	T1,T3,T5

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T5,T13,T34
1	0	Covered	T32,T54,T57

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T54,T57

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T5,T13,T34

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T6,T13,T16

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T33,T52,T40

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T32,T13

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T32
1	Covered	T1,T5,T13

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T6,T32

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T4,T6

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T32,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T32,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T13,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T37,T44
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T97,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T41,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T32,T13,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	741519896	293	0	0
CheckAccumTrig0_A	741519896	879	0	0
CheckAccumTrig1_A	741519896	51	0	0
CheckClr_A	741519896	410	0	0
CheckEn_A	741343977	255430212	0	0
CheckPhase0_A	741519896	1000	0	0
CheckPhase1_A	741519896	979	0	0
CheckPhase2_A	741519896	963	0	0
CheckPhase3_A	741519896	949	0	0
CheckTimeout0_A	741519896	1226	0	0
CheckTimeoutSt1_A	741519896	120126	0	0
CheckTimeoutSt2_A	741519896	1083	0	0
CheckTimeoutStTrig_A	741519896	92	0	0
ErrorStAllEscAsserted_A	741519896	1616	0	0
ErrorStIsTerminal_A	741519896	1346	0	0
u_state_regs_A	741519896	741332080	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	293	0	0
T9	20935	28	0	0
T10	0	44	0	0
T11	0	75	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	86	0	0
T43	0	60	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	879	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T13	0	10	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	51	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	0	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T32	54831	2	0	0
T33	51253	0	0	0
T35	0	2	0	0
T39	0	1	0	0
T54	152535	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T66	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	410	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	4	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T16	153051	9	0	0
T32	54831	3	0	0
T33	51253	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T59	0	1	0	0
T75	0	4	0	0
T79	0	2	0	0
T82	0	1	0	0
T83	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741343977	255430212	0	0
T1	15852	4916	0	0
T2	128146	122934	0	0
T3	81118	3100	0	0
T4	283164	1929	0	0
T5	7657	3013	0	0
T6	396597	2043	0	0
T17	13714	13640	0	0
T18	2014	752	0	0
T19	17438	6914	0	0
T20	24761	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1000	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	1	0	0
T6	396597	1	0	0
T13	0	10	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	979	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	1	0	0
T6	396597	1	0	0
T13	0	10	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	963	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	1	0	0
T6	396597	1	0	0
T13	0	10	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	949	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	1	0	0
T6	396597	1	0	0
T13	0	10	0	0
T15	0	1	0	0
T16	0	12	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1226	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	9	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T13	0	7	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	2	0	0
T20	24761	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T54	0	30	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	120126	0	0
T1	15852	134	0	0
T2	128146	0	0	0
T3	81118	1523	0	0
T4	283164	0	0	0
T5	7657	123	0	0
T6	396597	0	0	0
T13	0	470	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	115	0	0
T20	24761	0	0	0
T32	0	9	0	0
T33	0	161	0	0
T34	0	459	0	0
T54	0	1686	0	0
T75	0	173	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1083	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	9	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	6	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	2	0	0
T20	24761	0	0	0
T33	0	2	0	0
T54	0	29	0	0
T57	0	2	0	0
T75	0	1	0	0
T79	0	8	0	0
T88	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	92	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T13	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T83	0	5	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1616	0	0
T9	20935	184	0	0
T10	0	380	0	0
T11	0	353	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	358	0	0
T43	0	341	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1346	0	0
T9	20935	154	0	0
T10	0	320	0	0
T11	0	293	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	298	0	0
T43	0	281	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	741332080	0	0
T1	15852	15778	0	0
T2	128146	128140	0	0
T3	81118	81059	0	0
T4	283164	283154	0	0
T5	7657	7599	0	0
T6	396597	396587	0	0
T17	13714	13641	0	0
T18	2014	1958	0	0
T19	17438	17382	0	0
T20	24761	24690	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T17
1	0	1	Covered	T2,T18,T20
1	1	0	Covered	T3,T4,T13
1	1	1	Covered	T19,T21,T13

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T13
0	1	Covered	T19,T21,T86
1	0	Covered	T34,T54,T59

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T21,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T34,T54,T59

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T13
1	0	Not Covered
1	1	Covered	T19,T21,T86

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T18,T13,T16

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T7,T13,T16

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T19
1	Covered	T1,T5,T21

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T18
1	Covered	T2,T19,T13

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T18,T21

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T5,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T5,T18

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T54,T75
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T101,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T62,T104,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T39,T95,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T91,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T7,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	741519896	349	0	0
CheckAccumTrig0_A	741519896	546	0	0
CheckAccumTrig1_A	741519896	22	0	0
CheckClr_A	741519896	257	0	0
CheckEn_A	741343977	332891933	0	0
CheckPhase0_A	741519896	623	0	0
CheckPhase1_A	741519896	611	0	0
CheckPhase2_A	741519896	602	0	0
CheckPhase3_A	741519896	587	0	0
CheckTimeout0_A	741519896	495	0	0
CheckTimeoutSt1_A	741519896	70150	0	0
CheckTimeoutSt2_A	741519896	407	0	0
CheckTimeoutStTrig_A	741519896	66	0	0
ErrorStAllEscAsserted_A	741519896	1644	0	0
ErrorStIsTerminal_A	741519896	1374	0	0
u_state_regs_A	741519896	741332080	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	349	0	0
T9	20935	24	0	0
T10	0	94	0	0
T11	0	81	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	78	0	0
T43	0	72	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	546	0	0
T1	15852	1	0	0
T2	128146	1	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	4	0	0
T15	0	1	0	0
T16	0	7	0	0
T17	13714	0	0	0
T18	2014	1	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T34	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	22	0	0
T34	337325	1	0	0
T40	971778	0	0	0
T53	263798	0	0	0
T54	152535	1	0	0
T57	905277	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	75664	0	0	0
T73	630556	0	0	0
T74	4684	0	0	0
T75	279272	0	0	0
T76	14693	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	257	0	0
T7	100011	1	0	0
T8	150927	0	0	0
T13	111079	1	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T16	0	4	0	0
T21	22344	1	0	0
T32	54831	0	0	0
T33	51253	0	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T73	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	3	0	0
T83	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741343977	332891933	0	0
T1	15852	5635	0	0
T2	128146	3156	0	0
T3	81118	81058	0	0
T4	283164	282781	0	0
T5	7657	3027	0	0
T6	396597	396087	0	0
T17	13714	5614	0	0
T18	2014	756	0	0
T19	17438	2642	0	0
T20	24761	2750	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	623	0	0
T1	15852	1	0	0
T2	128146	1	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	4	0	0
T15	0	1	0	0
T17	13714	0	0	0
T18	2014	1	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	611	0	0
T1	15852	1	0	0
T2	128146	1	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	4	0	0
T15	0	1	0	0
T17	13714	0	0	0
T18	2014	1	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	602	0	0
T1	15852	1	0	0
T2	128146	1	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	4	0	0
T15	0	1	0	0
T17	13714	0	0	0
T18	2014	1	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	587	0	0
T1	15852	1	0	0
T2	128146	1	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	1	0	0
T6	396597	0	0	0
T7	0	1	0	0
T13	0	4	0	0
T15	0	1	0	0
T17	13714	0	0	0
T18	2014	1	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	495	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	5	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	22344	1	0	0
T32	54831	0	0	0
T34	0	1	0	0
T54	0	3	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	70150	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	704	0	0
T19	17438	4	0	0
T20	24761	0	0	0
T21	22344	115	0	0
T32	54831	0	0	0
T34	0	21	0	0
T54	0	67	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T75	0	84	0	0
T79	0	494	0	0
T83	0	528	0	0
T84	0	73	0	0
T86	0	860	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	407	0	0
T8	150927	0	0	0
T13	111079	5	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T33	51253	0	0	0
T35	0	13	0	0
T41	0	7	0	0
T54	152535	2	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T59	0	1	0	0
T73	630556	0	0	0
T74	4684	0	0	0
T75	0	1	0	0
T84	0	1	0	0
T87	0	26	0	0
T89	0	2	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	66	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T8	150927	0	0	0
T13	111079	0	0	0
T19	17438	1	0	0
T20	24761	0	0	0
T21	22344	1	0	0
T32	54831	0	0	0
T35	0	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T62	0	1	0	0
T79	0	1	0	0
T83	0	3	0	0
T86	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1644	0	0
T9	20935	163	0	0
T10	0	379	0	0
T11	0	377	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	341	0	0
T43	0	384	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1374	0	0
T9	20935	133	0	0
T10	0	319	0	0
T11	0	317	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	281	0	0
T43	0	324	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	741332080	0	0
T1	15852	15778	0	0
T2	128146	128140	0	0
T3	81118	81059	0	0
T4	283164	283154	0	0
T5	7657	7599	0	0
T6	396597	396587	0	0
T17	13714	13641	0	0
T18	2014	1958	0	0
T19	17438	17382	0	0
T20	24761	24690	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T13,T14,T85
1	1	0	Covered	T3,T4,T19
1	1	1	Covered	T1,T13,T33

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T33
0	1	Covered	T13,T75,T83
1	0	Covered	T33,T58,T41

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T13,T33
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T33,T58,T41

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T33
1	0	Not Covered
1	1	Covered	T13,T75,T83

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T13
1	Covered	T4,T40,T54

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T13,T16,T52

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T13,T33,T34

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T13,T33
1	Covered	T1,T6,T13

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T6,T13,T8

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T6,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T6,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T6,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T33
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T33,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T33
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T54
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T13,T63,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T109,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T38,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T40,T67,T71
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T54,T73,T80
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	741519896	323	0	0
CheckAccumTrig0_A	741519896	547	0	0
CheckAccumTrig1_A	741519896	24	0	0
CheckClr_A	741519896	232	0	0
CheckEn_A	741343977	342239532	0	0
CheckPhase0_A	741519896	612	0	0
CheckPhase1_A	741519896	595	0	0
CheckPhase2_A	741519896	584	0	0
CheckPhase3_A	741519896	575	0	0
CheckTimeout0_A	741519896	788	0	0
CheckTimeoutSt1_A	741519896	100382	0	0
CheckTimeoutSt2_A	741519896	719	0	0
CheckTimeoutStTrig_A	741519896	45	0	0
ErrorStAllEscAsserted_A	741519896	1608	0	0
ErrorStIsTerminal_A	741519896	1338	0	0
u_state_regs_A	741519896	741332080	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	323	0	0
T9	20935	39	0	0
T10	0	73	0	0
T11	0	64	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	64	0	0
T43	0	83	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	547	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T8	0	1	0	0
T13	0	8	0	0
T16	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T34	0	3	0	0
T40	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	24	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T33	51253	1	0	0
T41	0	1	0	0
T58	14240	1	0	0
T68	0	1	0	0
T77	38149	0	0	0
T79	379530	0	0	0
T80	70869	0	0	0
T81	481451	0	0	0
T110	0	2	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	3205	0	0	0
T118	355244	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	232	0	0
T8	150927	0	0	0
T13	111079	3	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T33	51253	0	0	0
T38	0	1	0	0
T40	971778	1	0	0
T41	0	5	0	0
T54	152535	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T72	75664	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T83	0	2	0	0
T84	0	1	0	0
T119	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741343977	342239532	0	0
T1	15852	590	0	0
T2	128146	95033	0	0
T3	81118	75587	0	0
T4	283164	7940	0	0
T5	7657	3052	0	0
T6	396597	7075	0	0
T17	13714	13640	0	0
T18	2014	760	0	0
T19	17438	17381	0	0
T20	24761	24689	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	612	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T8	0	1	0	0
T13	0	8	0	0
T16	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	595	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T8	0	1	0	0
T13	0	7	0	0
T16	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	584	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T8	0	1	0	0
T13	0	6	0	0
T16	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	575	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	1	0	0
T8	0	1	0	0
T13	0	6	0	0
T16	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	788	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	3	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T38	0	2	0	0
T54	0	30	0	0
T58	0	1	0	0
T75	0	3	0	0
T79	0	2	0	0
T83	0	3	0	0
T87	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	100382	0	0
T1	15852	165	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	624	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	5	0	0
T38	0	72	0	0
T41	0	514	0	0
T54	0	1847	0	0
T75	0	328	0	0
T79	0	981	0	0
T83	0	621	0	0
T87	0	17	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	719	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T41	0	3	0	0
T54	0	30	0	0
T75	0	2	0	0
T79	0	2	0	0
T83	0	1	0	0
T91	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	45	0	0
T8	150927	0	0	0
T13	111079	1	0	0
T14	496341	0	0	0
T15	284294	0	0	0
T33	51253	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0
T57	905277	0	0	0
T62	0	2	0	0
T75	279272	1	0	0
T76	14693	0	0	0
T83	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1608	0	0
T9	20935	179	0	0
T10	0	371	0	0
T11	0	377	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	354	0	0
T43	0	327	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1338	0	0
T9	20935	149	0	0
T10	0	311	0	0
T11	0	317	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	294	0	0
T43	0	267	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	741332080	0	0
T1	15852	15778	0	0
T2	128146	128140	0	0
T3	81118	81059	0	0
T4	283164	283154	0	0
T5	7657	7599	0	0
T6	396597	396587	0	0
T17	13714	13641	0	0
T18	2014	1958	0	0
T19	17438	17382	0	0
T20	24761	24690	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	128	89	89	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	299	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
145	1	1
146	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
163	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
172	1	1
173	1	1
175	1	1
176	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE
262	1	1
263	1	1
277	1	1
278	1	1
279	1	1
			MISSING_ELSE
286	4	4
289	4	4
299	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T31
1	1	1	Covered	T4,T13,T8

 LINE       151
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T17
1	0	1	Covered	T20,T13,T8
1	1	0	Covered	T1,T19,T13
1	1	1	Covered	T1,T3,T13

 LINE       165
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T13
0	1	Covered	T1,T13,T34
1	0	Covered	T58,T112,T120

 LINE       165
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T58,T112,T120

 LINE       165
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Covered	T1,T13,T34

 LINE       185
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T8
1	Covered	T4,T13,T33

 LINE       202
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T13,T78,T60

 LINE       219
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T13,T33
1	Covered	T1,T13,T8

 LINE       236
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T51,T16,T34

 LINE       277
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       289
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T13,T33

 LINE       289
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T13

 LINE       289
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T13,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	278	Covered	T12
IdleSt	175	Covered	T12
Phase0St	146	Covered	T12
Phase1St	192	Covered	T12
Phase2St	209	Covered	T12
Phase3St	227	Covered	T12
TerminalSt	243	Covered	T12
TimeoutSt	153	Covered	T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	278	Covered	T12
IdleSt->Phase0St	146	Covered	T12
IdleSt->TimeoutSt	153	Covered	T12
Phase0St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	188	Covered	T12
Phase0St->Phase1St	192	Covered	T12
Phase1St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	205	Covered	T12
Phase1St->Phase2St	209	Covered	T12
Phase2St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	223	Covered	T12
Phase2St->Phase3St	227	Covered	T12
Phase3St->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	239	Covered	T12
Phase3St->TerminalSt	243	Covered	T12
TerminalSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	255	Covered	T12
TimeoutSt->FsmErrorSt	278	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	175	Covered	T12
TimeoutSt->Phase0St	166	Covered	T12

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	138	22	22	100.00
IF	277	2	2	100.00
IF	299	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	145	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	151	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	165	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	172	if (timeout_en_i)
-6-:	187	if (clr_i)
-7-:	191	if (cnt_ge)
-8-:	204	if (clr_i)
-9-:	208	if (cnt_ge)
-10-:	222	if (clr_i)
-11-:	226	if (cnt_ge)
-12-:	238	if (clr_i)
-13-:	242	if (cnt_ge)
-14-:	254	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T33
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T62,T121,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T123,T112,T124
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T123,T125,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T87,T127,T128
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T51,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	277	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	741519896	309	0	0
CheckAccumTrig0_A	741519896	491	0	0
CheckAccumTrig1_A	741519896	18	0	0
CheckClr_A	741519896	202	0	0
CheckEn_A	741343977	341323970	0	0
CheckPhase0_A	741519896	565	0	0
CheckPhase1_A	741519896	553	0	0
CheckPhase2_A	741519896	539	0	0
CheckPhase3_A	741519896	530	0	0
CheckTimeout0_A	741519896	1216	0	0
CheckTimeoutSt1_A	741519896	128009	0	0
CheckTimeoutSt2_A	741519896	1136	0	0
CheckTimeoutStTrig_A	741519896	62	0	0
ErrorStAllEscAsserted_A	741519896	1567	0	0
ErrorStIsTerminal_A	741519896	1297	0	0
u_state_regs_A	741519896	741332080	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	309	0	0
T9	20935	29	0	0
T10	0	47	0	0
T11	0	82	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	82	0	0
T43	0	69	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	491	0	0
T4	283164	1	0	0
T6	396597	0	0	0
T7	100011	0	0	0
T8	0	1	0	0
T13	111079	3	0	0
T15	0	2	0	0
T16	0	2	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T40	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	11394	0	0	0
T56	8320	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	18	0	0
T58	14240	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T77	38149	0	0	0
T79	379530	0	0	0
T80	70869	0	0	0
T81	481451	0	0	0
T82	102231	0	0	0
T83	336632	0	0	0
T102	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T117	3205	0	0	0
T118	355244	0	0	0
T120	0	1	0	0
T126	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	22515	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	202	0	0
T15	284294	1	0	0
T16	153051	1	0	0
T34	337325	1	0	0
T40	971778	0	0	0
T41	0	1	0	0
T51	72451	1	0	0
T52	134287	0	0	0
T53	263798	0	0	0
T54	152535	0	0	0
T72	75664	0	0	0
T78	0	1	0	0
T79	0	3	0	0
T85	27123	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T132	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741343977	341323970	0	0
T1	15852	2824	0	0
T2	128146	119091	0	0
T3	81118	3172	0	0
T4	283164	7957	0	0
T5	7657	7598	0	0
T6	396597	396587	0	0
T17	13714	5604	0	0
T18	2014	764	0	0
T19	17438	17381	0	0
T20	24761	606	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	565	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T40	0	1	0	0
T51	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	553	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T40	0	1	0	0
T51	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	539	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T40	0	1	0	0
T51	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	530	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	1	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	1	0	0
T34	0	4	0	0
T40	0	1	0	0
T51	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1216	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	7	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	2	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T75	0	1	0	0
T79	0	2	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	128009	0	0
T1	15852	38	0	0
T2	128146	0	0	0
T3	81118	1186	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	77	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T33	0	276	0	0
T34	0	159	0	0
T54	0	22	0	0
T75	0	120	0	0
T79	0	607	0	0
T83	0	2023	0	0
T86	0	423	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1136	0	0
T3	81118	7	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T21	22344	0	0	0
T32	54831	0	0	0
T33	0	2	0	0
T41	0	7	0	0
T59	0	1	0	0
T60	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T83	0	6	0	0
T87	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	62	0	0
T1	15852	1	0	0
T2	128146	0	0	0
T3	81118	0	0	0
T4	283164	0	0	0
T5	7657	0	0	0
T6	396597	0	0	0
T13	0	1	0	0
T17	13714	0	0	0
T18	2014	0	0	0
T19	17438	0	0	0
T20	24761	0	0	0
T34	0	1	0	0
T54	0	1	0	0
T60	0	1	0	0
T62	0	2	0	0
T79	0	1	0	0
T83	0	1	0	0
T86	0	1	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1567	0	0
T9	20935	177	0	0
T10	0	344	0	0
T11	0	333	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	356	0	0
T43	0	357	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	1297	0	0
T9	20935	147	0	0
T10	0	284	0	0
T11	0	273	0	0
T38	128160	0	0	0
T41	179099	0	0	0
T42	0	296	0	0
T43	0	297	0	0
T44	1957	0	0	0
T45	242525	0	0	0
T46	4595	0	0	0
T47	10723	0	0	0
T48	15221	0	0	0
T49	594542	0	0	0
T50	75657	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741519896	741332080	0	0
T1	15852	15778	0	0
T2	128146	128140	0	0
T3	81118	81059	0	0
T4	283164	283154	0	0
T5	7657	7599	0	0
T6	396597	396587	0	0
T17	13714	13641	0	0
T18	2014	1958	0	0
T19	17438	17382	0	0
T20	24761	24690	0	0