Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T55,T94
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14582	0	0
DisabledNoTrigBkwd_A	2147483647	932236	0	0
DisabledNoTrigFwd_A	2147483647	1609395646	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14582	0	0
T8	669061	0	0	0
T34	29327	0	0	0
T53	1023	302	0	0
T54	356880	0	0	0
T55	1618	776	0	0
T65	46517	0	0	0
T72	415051	0	0	0
T73	18861	0	0	0
T94	0	527	0	0
T98	378160	0	0	0
T104	104569	0	0	0
T186	692797	0	0	0
T188	0	278	0	0
T189	2191	1113	0	0
T190	3477	843	0	0
T191	0	499	0	0
T192	0	201	0	0
T193	0	1536	0	0
T194	0	627	0	0
T195	0	1473	0	0
T196	0	843	0	0
T197	0	1163	0	0
T198	0	640	0	0
T199	0	117	0	0
T200	0	1129	0	0
T201	0	855	0	0
T202	0	394	0	0
T203	0	233	0	0
T204	0	1033	0	0
T205	238988	0	0	0
T206	33516	0	0	0
T207	55319	0	0	0
T208	867808	0	0	0
T209	124387	0	0	0
T210	350994	0	0	0
T211	122424	0	0	0
T212	136397	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	932236	0	0
T1	93363	56	0	0
T2	3689776	415	0	0
T3	315740	18	0	0
T4	1874984	2531	0	0
T5	1197352	730	0	0
T6	481936	1790	0	0
T7	120112	0	0	0
T8	0	7	0	0
T10	0	7068	0	0
T15	2293839	1362	0	0
T16	0	7326	0	0
T17	0	1	0	0
T18	322944	0	0	0
T19	134976	0	0	0
T20	0	2	0	0
T22	2072556	3505	0	0
T40	0	13	0	0
T53	0	8	0	0
T54	0	228	0	0
T55	0	18	0	0
T56	0	91	0	0
T57	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1609395646	0	0
T1	373452	308717	0	0
T2	3689776	2464815	0	0
T3	315740	283881	0	0
T4	1874984	1405819	0	0
T5	1197352	622426	0	0
T6	481936	365926	0	0
T7	120112	2904	0	0
T18	322944	93320	0	0
T19	134976	73720	0	0
T22	2072556	2012593	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	766612282	1968	0	0
DisabledNoTrigBkwd_A	766612282	258853	0	0
DisabledNoTrigFwd_A	766612282	348560505	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1968	0	0
T65	46517	0	0	0
T98	378160	0	0	0
T186	692797	0	0	0
T189	2191	1113	0	0
T201	0	855	0	0
T205	238988	0	0	0
T206	33516	0	0	0
T207	55319	0	0	0
T208	867808	0	0	0
T209	124387	0	0	0
T210	350994	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	258853	0	0
T1	93363	56	0	0
T2	922444	406	0	0
T3	78935	18	0	0
T4	468746	8	0	0
T5	299338	0	0	0
T6	120484	1707	0	0
T7	30028	0	0	0
T15	0	471	0	0
T16	0	31	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T20	0	2	0	0
T22	518139	3143	0	0
T40	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	348560505	0	0
T1	93363	28913	0	0
T2	922444	296315	0	0
T3	78935	47304	0	0
T4	468746	466580	0	0
T5	299338	299330	0	0
T6	120484	6322	0	0
T7	30028	720	0	0
T18	80736	14507	0	0
T19	33744	1651	0	0
T22	518139	594051	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T2,T22,T18
1	1	Covered	T2,T22,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T190,T191
1	1	Covered	T2,T22,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	766612282	3861	0	0
DisabledNoTrigBkwd_A	766612282	244451	0	0
DisabledNoTrigFwd_A	766612282	410156053	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	3861	0	0
T8	669061	0	0	0
T34	29327	0	0	0
T53	1023	302	0	0
T54	356880	0	0	0
T72	415051	0	0	0
T73	18861	0	0	0
T104	104569	0	0	0
T190	3477	843	0	0
T191	0	499	0	0
T195	0	1473	0	0
T199	0	117	0	0
T202	0	394	0	0
T203	0	233	0	0
T211	122424	0	0	0
T212	136397	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	244451	0	0
T2	922444	5	0	0
T3	78935	0	0	0
T4	468746	2519	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	6	0	0
T10	0	3131	0	0
T15	764613	240	0	0
T16	0	4455	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	25	0	0
T40	0	3	0	0
T53	0	8	0	0
T54	0	228	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	410156053	0	0
T1	93363	93268	0	0
T2	922444	867996	0	0
T3	78935	78859	0	0
T4	468746	2967	0	0
T5	299338	298814	0	0
T6	120484	120474	0	0
T7	30028	724	0	0
T18	80736	6771	0	0
T19	33744	25610	0	0
T22	518139	484388	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T2,T22,T4
1	1	Covered	T2,T22,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T94,T188
1	1	Covered	T2,T22,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	766612282	4993	0	0
DisabledNoTrigBkwd_A	766612282	234020	0	0
DisabledNoTrigFwd_A	766612282	422274443	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	4993	0	0
T9	570693	0	0	0
T10	837963	0	0	0
T17	311747	0	0	0
T55	1618	776	0	0
T56	445552	0	0	0
T57	311664	0	0	0
T79	8852	0	0	0
T85	35826	0	0	0
T94	2777	527	0	0
T188	0	278	0	0
T193	0	1536	0	0
T196	0	843	0	0
T204	0	1033	0	0
T213	21456	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	234020	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	253	0	0
T6	120484	78	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	14	0	0
T15	764613	651	0	0
T16	0	2797	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	36	0	0
T55	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	422274443	0	0
T1	93363	93268	0	0
T2	922444	642308	0	0
T3	78935	78859	0	0
T4	468746	468183	0	0
T5	299338	10158	0	0
T6	120484	119424	0	0
T7	30028	728	0	0
T18	80736	69062	0	0
T19	33744	12774	0	0
T22	518139	501323	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T2,T22,T4
1	1	Covered	T2,T22,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T194,T197
1	1	Covered	T2,T22,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	766612282	3760	0	0
DisabledNoTrigBkwd_A	766612282	194912	0	0
DisabledNoTrigFwd_A	766612282	428404645	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	3760	0	0
T13	41569	0	0	0
T192	1032	201	0	0
T194	1347	627	0	0
T197	3505	1163	0	0
T198	0	640	0	0
T200	0	1129	0	0
T214	618034	0	0	0
T215	377806	0	0	0
T216	579402	0	0	0
T217	903736	0	0	0
T218	406941	0	0	0
T219	380387	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	194912	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	477	0	0
T6	120484	5	0	0
T7	30028	0	0	0
T10	0	3923	0	0
T15	764613	0	0	0
T16	0	43	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	301	0	0
T56	0	91	0	0
T57	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	428404645	0	0
T1	93363	93268	0	0
T2	922444	658196	0	0
T3	78935	78859	0	0
T4	468746	468089	0	0
T5	299338	14124	0	0
T6	120484	119706	0	0
T7	30028	732	0	0
T18	80736	2980	0	0
T19	33744	33685	0	0
T22	518139	432831	0	0