Module Definition
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Module : alert_handler_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.14 100.00 96.56 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_wrap.u_reg 99.14 100.00 96.56 100.00 100.00

Line Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
TOTAL22282228100.00
ALWAYS7244100.00
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CONT_ASSIGN1693211100.00
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CONT_ASSIGN1693811100.00
CONT_ASSIGN1693911100.00
CONT_ASSIGN1694011100.00
CONT_ASSIGN1694211100.00
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CONT_ASSIGN1694811100.00
CONT_ASSIGN1695011100.00
CONT_ASSIGN1695111100.00
CONT_ASSIGN1695211100.00
CONT_ASSIGN1695411100.00
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CONT_ASSIGN1696011100.00
CONT_ASSIGN1696211100.00
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CONT_ASSIGN1697011100.00
CONT_ASSIGN1697111100.00
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CONT_ASSIGN1698011100.00
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CONT_ASSIGN1699011100.00
CONT_ASSIGN1699111100.00
CONT_ASSIGN1699211100.00
CONT_ASSIGN1699411100.00
CONT_ASSIGN1699511100.00
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CONT_ASSIGN1699811100.00
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CONT_ASSIGN1700011100.00
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CONT_ASSIGN1701011100.00
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CONT_ASSIGN1702011100.00
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CONT_ASSIGN1702711100.00
CONT_ASSIGN1702811100.00
CONT_ASSIGN1703011100.00
CONT_ASSIGN1703111100.00
CONT_ASSIGN1703311100.00
CONT_ASSIGN1703411100.00
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CONT_ASSIGN1704011100.00
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CONT_ASSIGN1705111100.00
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CONT_ASSIGN1706011100.00
CONT_ASSIGN1706111100.00
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CONT_ASSIGN1706411100.00
CONT_ASSIGN1706611100.00
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CONT_ASSIGN1707011100.00
CONT_ASSIGN1707211100.00
CONT_ASSIGN1707311100.00
CONT_ASSIGN1707511100.00
CONT_ASSIGN1707611100.00
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CONT_ASSIGN1707911100.00
CONT_ASSIGN1708111100.00
CONT_ASSIGN1708211100.00
CONT_ASSIGN1708411100.00
CONT_ASSIGN1708511100.00
CONT_ASSIGN1708711100.00
CONT_ASSIGN1708811100.00
CONT_ASSIGN1709011100.00
CONT_ASSIGN1709111100.00
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CONT_ASSIGN1711111100.00
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CONT_ASSIGN1712011100.00
CONT_ASSIGN1712111100.00
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CONT_ASSIGN1712711100.00
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CONT_ASSIGN1713011100.00
CONT_ASSIGN1713211100.00
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CONT_ASSIGN1713811100.00
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CONT_ASSIGN1714111100.00
CONT_ASSIGN1714211100.00
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CONT_ASSIGN1715011100.00
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CONT_ASSIGN1716011100.00
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CONT_ASSIGN1717411100.00
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CONT_ASSIGN1717811100.00
CONT_ASSIGN1718011100.00
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CONT_ASSIGN1718911100.00
CONT_ASSIGN1719011100.00
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CONT_ASSIGN1721011100.00
CONT_ASSIGN1721111100.00
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CONT_ASSIGN1721911100.00
CONT_ASSIGN1722011100.00
CONT_ASSIGN1722211100.00
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CONT_ASSIGN1724011100.00
CONT_ASSIGN1724111100.00
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CONT_ASSIGN1725111100.00
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CONT_ASSIGN1732011100.00
CONT_ASSIGN1732111100.00
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CONT_ASSIGN1733211100.00
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CONT_ASSIGN1734011100.00
CONT_ASSIGN1734211100.00
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CONT_ASSIGN1735111100.00
CONT_ASSIGN1735211100.00
CONT_ASSIGN1735311100.00
CONT_ASSIGN1735511100.00
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CONT_ASSIGN1736011100.00
CONT_ASSIGN1736111100.00
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CONT_ASSIGN1736411100.00
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CONT_ASSIGN1737011100.00
CONT_ASSIGN1737211100.00
CONT_ASSIGN1737311100.00
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CONT_ASSIGN1738011100.00
CONT_ASSIGN1738111100.00
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CONT_ASSIGN1739011100.00
CONT_ASSIGN1739111100.00
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CONT_ASSIGN1739511100.00
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CONT_ASSIGN1740711100.00
CONT_ASSIGN1740911100.00
CONT_ASSIGN1741111100.00
CONT_ASSIGN1741211100.00
CONT_ASSIGN1741411100.00
CONT_ASSIGN1741511100.00
CONT_ASSIGN1741611100.00
CONT_ASSIGN1741811100.00
CONT_ASSIGN1741911100.00
CONT_ASSIGN1742011100.00
CONT_ASSIGN1742111100.00
CONT_ASSIGN1742311100.00
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CONT_ASSIGN1743111100.00
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CONT_ASSIGN1743511100.00
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CONT_ASSIGN1743711100.00
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CONT_ASSIGN1744011100.00
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CONT_ASSIGN1745011100.00
CONT_ASSIGN1745211100.00
CONT_ASSIGN1745311100.00
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CONT_ASSIGN1745811100.00
CONT_ASSIGN1746011100.00
CONT_ASSIGN1746211100.00
CONT_ASSIGN1746411100.00
CONT_ASSIGN1746611100.00
CONT_ASSIGN1746811100.00
CONT_ASSIGN1747011100.00
CONT_ASSIGN1747211100.00
CONT_ASSIGN1747411100.00
CONT_ASSIGN1747511100.00
CONT_ASSIGN1747711100.00
CONT_ASSIGN1747811100.00
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CONT_ASSIGN1748111100.00
CONT_ASSIGN1748211100.00
CONT_ASSIGN1748311100.00
CONT_ASSIGN1748411100.00
CONT_ASSIGN1748611100.00
CONT_ASSIGN1748711100.00
CONT_ASSIGN1748811100.00
CONT_ASSIGN1749011100.00
CONT_ASSIGN1749111100.00
CONT_ASSIGN1749211100.00
CONT_ASSIGN1749411100.00
CONT_ASSIGN1749511100.00
CONT_ASSIGN1749611100.00
CONT_ASSIGN1749811100.00
CONT_ASSIGN1749911100.00
CONT_ASSIGN1750011100.00
CONT_ASSIGN1750211100.00
CONT_ASSIGN1750311100.00
CONT_ASSIGN1750411100.00
CONT_ASSIGN1750611100.00
CONT_ASSIGN1750711100.00
CONT_ASSIGN1750811100.00
CONT_ASSIGN1751011100.00
CONT_ASSIGN1751111100.00
CONT_ASSIGN1751211100.00
CONT_ASSIGN1751311100.00
CONT_ASSIGN1751511100.00
CONT_ASSIGN1751611100.00
CONT_ASSIGN1751711100.00
CONT_ASSIGN1751911100.00
CONT_ASSIGN1752111100.00
CONT_ASSIGN1752311100.00
CONT_ASSIGN1752511100.00
CONT_ASSIGN1752711100.00
CONT_ASSIGN1752911100.00
CONT_ASSIGN1753111100.00
CONT_ASSIGN1753311100.00
CONT_ASSIGN1753511100.00
CONT_ASSIGN1753711100.00
CONT_ASSIGN1753811100.00
CONT_ASSIGN1754011100.00
CONT_ASSIGN1754111100.00
CONT_ASSIGN1754211100.00
CONT_ASSIGN1754411100.00
CONT_ASSIGN1754511100.00
CONT_ASSIGN1754611100.00
CONT_ASSIGN1754711100.00
CONT_ASSIGN1754911100.00
CONT_ASSIGN1755011100.00
CONT_ASSIGN1755111100.00
CONT_ASSIGN1755311100.00
CONT_ASSIGN1755411100.00
CONT_ASSIGN1755511100.00
CONT_ASSIGN1755711100.00
CONT_ASSIGN1755811100.00
CONT_ASSIGN1755911100.00
CONT_ASSIGN1756111100.00
CONT_ASSIGN1756211100.00
CONT_ASSIGN1756311100.00
CONT_ASSIGN1756511100.00
CONT_ASSIGN1756611100.00
CONT_ASSIGN1756711100.00
CONT_ASSIGN1756911100.00
CONT_ASSIGN1757011100.00
CONT_ASSIGN1757111100.00
CONT_ASSIGN1757311100.00
CONT_ASSIGN1757411100.00
CONT_ASSIGN1757511100.00
ALWAYS17579351351100.00
ALWAYS17934397397100.00
ALWAYS1939233100.00
ALWAYS1940033100.00
CONT_ASSIGN1940811100.00
CONT_ASSIGN1941111100.00
CONT_ASSIGN1963111100.00
CONT_ASSIGN1985311100.00
CONT_ASSIGN1986111100.00
CONT_ASSIGN1986211100.00

Click here to see the source line report.

Cond Coverage for Module : alert_handler_reg_top
TotalCoveredPercent
Conditions4800463596.56
Logical4800463596.56
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
62-9201100.00
9242-15665100.00
15666-15837100.00
15838-15924100.00
15924100.00
15924100.00
15924-1637399.49
16376-1662894.29
16631-1684489.35
16847-1707391.12
17076-1736295.87
17365-1940888.38

Branch Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
Branches 360 360 100.00
TERNARY 15920 2 2 100.00
IF 72 3 3 100.00
CASE 17935 351 351 100.00
IF 19392 2 2 100.00
IF 19400 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 15920 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T14,T23,T24
0 Covered T14,T23,T24


LineNo. Expression -1-: 72 if ((!rst_ni)) -2-: 74 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T14,T23,T24
0 1 Covered T28,T125,T153
0 0 Covered T14,T23,T24


LineNo. Expression -1-: 17935 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T14,T23,T24
addr_hit[1] Covered T14,T23,T24
addr_hit[2] Covered T14,T23,T24
addr_hit[3] Covered T14,T23,T26
addr_hit[4] Covered T14,T23,T26
addr_hit[5] Covered T14,T23,T26
addr_hit[6] Covered T14,T23,T26
addr_hit[7] Covered T14,T23,T26
addr_hit[8] Covered T14,T23,T26
addr_hit[9] Covered T14,T23,T26
addr_hit[10] Covered T14,T23,T26
addr_hit[11] Covered T14,T23,T24
addr_hit[12] Covered T14,T23,T26
addr_hit[13] Covered T14,T23,T26
addr_hit[14] Covered T14,T23,T26
addr_hit[15] Covered T14,T23,T26
addr_hit[16] Covered T14,T23,T26
addr_hit[17] Covered T14,T23,T25
addr_hit[18] Covered T14,T23,T26
addr_hit[19] Covered T14,T23,T26
addr_hit[20] Covered T14,T23,T26
addr_hit[21] Covered T14,T23,T26
addr_hit[22] Covered T14,T23,T26
addr_hit[23] Covered T14,T23,T26
addr_hit[24] Covered T14,T23,T26
addr_hit[25] Covered T14,T23,T26
addr_hit[26] Covered T14,T23,T26
addr_hit[27] Covered T14,T23,T26
addr_hit[28] Covered T14,T23,T26
addr_hit[29] Covered T14,T23,T26
addr_hit[30] Covered T14,T23,T26
addr_hit[31] Covered T14,T23,T26
addr_hit[32] Covered T14,T23,T26
addr_hit[33] Covered T14,T23,T25
addr_hit[34] Covered T14,T23,T26
addr_hit[35] Covered T14,T23,T24
addr_hit[36] Covered T14,T23,T26
addr_hit[37] Covered T14,T23,T26
addr_hit[38] Covered T14,T23,T26
addr_hit[39] Covered T14,T23,T25
addr_hit[40] Covered T14,T23,T24
addr_hit[41] Covered T14,T23,T26
addr_hit[42] Covered T14,T23,T26
addr_hit[43] Covered T14,T23,T26
addr_hit[44] Covered T14,T23,T26
addr_hit[45] Covered T14,T23,T26
addr_hit[46] Covered T14,T23,T26
addr_hit[47] Covered T14,T23,T26
addr_hit[48] Covered T14,T23,T26
addr_hit[49] Covered T14,T23,T26
addr_hit[50] Covered T14,T23,T26
addr_hit[51] Covered T14,T23,T26
addr_hit[52] Covered T14,T23,T26
addr_hit[53] Covered T14,T23,T26
addr_hit[54] Covered T14,T23,T26
addr_hit[55] Covered T14,T23,T25
addr_hit[56] Covered T14,T23,T26
addr_hit[57] Covered T14,T23,T26
addr_hit[58] Covered T14,T23,T26
addr_hit[59] Covered T14,T23,T26
addr_hit[60] Covered T14,T23,T26
addr_hit[61] Covered T14,T23,T26
addr_hit[62] Covered T14,T23,T26
addr_hit[63] Covered T14,T23,T26
addr_hit[64] Covered T14,T23,T26
addr_hit[65] Covered T14,T23,T26
addr_hit[66] Covered T14,T23,T26
addr_hit[67] Covered T14,T23,T26
addr_hit[68] Covered T14,T23,T26
addr_hit[69] Covered T14,T23,T26
addr_hit[70] Covered T14,T23,T26
addr_hit[71] Covered T14,T23,T26
addr_hit[72] Covered T14,T23,T26
addr_hit[73] Covered T14,T23,T26
addr_hit[74] Covered T14,T23,T26
addr_hit[75] Covered T14,T23,T26
addr_hit[76] Covered T14,T23,T26
addr_hit[77] Covered T14,T23,T26
addr_hit[78] Covered T14,T23,T26
addr_hit[79] Covered T14,T23,T26
addr_hit[80] Covered T14,T23,T26
addr_hit[81] Covered T14,T23,T26
addr_hit[82] Covered T14,T23,T26
addr_hit[83] Covered T14,T23,T26
addr_hit[84] Covered T14,T23,T26
addr_hit[85] Covered T14,T23,T26
addr_hit[86] Covered T14,T23,T26
addr_hit[87] Covered T14,T23,T26
addr_hit[88] Covered T14,T23,T26
addr_hit[89] Covered T14,T23,T26
addr_hit[90] Covered T14,T23,T26
addr_hit[91] Covered T14,T23,T26
addr_hit[92] Covered T14,T23,T26
addr_hit[93] Covered T14,T23,T26
addr_hit[94] Covered T14,T23,T26
addr_hit[95] Covered T14,T23,T25
addr_hit[96] Covered T14,T23,T26
addr_hit[97] Covered T14,T23,T26
addr_hit[98] Covered T14,T23,T26
addr_hit[99] Covered T14,T23,T25
addr_hit[100] Covered T14,T23,T26
addr_hit[101] Covered T14,T23,T25
addr_hit[102] Covered T14,T23,T26
addr_hit[103] Covered T14,T23,T26
addr_hit[104] Covered T14,T23,T26
addr_hit[105] Covered T14,T23,T26
addr_hit[106] Covered T14,T23,T26
addr_hit[107] Covered T14,T23,T26
addr_hit[108] Covered T14,T23,T26
addr_hit[109] Covered T14,T23,T26
addr_hit[110] Covered T14,T23,T26
addr_hit[111] Covered T14,T23,T26
addr_hit[112] Covered T14,T23,T26
addr_hit[113] Covered T14,T23,T26
addr_hit[114] Covered T14,T23,T26
addr_hit[115] Covered T14,T23,T26
addr_hit[116] Covered T14,T23,T26
addr_hit[117] Covered T14,T23,T26
addr_hit[118] Covered T14,T23,T26
addr_hit[119] Covered T14,T23,T26
addr_hit[120] Covered T14,T23,T26
addr_hit[121] Covered T14,T23,T25
addr_hit[122] Covered T14,T23,T26
addr_hit[123] Covered T14,T23,T26
addr_hit[124] Covered T14,T23,T26
addr_hit[125] Covered T14,T23,T26
addr_hit[126] Covered T14,T23,T26
addr_hit[127] Covered T14,T23,T26
addr_hit[128] Covered T14,T23,T26
addr_hit[129] Covered T14,T23,T26
addr_hit[130] Covered T14,T23,T26
addr_hit[131] Covered T14,T23,T26
addr_hit[132] Covered T14,T23,T26
addr_hit[133] Covered T14,T23,T26
addr_hit[134] Covered T14,T23,T26
addr_hit[135] Covered T14,T23,T26
addr_hit[136] Covered T14,T23,T26
addr_hit[137] Covered T14,T23,T26
addr_hit[138] Covered T14,T23,T26
addr_hit[139] Covered T14,T23,T26
addr_hit[140] Covered T14,T23,T26
addr_hit[141] Covered T14,T23,T26
addr_hit[142] Covered T14,T23,T26
addr_hit[143] Covered T14,T23,T26
addr_hit[144] Covered T14,T23,T26
addr_hit[145] Covered T14,T23,T26
addr_hit[146] Covered T14,T23,T25
addr_hit[147] Covered T14,T23,T25
addr_hit[148] Covered T14,T23,T26
addr_hit[149] Covered T14,T23,T26
addr_hit[150] Covered T14,T23,T26
addr_hit[151] Covered T14,T23,T26
addr_hit[152] Covered T14,T23,T26
addr_hit[153] Covered T14,T23,T26
addr_hit[154] Covered T14,T23,T26
addr_hit[155] Covered T14,T23,T26
addr_hit[156] Covered T14,T23,T26
addr_hit[157] Covered T14,T23,T24
addr_hit[158] Covered T14,T23,T26
addr_hit[159] Covered T14,T23,T26
addr_hit[160] Covered T14,T23,T26
addr_hit[161] Covered T14,T23,T26
addr_hit[162] Covered T14,T23,T25
addr_hit[163] Covered T14,T23,T26
addr_hit[164] Covered T14,T23,T26
addr_hit[165] Covered T14,T23,T26
addr_hit[166] Covered T14,T23,T26
addr_hit[167] Covered T14,T23,T26
addr_hit[168] Covered T14,T23,T26
addr_hit[169] Covered T14,T23,T24
addr_hit[170] Covered T14,T23,T26
addr_hit[171] Covered T14,T23,T24
addr_hit[172] Covered T14,T23,T26
addr_hit[173] Covered T14,T23,T26
addr_hit[174] Covered T14,T23,T26
addr_hit[175] Covered T14,T23,T26
addr_hit[176] Covered T14,T23,T26
addr_hit[177] Covered T14,T23,T26
addr_hit[178] Covered T14,T23,T26
addr_hit[179] Covered T14,T23,T26
addr_hit[180] Covered T14,T23,T25
addr_hit[181] Covered T14,T23,T26
addr_hit[182] Covered T14,T23,T26
addr_hit[183] Covered T14,T23,T26
addr_hit[184] Covered T14,T23,T26
addr_hit[185] Covered T14,T23,T26
addr_hit[186] Covered T14,T23,T26
addr_hit[187] Covered T14,T23,T26
addr_hit[188] Covered T14,T23,T26
addr_hit[189] Covered T14,T23,T25
addr_hit[190] Covered T14,T23,T26
addr_hit[191] Covered T14,T23,T26
addr_hit[192] Covered T14,T23,T26
addr_hit[193] Covered T14,T23,T24
addr_hit[194] Covered T14,T23,T26
addr_hit[195] Covered T14,T23,T26
addr_hit[196] Covered T14,T23,T26
addr_hit[197] Covered T14,T23,T26
addr_hit[198] Covered T14,T23,T26
addr_hit[199] Covered T14,T23,T26
addr_hit[200] Covered T14,T23,T24
addr_hit[201] Covered T14,T23,T26
addr_hit[202] Covered T14,T23,T26
addr_hit[203] Covered T14,T23,T26
addr_hit[204] Covered T14,T23,T26
addr_hit[205] Covered T14,T23,T25
addr_hit[206] Covered T14,T23,T26
addr_hit[207] Covered T14,T23,T25
addr_hit[208] Covered T14,T23,T24
addr_hit[209] Covered T14,T23,T26
addr_hit[210] Covered T14,T23,T26
addr_hit[211] Covered T14,T23,T26
addr_hit[212] Covered T14,T23,T26
addr_hit[213] Covered T14,T23,T26
addr_hit[214] Covered T14,T23,T26
addr_hit[215] Covered T14,T23,T26
addr_hit[216] Covered T14,T23,T25
addr_hit[217] Covered T14,T23,T26
addr_hit[218] Covered T14,T23,T26
addr_hit[219] Covered T14,T23,T26
addr_hit[220] Covered T14,T23,T26
addr_hit[221] Covered T14,T23,T25
addr_hit[222] Covered T14,T23,T26
addr_hit[223] Covered T14,T23,T26
addr_hit[224] Covered T14,T23,T26
addr_hit[225] Covered T14,T23,T26
addr_hit[226] Covered T14,T23,T26
addr_hit[227] Covered T14,T23,T26
addr_hit[228] Covered T14,T23,T26
addr_hit[229] Covered T14,T23,T26
addr_hit[230] Covered T14,T23,T26
addr_hit[231] Covered T14,T23,T26
addr_hit[232] Covered T14,T23,T26
addr_hit[233] Covered T14,T23,T26
addr_hit[234] Covered T14,T23,T26
addr_hit[235] Covered T14,T23,T26
addr_hit[236] Covered T14,T23,T26
addr_hit[237] Covered T14,T23,T26
addr_hit[238] Covered T14,T23,T26
addr_hit[239] Covered T14,T23,T26
addr_hit[240] Covered T14,T23,T26
addr_hit[241] Covered T14,T23,T26
addr_hit[242] Covered T14,T23,T25
addr_hit[243] Covered T14,T23,T26
addr_hit[244] Covered T14,T23,T26
addr_hit[245] Covered T14,T23,T26
addr_hit[246] Covered T14,T23,T26
addr_hit[247] Covered T14,T23,T26
addr_hit[248] Covered T14,T23,T26
addr_hit[249] Covered T14,T23,T26
addr_hit[250] Covered T14,T23,T25
addr_hit[251] Covered T14,T23,T25
addr_hit[252] Covered T14,T23,T26
addr_hit[253] Covered T14,T23,T24
addr_hit[254] Covered T14,T23,T26
addr_hit[255] Covered T14,T23,T26
addr_hit[256] Covered T14,T23,T26
addr_hit[257] Covered T14,T23,T26
addr_hit[258] Covered T14,T23,T26
addr_hit[259] Covered T14,T23,T26
addr_hit[260] Covered T14,T23,T24
addr_hit[261] Covered T14,T23,T26
addr_hit[262] Covered T14,T23,T26
addr_hit[263] Covered T14,T23,T26
addr_hit[264] Covered T14,T23,T26
addr_hit[265] Covered T14,T23,T26
addr_hit[266] Covered T14,T23,T26
addr_hit[267] Covered T14,T23,T26
addr_hit[268] Covered T14,T23,T26
addr_hit[269] Covered T14,T23,T26
addr_hit[270] Covered T14,T23,T26
addr_hit[271] Covered T14,T23,T26
addr_hit[272] Covered T14,T23,T26
addr_hit[273] Covered T14,T23,T25
addr_hit[274] Covered T14,T23,T26
addr_hit[275] Covered T14,T23,T26
addr_hit[276] Covered T14,T23,T26
addr_hit[277] Covered T14,T23,T26
addr_hit[278] Covered T14,T23,T26
addr_hit[279] Covered T14,T23,T26
addr_hit[280] Covered T14,T23,T26
addr_hit[281] Covered T14,T23,T26
addr_hit[282] Covered T14,T23,T26
addr_hit[283] Covered T14,T23,T26
addr_hit[284] Covered T14,T23,T26
addr_hit[285] Covered T14,T23,T26
addr_hit[286] Covered T14,T23,T26
addr_hit[287] Covered T14,T23,T26
addr_hit[288] Covered T14,T23,T26
addr_hit[289] Covered T14,T23,T26
addr_hit[290] Covered T14,T23,T26
addr_hit[291] Covered T14,T23,T24
addr_hit[292] Covered T14,T23,T26
addr_hit[293] Covered T14,T23,T26
addr_hit[294] Covered T14,T23,T26
addr_hit[295] Covered T14,T23,T26
addr_hit[296] Covered T14,T23,T26
addr_hit[297] Covered T14,T23,T26
addr_hit[298] Covered T14,T23,T26
addr_hit[299] Covered T14,T23,T26
addr_hit[300] Covered T14,T23,T26
addr_hit[301] Covered T14,T23,T26
addr_hit[302] Covered T14,T23,T24
addr_hit[303] Covered T14,T23,T26
addr_hit[304] Covered T14,T23,T26
addr_hit[305] Covered T14,T23,T26
addr_hit[306] Covered T14,T23,T26
addr_hit[307] Covered T14,T23,T26
addr_hit[308] Covered T14,T23,T26
addr_hit[309] Covered T14,T23,T26
addr_hit[310] Covered T14,T23,T26
addr_hit[311] Covered T14,T23,T26
addr_hit[312] Covered T14,T23,T26
addr_hit[313] Covered T14,T23,T25
addr_hit[314] Covered T14,T23,T24
addr_hit[315] Covered T14,T23,T26
addr_hit[316] Covered T14,T23,T26
addr_hit[317] Covered T14,T23,T26
addr_hit[318] Covered T14,T23,T26
addr_hit[319] Covered T14,T23,T26
addr_hit[320] Covered T14,T23,T26
addr_hit[321] Covered T14,T23,T26
addr_hit[322] Covered T14,T23,T26
addr_hit[323] Covered T14,T23,T26
addr_hit[324] Covered T14,T23,T26
addr_hit[325] Covered T14,T23,T25
addr_hit[326] Covered T14,T23,T25
addr_hit[327] Covered T14,T23,T26
addr_hit[328] Covered T14,T23,T26
addr_hit[329] Covered T14,T23,T26
addr_hit[330] Covered T14,T23,T24
addr_hit[331] Covered T14,T23,T26
addr_hit[332] Covered T14,T23,T26
addr_hit[333] Covered T14,T23,T26
addr_hit[334] Covered T14,T23,T26
addr_hit[335] Covered T14,T23,T26
addr_hit[336] Covered T14,T23,T26
addr_hit[337] Covered T14,T23,T24
addr_hit[338] Covered T14,T23,T25
addr_hit[339] Covered T14,T23,T26
addr_hit[340] Covered T14,T23,T26
addr_hit[341] Covered T14,T23,T26
addr_hit[342] Covered T14,T23,T26
addr_hit[343] Covered T14,T23,T26
addr_hit[344] Covered T14,T23,T26
addr_hit[345] Covered T14,T23,T26
addr_hit[346] Covered T14,T23,T26
addr_hit[347] Covered T14,T23,T26
addr_hit[348] Covered T14,T23,T26
addr_hit[349] Covered T14,T23,T26
default Covered T14,T23,T24


LineNo. Expression -1-: 19392 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T14,T23,T24
0 Covered T14,T23,T24


LineNo. Expression -1-: 19400 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T14,T23,T24
0 Covered T14,T23,T24


Assert Coverage for Module : alert_handler_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 787095701 95720909 0 0
reAfterRv 787095701 95720865 0 0
rePulse 787095701 14090289 0 0
wePulse 787095701 81630576 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 787095701 95720909 0 0
T14 6628 751 0 0
T23 630353 99292 0 0
T24 186 22 0 0
T25 519 40 0 0
T26 9095 489 0 0
T27 984 22 0 0
T28 5674 150 0 0
T29 3699 185 0 0
T30 876 40 0 0
T31 4968 682 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 787095701 95720865 0 0
T14 6628 751 0 0
T23 630353 99292 0 0
T24 186 22 0 0
T25 519 40 0 0
T26 9095 489 0 0
T27 984 22 0 0
T28 5674 150 0 0
T29 3699 185 0 0
T30 876 40 0 0
T31 4968 682 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 787095701 14090289 0 0
T14 6628 350 0 0
T23 630353 58703 0 0
T24 186 11 0 0
T25 519 20 0 0
T26 9095 4 0 0
T27 984 11 0 0
T28 5674 26 0 0
T29 3699 3 0 0
T30 876 20 0 0
T31 4968 282 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 787095701 81630576 0 0
T14 6628 401 0 0
T23 630353 40589 0 0
T24 186 11 0 0
T25 519 20 0 0
T26 9095 485 0 0
T27 984 11 0 0
T28 5674 124 0 0
T29 3699 182 0 0
T30 876 20 0 0
T31 4968 400 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%