Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T32
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T22,T4
1	1	0	Covered	T2,T3,T22
1	1	1	Covered	T2,T22,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T18
0	1	Covered	T18,T10,T33
1	0	Covered	T2,T16,T34

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T22,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T34

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Covered	T10,T35,T36
1	1	Covered	T18,T10,T33

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T22

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T22,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T38,T39
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T16,T40
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T22,T16
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T10,T41
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1166	0	0
CheckAccumTrig0_A	2147483647	2730	0	0
CheckAccumTrig1_A	2147483647	137	0	0
CheckClr_A	2147483647	1311	0	0
CheckEn_A	2147483647	1256427415	0	0
CheckPhase0_A	2147483647	3068	0	0
CheckPhase1_A	2147483647	3006	0	0
CheckPhase2_A	2147483647	2944	0	0
CheckPhase3_A	2147483647	2876	0	0
CheckTimeout0_A	2147483647	4599	0	0
CheckTimeoutSt1_A	2147483647	476877	0	0
CheckTimeoutSt2_A	2147483647	4210	0	0
CheckTimeoutStTrig_A	2147483647	251	0	0
ErrorStAllEscAsserted_A	2147483647	6507	0	0
ErrorStIsTerminal_A	2147483647	5427	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1166	0	0
T11	185440	240	0	0
T12	0	181	0	0
T13	0	256	0	0
T42	0	274	0	0
T43	0	215	0	0
T44	116832	0	0	0
T45	112364	0	0	0
T46	45228	0	0	0
T47	37336	0	0	0
T48	299924	0	0	0
T49	188508	0	0	0
T50	1675676	0	0	0
T51	1313956	0	0	0
T52	515036	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2730	0	0
T1	93363	2	0	0
T2	3689776	12	0	0
T3	315740	4	0	0
T4	1874984	6	0	0
T5	1197352	2	0	0
T6	481936	3	0	0
T7	120112	0	0	0
T8	0	2	0	0
T10	0	17	0	0
T15	2293839	3	0	0
T16	0	13	0	0
T17	0	1	0	0
T18	322944	0	0	0
T19	134976	0	0	0
T20	0	1	0	0
T22	2072556	10	0	0
T40	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	137	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T8	669061	0	0	0
T10	837963	3	0	0
T16	445378	2	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T22	518139	0	0	0
T34	58654	1	0	0
T37	129723	1	0	0
T40	11831	0	0	0
T52	0	1	0	0
T53	1023	0	0	0
T54	713760	0	0	0
T58	598156	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	37722	0	0	0
T74	84291	0	0	0
T75	7232	0	0	0
T76	116694	0	0	0
T77	12386	0	0	0
T78	31860	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T1	93363	1	0	0
T2	2767332	9	0	0
T3	236805	4	0	0
T4	1406238	2	0	0
T5	898014	0	0	0
T6	361452	0	0	0
T7	90084	0	0	0
T8	669061	1	0	0
T10	837963	26	0	0
T15	1529226	0	0	0
T16	445378	6	0	0
T18	242208	0	0	0
T19	101232	0	0	0
T20	27643	1	0	0
T21	13919	0	0	0
T22	1554417	1	0	0
T34	29327	0	0	0
T37	0	7	0	0
T40	11831	1	0	0
T41	0	3	0	0
T53	1023	0	0	0
T54	356880	0	0	0
T58	0	12	0	0
T73	18861	0	0	0
T76	0	7	0	0
T77	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256427415	0	0
T1	373452	286510	0	0
T2	3689776	2208580	0	0
T3	315740	283877	0	0
T4	1874984	34281	0	0
T5	1197352	622426	0	0
T6	481936	124815	0	0
T7	120112	2900	0	0
T18	322944	93319	0	0
T19	134976	73718	0	0
T22	2072556	2007064	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3068	0	0
T1	93363	2	0	0
T2	3689776	13	0	0
T3	315740	4	0	0
T4	1874984	6	0	0
T5	1197352	2	0	0
T6	481936	3	0	0
T7	120112	0	0	0
T8	0	2	0	0
T10	0	18	0	0
T15	2293839	3	0	0
T16	0	16	0	0
T17	0	1	0	0
T18	322944	1	0	0
T19	134976	0	0	0
T20	0	1	0	0
T22	2072556	10	0	0
T40	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3006	0	0
T1	93363	2	0	0
T2	3689776	13	0	0
T3	315740	4	0	0
T4	1874984	5	0	0
T5	1197352	2	0	0
T6	481936	3	0	0
T7	120112	0	0	0
T8	0	2	0	0
T10	0	23	0	0
T15	2293839	3	0	0
T16	0	15	0	0
T17	0	1	0	0
T18	322944	1	0	0
T19	134976	0	0	0
T20	0	1	0	0
T22	2072556	10	0	0
T40	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2944	0	0
T1	93363	2	0	0
T2	3689776	13	0	0
T3	315740	3	0	0
T4	1874984	5	0	0
T5	1197352	2	0	0
T6	481936	3	0	0
T7	120112	0	0	0
T8	0	3	0	0
T10	0	22	0	0
T15	2293839	3	0	0
T16	0	13	0	0
T17	0	1	0	0
T18	322944	1	0	0
T19	134976	0	0	0
T22	2072556	9	0	0
T40	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2876	0	0
T1	93363	2	0	0
T2	3689776	13	0	0
T3	315740	3	0	0
T4	1874984	5	0	0
T5	1197352	2	0	0
T6	481936	3	0	0
T7	120112	0	0	0
T8	0	3	0	0
T10	0	22	0	0
T15	2293839	3	0	0
T16	0	11	0	0
T17	0	1	0	0
T18	322944	1	0	0
T19	134976	0	0	0
T22	2072556	9	0	0
T40	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4599	0	0
T2	2767332	4	0	0
T3	236805	0	0	0
T4	1874984	0	0	0
T5	1197352	0	0	0
T6	481936	1	0	0
T7	120112	0	0	0
T10	0	40	0	0
T15	3058452	0	0	0
T16	445378	5	0	0
T18	322944	21	0	0
T19	134976	18	0	0
T20	27643	0	0	0
T22	2072556	28	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	5	0	0
T58	0	48	0	0
T75	0	4	0	0
T76	0	12	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	476877	0	0
T2	2767332	699	0	0
T3	236805	0	0	0
T4	1874984	0	0	0
T5	1197352	0	0	0
T6	481936	114	0	0
T7	120112	0	0	0
T10	0	11216	0	0
T15	3058452	0	0	0
T16	445378	217	0	0
T18	322944	4641	0	0
T19	134976	1043	0	0
T20	27643	0	0	0
T22	2072556	4518	0	0
T33	0	569	0	0
T34	0	60	0	0
T37	0	565	0	0
T40	0	159	0	0
T41	0	290	0	0
T58	0	5464	0	0
T75	0	291	0	0
T76	0	1066	0	0
T85	0	83	0	0
T86	0	145	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4210	0	0
T2	1844888	3	0	0
T3	157870	0	0	0
T4	1874984	0	0	0
T5	1197352	0	0	0
T6	481936	1	0	0
T7	120112	0	0	0
T10	0	28	0	0
T15	3058452	0	0	0
T16	890756	2	0	0
T18	322944	20	0	0
T19	134976	18	0	0
T20	55286	0	0	0
T22	2072556	28	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T58	0	37	0	0
T59	0	1	0	0
T60	0	2	0	0
T75	0	5	0	0
T76	0	10	0	0
T77	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	251	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	2513889	6	0	0
T15	764613	0	0	0
T16	445378	0	0	0
T17	935241	0	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T33	218433	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	11831	0	0	0
T41	833640	2	0	0
T56	1336656	0	0	0
T57	934992	0	0	0
T58	0	10	0	0
T59	0	5	0	0
T60	0	7	0	0
T76	0	3	0	0
T77	0	2	0	0
T78	0	2	0	0
T80	1046646	0	0	0
T84	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	8331	0	0	0
T95	294483	0	0	0
T96	1001616	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6507	0	0
T11	185440	1429	0	0
T12	0	725	0	0
T13	0	1461	0	0
T42	0	1480	0	0
T43	0	1412	0	0
T44	116832	0	0	0
T45	112364	0	0	0
T46	45228	0	0	0
T47	37336	0	0	0
T48	299924	0	0	0
T49	188508	0	0	0
T50	1675676	0	0	0
T51	1313956	0	0	0
T52	515036	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5427	0	0
T11	185440	1189	0	0
T12	0	605	0	0
T13	0	1221	0	0
T42	0	1240	0	0
T43	0	1172	0	0
T44	116832	0	0	0
T45	112364	0	0	0
T46	45228	0	0	0
T47	37336	0	0	0
T48	299924	0	0	0
T49	188508	0	0	0
T50	1675676	0	0	0
T51	1313956	0	0	0
T52	515036	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	373452	373072	0	0
T2	3689776	3689280	0	0
T3	315740	315436	0	0
T4	1874984	1874964	0	0
T5	1197352	1197320	0	0
T6	481936	481896	0	0
T7	120112	119596	0	0
T18	322944	322568	0	0
T19	134976	134740	0	0
T22	2072556	2072364	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T22,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T22,T18
1	0	1	Covered	T2,T22,T5
1	1	0	Covered	T22,T18,T19
1	1	1	Covered	T2,T22,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T18
0	1	Covered	T10,T58,T77
1	0	Covered	T2,T10,T97

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T97

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Not Covered
1	1	Covered	T10,T58,T77

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T22,T15,T16

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T2,T10,T80

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T15
1	Covered	T2,T4,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T8,T10,T56

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T22,T5,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T58
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T98,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T41,T37,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T37,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T99,T67,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T22,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T80
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T22,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	766612282	262	0	0
CheckAccumTrig0_A	766612282	569	0	0
CheckAccumTrig1_A	766612282	30	0	0
CheckClr_A	766612282	247	0	0
CheckEn_A	766355426	324455361	0	0
CheckPhase0_A	766612282	645	0	0
CheckPhase1_A	766612282	635	0	0
CheckPhase2_A	766612282	625	0	0
CheckPhase3_A	766612282	614	0	0
CheckTimeout0_A	766612282	882	0	0
CheckTimeoutSt1_A	766612282	114575	0	0
CheckTimeoutSt2_A	766612282	796	0	0
CheckTimeoutStTrig_A	766612282	55	0	0
ErrorStAllEscAsserted_A	766612282	1615	0	0
ErrorStIsTerminal_A	766612282	1345	0	0
u_state_regs_A	766612282	766423669	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	262	0	0
T11	46360	50	0	0
T12	0	45	0	0
T13	0	55	0	0
T42	0	60	0	0
T43	0	52	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	569	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	4	0	0
T15	764613	1	0	0
T16	0	5	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	30	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	2	0	0
T15	764613	0	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	0	0	0
T67	0	1	0	0
T92	0	2	0	0
T97	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	247	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	3	0	0
T15	764613	0	0	0
T16	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	0	0	0
T37	0	3	0	0
T41	0	2	0	0
T58	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766355426	324455361	0	0
T1	93363	93267	0	0
T2	922444	642305	0	0
T3	78935	78858	0	0
T4	468746	2983	0	0
T5	299338	10158	0	0
T6	120484	3165	0	0
T7	30028	727	0	0
T18	80736	69061	0	0
T19	33744	12774	0	0
T22	518139	501323	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	645	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	7	0	0
T15	764613	1	0	0
T16	0	5	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	635	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	7	0	0
T15	764613	1	0	0
T16	0	5	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	625	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	7	0	0
T15	764613	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	614	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	7	0	0
T15	764613	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	882	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	7	0	0
T15	764613	0	0	0
T16	0	1	0	0
T18	80736	1	0	0
T19	33744	8	0	0
T22	518139	5	0	0
T40	0	1	0	0
T41	0	1	0	0
T58	0	13	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	114575	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	2322	0	0
T15	764613	0	0	0
T16	0	105	0	0
T18	80736	239	0	0
T19	33744	452	0	0
T22	518139	796	0	0
T40	0	159	0	0
T41	0	29	0	0
T58	0	2423	0	0
T86	0	117	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	796	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	4	0	0
T15	764613	0	0	0
T16	445378	1	0	0
T18	80736	1	0	0
T19	33744	8	0	0
T20	27643	0	0	0
T22	518139	5	0	0
T40	0	1	0	0
T41	0	1	0	0
T58	0	12	0	0
T75	0	1	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	55	0	0
T10	837963	1	0	0
T17	311747	0	0	0
T33	72811	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	277880	0	0	0
T56	445552	0	0	0
T57	311664	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	3	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	348882	0	0	0
T84	0	1	0	0
T89	0	1	0	0
T94	2777	0	0	0
T95	98161	0	0	0
T96	333872	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1615	0	0
T11	46360	350	0	0
T12	0	179	0	0
T13	0	372	0	0
T42	0	353	0	0
T43	0	361	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1345	0	0
T11	46360	290	0	0
T12	0	149	0	0
T13	0	312	0	0
T42	0	293	0	0
T43	0	301	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	766423669	0	0
T1	93363	93268	0	0
T2	922444	922320	0	0
T3	78935	78859	0	0
T4	468746	468741	0	0
T5	299338	299330	0	0
T6	120484	120474	0	0
T7	30028	29899	0	0
T18	80736	80642	0	0
T19	33744	33685	0	0
T22	518139	518091	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T22,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T22,T18
1	0	1	Covered	T2,T22,T5
1	1	0	Covered	T22,T19,T16
1	1	1	Covered	T2,T22,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T18
0	1	Covered	T10,T33,T58
1	0	Covered	T16,T10,T92

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T10,T92

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Not Covered
1	1	Covered	T10,T33,T58

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T10,T57,T80

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T22,T16,T10

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T6,T16,T17

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T22,T6,T16
1	Covered	T2,T4,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T22,T4,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T10,T33
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T92,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T60,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T37,T60
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T38,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T22,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T10,T83
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T22,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	766612282	280	0	0
CheckAccumTrig0_A	766612282	577	0	0
CheckAccumTrig1_A	766612282	32	0	0
CheckClr_A	766612282	266	0	0
CheckEn_A	766355426	329280855	0	0
CheckPhase0_A	766612282	662	0	0
CheckPhase1_A	766612282	652	0	0
CheckPhase2_A	766612282	642	0	0
CheckPhase3_A	766612282	627	0	0
CheckTimeout0_A	766612282	578	0	0
CheckTimeoutSt1_A	766612282	79885	0	0
CheckTimeoutSt2_A	766612282	481	0	0
CheckTimeoutStTrig_A	766612282	65	0	0
ErrorStAllEscAsserted_A	766612282	1556	0	0
ErrorStIsTerminal_A	766612282	1286	0	0
u_state_regs_A	766612282	766423669	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	280	0	0
T11	46360	39	0	0
T12	0	43	0	0
T13	0	53	0	0
T42	0	96	0	0
T43	0	49	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	577	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	7	0	0
T15	764613	0	0	0
T16	0	4	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	3	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	32	0	0
T8	669061	0	0	0
T10	837963	3	0	0
T16	445378	1	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T34	29327	0	0	0
T40	11831	0	0	0
T53	1023	0	0	0
T54	356880	0	0	0
T63	0	1	0	0
T73	18861	0	0	0
T92	0	2	0	0
T93	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	266	0	0
T8	669061	0	0	0
T10	837963	4	0	0
T16	445378	3	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T34	29327	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	11831	0	0	0
T53	1023	0	0	0
T54	356880	0	0	0
T58	0	9	0	0
T73	18861	0	0	0
T76	0	4	0	0
T83	0	1	0	0
T84	0	1	0	0
T113	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766355426	329280855	0	0
T1	93363	93267	0	0
T2	922444	635396	0	0
T3	78935	78858	0	0
T4	468746	13723	0	0
T5	299338	14124	0	0
T6	120484	594	0	0
T7	30028	731	0	0
T18	80736	2980	0	0
T19	33744	33684	0	0
T22	518139	432830	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	662	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	11	0	0
T15	764613	0	0	0
T16	0	5	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	3	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	652	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	10	0	0
T15	764613	0	0	0
T16	0	5	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	3	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	642	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	9	0	0
T15	764613	0	0	0
T16	0	5	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	3	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	627	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	1	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	9	0	0
T15	764613	0	0	0
T16	0	4	0	0
T17	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	3	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	578	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	4	0	0
T15	764613	0	0	0
T16	0	1	0	0
T18	80736	10	0	0
T19	33744	0	0	0
T22	518139	9	0	0
T33	0	1	0	0
T58	0	9	0	0
T75	0	1	0	0
T76	0	3	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	79885	0	0
T2	922444	487	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	176	0	0
T15	764613	0	0	0
T16	0	1	0	0
T18	80736	2349	0	0
T19	33744	0	0	0
T22	518139	1441	0	0
T33	0	569	0	0
T58	0	823	0	0
T75	0	45	0	0
T76	0	612	0	0
T86	0	28	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	481	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T15	764613	0	0	0
T18	80736	10	0	0
T19	33744	0	0	0
T22	518139	9	0	0
T37	0	2	0	0
T38	0	1	0	0
T58	0	5	0	0
T75	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	65	0	0
T10	837963	1	0	0
T17	311747	0	0	0
T33	72811	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T41	277880	0	0	0
T56	445552	0	0	0
T57	311664	0	0	0
T58	0	4	0	0
T60	0	2	0	0
T78	0	1	0	0
T80	348882	0	0	0
T87	0	1	0	0
T88	0	3	0	0
T91	0	1	0	0
T94	2777	0	0	0
T95	98161	0	0	0
T96	333872	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1556	0	0
T11	46360	325	0	0
T12	0	169	0	0
T13	0	352	0	0
T42	0	385	0	0
T43	0	325	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1286	0	0
T11	46360	265	0	0
T12	0	139	0	0
T13	0	292	0	0
T42	0	325	0	0
T43	0	265	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	766423669	0	0
T1	93363	93268	0	0
T2	922444	922320	0	0
T3	78935	78859	0	0
T4	468746	468741	0	0
T5	299338	299330	0	0
T6	120484	120474	0	0
T7	30028	29899	0	0
T18	80736	80642	0	0
T19	33744	33685	0	0
T22	518139	518091	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T22,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T22,T18
1	0	1	Covered	T2,T22,T15
1	1	0	Covered	T22,T18,T19
1	1	1	Covered	T2,T22,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T18
0	1	Covered	T18,T10,T58
1	0	Covered	T16,T10,T60

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T22,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T10,T60

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T18
1	0	Covered	T35
1	1	Covered	T18,T10,T58

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T15,T53,T8

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T2,T4,T10

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T22,T4
1	Covered	T16,T17,T80

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T2,T22,T4

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T22,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T16,T10
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T38,T39,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T40,T10
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T22,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T81,T61,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T22,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T37,T114
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T22,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T22,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T22,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	766612282	332	0	0
CheckAccumTrig0_A	766612282	539	0	0
CheckAccumTrig1_A	766612282	26	0	0
CheckClr_A	766612282	243	0	0
CheckEn_A	766355426	334746629	0	0
CheckPhase0_A	766612282	628	0	0
CheckPhase1_A	766612282	611	0	0
CheckPhase2_A	766612282	602	0	0
CheckPhase3_A	766612282	591	0	0
CheckTimeout0_A	766612282	1031	0	0
CheckTimeoutSt1_A	766612282	112343	0	0
CheckTimeoutSt2_A	766612282	933	0	0
CheckTimeoutStTrig_A	766612282	72	0	0
ErrorStAllEscAsserted_A	766612282	1682	0	0
ErrorStIsTerminal_A	766612282	1412	0	0
u_state_regs_A	766612282	766423669	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	332	0	0
T11	46360	73	0	0
T12	0	48	0	0
T13	0	76	0	0
T42	0	64	0	0
T43	0	71	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	539	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	6	0	0
T15	764613	1	0	0
T16	0	1	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	26	0	0
T8	669061	0	0	0
T10	837963	1	0	0
T16	445378	2	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T34	29327	0	0	0
T40	11831	0	0	0
T52	0	1	0	0
T53	1023	0	0	0
T54	356880	0	0	0
T60	0	1	0	0
T61	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T73	18861	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	243	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	1	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	4	0	0
T15	764613	0	0	0
T16	0	2	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T58	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T81	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766355426	334746629	0	0
T1	93363	93267	0	0
T2	922444	634566	0	0
T3	78935	78858	0	0
T4	468746	2967	0	0
T5	299338	298814	0	0
T6	120484	120474	0	0
T7	30028	723	0	0
T18	80736	6771	0	0
T19	33744	25609	0	0
T22	518139	484388	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	628	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T15	764613	1	0	0
T16	0	3	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T40	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	611	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	6	0	0
T15	764613	1	0	0
T16	0	2	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	602	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	6	0	0
T15	764613	1	0	0
T16	0	2	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	591	0	0
T2	922444	2	0	0
T3	78935	0	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	6	0	0
T15	764613	1	0	0
T16	0	1	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T22	518139	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1031	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	12	0	0
T15	764613	0	0	0
T16	0	3	0	0
T18	80736	1	0	0
T19	33744	2	0	0
T22	518139	9	0	0
T37	0	1	0	0
T58	0	14	0	0
T75	0	1	0	0
T76	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	112343	0	0
T2	922444	211	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	2341	0	0
T15	764613	0	0	0
T16	0	111	0	0
T18	80736	26	0	0
T19	33744	123	0	0
T22	518139	1476	0	0
T37	0	565	0	0
T58	0	1064	0	0
T75	0	85	0	0
T76	0	454	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	933	0	0
T2	922444	1	0	0
T3	78935	0	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	10	0	0
T15	764613	0	0	0
T16	0	1	0	0
T18	80736	0	0	0
T19	33744	2	0	0
T22	518139	9	0	0
T58	0	12	0	0
T59	0	1	0	0
T60	0	2	0	0
T75	0	1	0	0
T76	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	72	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T10	0	1	0	0
T15	764613	0	0	0
T16	445378	0	0	0
T18	80736	1	0	0
T19	33744	0	0	0
T20	27643	0	0	0
T21	13919	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	11831	0	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	1	0	0
T76	0	2	0	0
T92	0	1	0	0
T93	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1682	0	0
T11	46360	383	0	0
T12	0	198	0	0
T13	0	361	0	0
T42	0	358	0	0
T43	0	382	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1412	0	0
T11	46360	323	0	0
T12	0	168	0	0
T13	0	301	0	0
T42	0	298	0	0
T43	0	322	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	766423669	0	0
T1	93363	93268	0	0
T2	922444	922320	0	0
T3	78935	78859	0	0
T4	468746	468741	0	0
T5	299338	299330	0	0
T6	120484	120474	0	0
T7	30028	29899	0	0
T18	80736	80642	0	0
T19	33744	33685	0	0
T22	518139	518091	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T32
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T22,T4
1	1	0	Covered	T2,T3,T22
1	1	1	Covered	T22,T18,T6

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T6
0	1	Covered	T10,T41,T58
1	0	Covered	T34,T58,T37

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T18,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T34,T58,T37

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T6
1	0	Covered	T10,T36
1	1	Covered	T10,T41,T58

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T22

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T22,T16

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T18,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T34,T10,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T18,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T18,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T39,T63
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T41,T58
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T22,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T41,T58
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	766612282	292	0	0
CheckAccumTrig0_A	766612282	1045	0	0
CheckAccumTrig1_A	766612282	49	0	0
CheckClr_A	766612282	555	0	0
CheckEn_A	766355426	267944570	0	0
CheckPhase0_A	766612282	1133	0	0
CheckPhase1_A	766612282	1108	0	0
CheckPhase2_A	766612282	1075	0	0
CheckPhase3_A	766612282	1044	0	0
CheckTimeout0_A	766612282	2108	0	0
CheckTimeoutSt1_A	766612282	170074	0	0
CheckTimeoutSt2_A	766612282	2000	0	0
CheckTimeoutStTrig_A	766612282	59	0	0
ErrorStAllEscAsserted_A	766612282	1654	0	0
ErrorStIsTerminal_A	766612282	1384	0	0
u_state_regs_A	766612282	766423669	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	292	0	0
T11	46360	78	0	0
T12	0	45	0	0
T13	0	72	0	0
T42	0	54	0	0
T43	0	43	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1045	0	0
T1	93363	2	0	0
T2	922444	8	0	0
T3	78935	4	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T20	0	1	0	0
T22	518139	5	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	49	0	0
T34	29327	1	0	0
T37	129723	1	0	0
T54	356880	0	0	0
T58	598156	1	0	0
T59	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T73	18861	0	0	0
T74	84291	0	0	0
T75	7232	0	0	0
T76	116694	0	0	0
T77	12386	0	0	0
T78	31860	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	555	0	0
T1	93363	1	0	0
T2	922444	6	0	0
T3	78935	4	0	0
T4	468746	1	0	0
T5	299338	0	0	0
T6	120484	0	0	0
T7	30028	0	0	0
T8	0	1	0	0
T10	0	15	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T20	0	1	0	0
T22	518139	1	0	0
T79	0	1	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766355426	267944570	0	0
T1	93363	6709	0	0
T2	922444	296313	0	0
T3	78935	47303	0	0
T4	468746	14608	0	0
T5	299338	299330	0	0
T6	120484	582	0	0
T7	30028	719	0	0
T18	80736	14507	0	0
T19	33744	1651	0	0
T22	518139	588523	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1133	0	0
T1	93363	2	0	0
T2	922444	8	0	0
T3	78935	4	0	0
T4	468746	2	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T20	0	1	0	0
T22	518139	5	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1108	0	0
T1	93363	2	0	0
T2	922444	8	0	0
T3	78935	4	0	0
T4	468746	1	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T20	0	1	0	0
T22	518139	5	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1075	0	0
T1	93363	2	0	0
T2	922444	8	0	0
T3	78935	3	0	0
T4	468746	1	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	4	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1044	0	0
T1	93363	2	0	0
T2	922444	8	0	0
T3	78935	3	0	0
T4	468746	1	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T8	0	1	0	0
T15	0	1	0	0
T16	0	3	0	0
T18	80736	0	0	0
T19	33744	0	0	0
T22	518139	4	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	2108	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	17	0	0
T15	764613	0	0	0
T16	445378	0	0	0
T18	80736	9	0	0
T19	33744	8	0	0
T20	27643	0	0	0
T22	518139	5	0	0
T34	0	2	0	0
T41	0	4	0	0
T58	0	12	0	0
T75	0	2	0	0
T85	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	170074	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	114	0	0
T7	30028	0	0	0
T10	0	6377	0	0
T15	764613	0	0	0
T16	445378	0	0	0
T18	80736	2027	0	0
T19	33744	468	0	0
T20	27643	0	0	0
T22	518139	805	0	0
T34	0	60	0	0
T41	0	261	0	0
T58	0	1154	0	0
T75	0	161	0	0
T85	0	83	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	2000	0	0
T4	468746	0	0	0
T5	299338	0	0	0
T6	120484	1	0	0
T7	30028	0	0	0
T10	0	14	0	0
T15	764613	0	0	0
T16	445378	0	0	0
T18	80736	9	0	0
T19	33744	8	0	0
T20	27643	0	0	0
T22	518139	5	0	0
T34	0	1	0	0
T41	0	2	0	0
T58	0	8	0	0
T75	0	2	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	59	0	0
T10	837963	3	0	0
T17	311747	0	0	0
T33	72811	0	0	0
T37	0	1	0	0
T41	277880	2	0	0
T56	445552	0	0	0
T57	311664	0	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T80	348882	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	2777	0	0	0
T95	98161	0	0	0
T96	333872	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1654	0	0
T11	46360	371	0	0
T12	0	179	0	0
T13	0	376	0	0
T42	0	384	0	0
T43	0	344	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	1384	0	0
T11	46360	311	0	0
T12	0	149	0	0
T13	0	316	0	0
T42	0	324	0	0
T43	0	284	0	0
T44	29208	0	0	0
T45	28091	0	0	0
T46	11307	0	0	0
T47	9334	0	0	0
T48	74981	0	0	0
T49	47127	0	0	0
T50	418919	0	0	0
T51	328489	0	0	0
T52	128759	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	766612282	766423669	0	0
T1	93363	93268	0	0
T2	922444	922320	0	0
T3	78935	78859	0	0
T4	468746	468741	0	0
T5	299338	299330	0	0
T6	120484	120474	0	0
T7	30028	29899	0	0
T18	80736	80642	0	0
T19	33744	33685	0	0
T22	518139	518091	0	0