Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66256114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32328217

1

T14

13

T24

409

T25

315

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14995905	1			T14	20		T24	560		T25	350
values[0x0]	40542545	1			T14	11		T24	382		T25	208
values[0x1]	43045881	1			T14	9		T24	418		T25	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56284367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42299964

1

T14

16

T24

618

T25

407

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	322007	1			T24	6		T25	4		T26	22
valid_sources[0x01]	316617	1			T24	12		T25	1		T26	50
valid_sources[0x02]	309544	1			T24	4		T26	28		T27	31
valid_sources[0x03]	313215	1			T24	1		T25	4		T26	40
valid_sources[0x04]	521852	1			T24	6		T25	4		T26	26
valid_sources[0x05]	1229360	1			T24	6		T25	1		T26	19
valid_sources[0x06]	305944	1			T24	7		T25	2		T26	8
valid_sources[0x07]	546551	1			T24	5		T25	4		T26	26
valid_sources[0x08]	315754	1			T24	5		T25	3		T26	18
valid_sources[0x09]	316772	1			T24	8		T25	2		T26	9
valid_sources[0x0a]	308566	1			T24	10		T26	28		T27	30
valid_sources[0x0b]	319102	1			T24	5		T25	5		T26	21
valid_sources[0x0c]	315648	1			T24	4		T25	1		T26	28
valid_sources[0x0d]	309792	1			T24	1		T25	4		T26	34
valid_sources[0x0e]	317926	1			T24	3		T25	4		T26	14
valid_sources[0x0f]	306808	1			T25	9		T26	25		T27	27
valid_sources[0x10]	783135	1			T24	3		T25	3		T26	39
valid_sources[0x11]	590568	1			T24	1		T25	1		T26	27
valid_sources[0x12]	340828	1			T24	10		T25	4		T26	12
valid_sources[0x13]	317900	1			T24	8		T25	6		T26	48
valid_sources[0x14]	319595	1			T24	6		T25	3		T26	19
valid_sources[0x15]	317936	1			T24	4		T25	6		T26	18
valid_sources[0x16]	414584	1			T24	7		T25	3		T26	34
valid_sources[0x17]	311902	1			T24	7		T25	3		T26	29
valid_sources[0x18]	313966	1			T24	5		T25	1		T26	45
valid_sources[0x19]	310089	1			T24	6		T25	2		T26	35
valid_sources[0x1a]	325002	1			T24	4		T25	5		T26	14
valid_sources[0x1b]	316748	1			T24	4		T25	3		T26	28
valid_sources[0x1c]	313266	1			T24	3		T25	2		T26	8
valid_sources[0x1d]	578292	1			T14	2		T24	3		T25	4
valid_sources[0x1e]	308144	1			T24	5		T25	3		T26	20
valid_sources[0x1f]	323019	1			T24	10		T25	1		T26	26
valid_sources[0x20]	671756	1			T24	5		T25	3		T26	35
valid_sources[0x21]	314345	1			T24	4		T25	3		T26	19
valid_sources[0x22]	315900	1			T24	4		T25	3		T26	40
valid_sources[0x23]	992886	1			T25	3		T26	31		T27	24
valid_sources[0x24]	309694	1			T24	5		T25	3		T26	41
valid_sources[0x25]	321132	1			T24	4		T25	2		T26	15
valid_sources[0x26]	315472	1			T14	1		T25	4		T26	25
valid_sources[0x27]	363426	1			T24	5		T25	2		T26	20
valid_sources[0x28]	313377	1			T24	5		T25	2		T26	21
valid_sources[0x29]	322332	1			T14	2		T24	6		T25	2
valid_sources[0x2a]	311665	1			T24	6		T25	4		T26	26
valid_sources[0x2b]	321753	1			T24	8		T25	2		T26	46
valid_sources[0x2c]	319666	1			T24	4		T25	6		T26	7
valid_sources[0x2d]	758251	1			T24	10		T25	4		T26	11
valid_sources[0x2e]	355234	1			T14	2		T24	7		T25	4
valid_sources[0x2f]	755495	1			T24	10		T25	1		T26	15
valid_sources[0x30]	312934	1			T24	4		T25	4		T26	14
valid_sources[0x31]	311031	1			T14	1		T24	3		T25	2
valid_sources[0x32]	731149	1			T24	5		T25	1		T26	41
valid_sources[0x33]	313108	1			T24	2		T25	4		T26	34
valid_sources[0x34]	306330	1			T24	6		T25	1		T26	9
valid_sources[0x35]	311354	1			T24	3		T25	3		T26	34
valid_sources[0x36]	312121	1			T24	7		T25	4		T26	48
valid_sources[0x37]	645371	1			T24	3		T25	5		T26	27
valid_sources[0x38]	748416	1			T24	7		T25	4		T26	37
valid_sources[0x39]	648384	1			T24	7		T25	2		T26	40
valid_sources[0x3a]	312360	1			T24	4		T25	1		T26	17
valid_sources[0x3b]	333456	1			T24	5		T25	1		T26	16
valid_sources[0x3c]	307687	1			T24	2		T25	4		T26	24
valid_sources[0x3d]	315148	1			T24	2		T25	3		T26	41
valid_sources[0x3e]	618764	1			T24	2		T25	4		T26	22
valid_sources[0x3f]	309089	1			T14	1		T24	6		T25	1
valid_sources[0x40]	696290	1			T24	8		T25	2		T26	7
valid_sources[0x41]	304957	1			T24	6		T25	3		T26	22
valid_sources[0x42]	326531	1			T24	2		T25	4		T26	27
valid_sources[0x43]	316931	1			T24	7		T25	3		T26	27
valid_sources[0x44]	340690	1			T24	7		T25	2		T26	23
valid_sources[0x45]	318655	1			T24	8		T25	4		T26	18
valid_sources[0x46]	312767	1			T24	5		T25	3		T26	28
valid_sources[0x47]	314036	1			T24	5		T26	18		T27	32
valid_sources[0x48]	317105	1			T24	8		T25	4		T26	10
valid_sources[0x49]	628780	1			T24	10		T25	2		T26	57
valid_sources[0x4a]	311133	1			T24	3		T26	55		T27	45
valid_sources[0x4b]	308995	1			T24	4		T25	4		T26	23
valid_sources[0x4c]	526381	1			T24	8		T25	6		T26	63
valid_sources[0x4d]	318162	1			T24	8		T25	2		T26	36
valid_sources[0x4e]	671217	1			T24	7		T25	5		T26	17
valid_sources[0x4f]	334111	1			T24	5		T25	1		T26	16
valid_sources[0x50]	309586	1			T24	6		T25	3		T26	23
valid_sources[0x51]	316000	1			T24	9		T25	2		T26	36
valid_sources[0x52]	313312	1			T24	4		T25	5		T26	15
valid_sources[0x53]	313205	1			T24	7		T25	2		T26	17
valid_sources[0x54]	314104	1			T24	7		T25	5		T26	8
valid_sources[0x55]	319342	1			T14	4		T24	5		T25	4
valid_sources[0x56]	715766	1			T24	5		T25	3		T26	13
valid_sources[0x57]	308313	1			T24	8		T25	5		T26	34
valid_sources[0x58]	310124	1			T24	10		T25	4		T26	18
valid_sources[0x59]	311916	1			T24	5		T25	4		T26	23
valid_sources[0x5a]	313081	1			T14	1		T24	9		T25	3
valid_sources[0x5b]	745758	1			T24	7		T25	7		T26	23
valid_sources[0x5c]	321646	1			T24	4		T25	3		T26	25
valid_sources[0x5d]	316049	1			T24	8		T25	2		T26	43
valid_sources[0x5e]	310683	1			T24	2		T25	3		T26	35
valid_sources[0x5f]	316186	1			T24	3		T25	2		T26	25
valid_sources[0x60]	796477	1			T24	7		T25	1		T26	23
valid_sources[0x61]	571282	1			T24	5		T25	2		T26	34
valid_sources[0x62]	316554	1			T24	8		T25	4		T26	22
valid_sources[0x63]	311903	1			T24	5		T26	26		T27	20
valid_sources[0x64]	353439	1			T24	4		T25	3		T26	28
valid_sources[0x65]	322747	1			T24	7		T25	2		T26	14
valid_sources[0x66]	313425	1			T24	4		T25	3		T26	35
valid_sources[0x67]	325859	1			T24	1		T25	1		T26	27
valid_sources[0x68]	315021	1			T24	7		T25	4		T26	18
valid_sources[0x69]	314343	1			T24	5		T25	2		T26	44
valid_sources[0x6a]	315471	1			T24	8		T25	4		T26	35
valid_sources[0x6b]	313557	1			T14	1		T24	2		T25	2
valid_sources[0x6c]	318733	1			T24	4		T25	3		T26	46
valid_sources[0x6d]	518357	1			T24	9		T25	3		T26	47
valid_sources[0x6e]	555028	1			T14	7		T24	3		T25	5
valid_sources[0x6f]	316943	1			T24	4		T25	3		T26	35
valid_sources[0x70]	314691	1			T24	5		T25	4		T26	14
valid_sources[0x71]	312385	1			T24	4		T25	1		T26	34
valid_sources[0x72]	316739	1			T24	3		T25	2		T26	45
valid_sources[0x73]	305074	1			T24	10		T25	6		T26	33
valid_sources[0x74]	527383	1			T24	4		T25	3		T26	7
valid_sources[0x75]	311013	1			T14	3		T24	9		T25	1
valid_sources[0x76]	312198	1			T24	3		T25	3		T26	12
valid_sources[0x77]	312088	1			T24	1		T25	1		T26	10
valid_sources[0x78]	310571	1			T14	3		T24	4		T25	2
valid_sources[0x79]	313358	1			T24	5		T25	1		T26	14
valid_sources[0x7a]	311710	1			T24	7		T25	3		T26	21
valid_sources[0x7b]	309738	1			T24	6		T26	22		T27	29
valid_sources[0x7c]	312942	1			T24	5		T25	3		T26	7
valid_sources[0x7d]	318341	1			T24	3		T25	5		T26	35
valid_sources[0x7e]	307995	1			T24	1		T25	6		T26	21
valid_sources[0x7f]	326985	1			T24	1		T25	2		T26	23
valid_sources[0x80]	306314	1			T24	7		T25	1		T26	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7501836

1

T14

9

T24

167

T25

177

values[0x0]

all_enables

biggest_size

15621999

1

T14

2

T24

153

T25

86

values[0x1]

all_enables

biggest_size

9204382

1

T14

2

T24

89

T25

52