Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T83,T210
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14357	0	0
DisabledNoTrigBkwd_A	2147483647	876630	0	0
DisabledNoTrigFwd_A	2147483647	1662800439	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14357	0	0
T8	421192	0	0	0
T15	282559	0	0	0
T35	70559	0	0	0
T45	0	651	0	0
T56	3439	790	0	0
T57	117146	0	0	0
T58	35232	0	0	0
T83	1369	576	0	0
T114	124571	0	0	0
T210	0	1638	0	0
T211	0	752	0	0
T212	0	977	0	0
T213	0	846	0	0
T214	0	405	0	0
T215	1088	326	0	0
T216	1266	537	0	0
T217	4143	515	0	0
T218	0	1138	0	0
T219	0	1030	0	0
T220	0	582	0	0
T221	0	638	0	0
T222	0	698	0	0
T223	0	661	0	0
T224	0	291	0	0
T225	0	878	0	0
T226	0	428	0	0
T227	20209	0	0	0
T228	23055	0	0	0
T229	2265	0	0	0
T230	77825	0	0	0
T231	946289	0	0	0
T232	208755	0	0	0
T233	247884	0	0	0
T234	204926	0	0	0
T235	917455	0	0	0
T236	844157	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	876630	0	0
T2	1785020	3705	0	0
T3	541392	92	0	0
T4	561136	1518	0	0
T5	932812	5503	0	0
T6	2062356	2342	0	0
T8	0	462	0	0
T15	0	724	0	0
T16	0	5017	0	0
T17	0	266	0	0
T19	259736	5	0	0
T20	22632	0	0	0
T21	1388616	416	0	0
T22	343528	2	0	0
T23	309908	88	0	0
T35	0	19	0	0
T54	0	29	0	0
T55	0	1	0	0
T56	0	10	0	0
T57	0	47	0	0
T58	0	104	0	0
T59	0	34	0	0
T60	0	2431	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662800439	0	0
T1	502812	705853	0	0
T2	1785020	923314	0	0
T3	541392	1790827	0	0
T4	561136	560366	0	0
T5	932812	473087	0	0
T19	259736	197630	0	0
T20	22632	19477	0	0
T21	1388616	673248	0	0
T22	343528	260613	0	0
T23	309908	104823	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T216,T224,T226
1	1	Covered	T2,T3,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	758595158	1256	0	0
DisabledNoTrigBkwd_A	758595158	276031	0	0
DisabledNoTrigFwd_A	758595158	388338396	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1256	0	0
T114	124571	0	0	0
T216	1266	537	0	0
T217	4143	0	0	0
T224	0	291	0	0
T226	0	428	0	0
T230	77825	0	0	0
T231	946289	0	0	0
T232	208755	0	0	0
T233	247884	0	0	0
T234	204926	0	0	0
T235	917455	0	0	0
T236	844157	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	276031	0	0
T2	446255	11	0	0
T3	135348	89	0	0
T4	140284	76	0	0
T5	233203	4221	0	0
T6	515589	0	0	0
T16	0	1648	0	0
T19	64934	5	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	6	0	0
T54	0	5	0	0
T55	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	388338396	0	0
T1	125703	120992	0	0
T2	446255	444341	0	0
T3	135348	684681	0	0
T4	140284	124230	0	0
T5	233203	3311	0	0
T19	64934	3050	0	0
T20	5658	5603	0	0
T21	347154	323821	0	0
T22	85882	3123	0	0
T23	77477	66303	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T215
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	758595158	1116	0	0
DisabledNoTrigBkwd_A	758595158	190747	0	0
DisabledNoTrigFwd_A	758595158	451554874	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1116	0	0
T8	421192	0	0	0
T15	282559	0	0	0
T35	70559	0	0	0
T56	3439	790	0	0
T57	117146	0	0	0
T58	35232	0	0	0
T215	1088	326	0	0
T227	20209	0	0	0
T228	23055	0	0	0
T229	2265	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	190747	0	0
T2	446255	1833	0	0
T3	135348	3	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	722	0	0
T16	0	1515	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	176	0	0
T22	85882	0	0	0
T23	77477	23	0	0
T54	0	24	0	0
T56	0	10	0	0
T58	0	55	0	0
T59	0	34	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	451554874	0	0
T1	125703	123148	0	0
T2	446255	26300	0	0
T3	135348	846454	0	0
T4	140284	139737	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	13407	0	0
T22	85882	85830	0	0
T23	77477	9317	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T83,T45,T211
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	758595158	5560	0	0
DisabledNoTrigBkwd_A	758595158	205208	0	0
DisabledNoTrigFwd_A	758595158	405471692	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	5560	0	0
T45	0	651	0	0
T83	1369	576	0	0
T84	285611	0	0	0
T85	460170	0	0	0
T97	37453	0	0	0
T98	154298	0	0	0
T211	0	752	0	0
T212	0	977	0	0
T213	0	846	0	0
T217	0	515	0	0
T220	0	582	0	0
T223	0	661	0	0
T237	74894	0	0	0
T238	304759	0	0	0
T239	254053	0	0	0
T240	347638	0	0	0
T241	782152	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	205208	0	0
T2	446255	5	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2338	0	0
T16	0	1854	0	0
T17	0	266	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	239	0	0
T22	85882	0	0	0
T23	77477	36	0	0
T35	0	19	0	0
T57	0	47	0	0
T58	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	405471692	0	0
T1	125703	125697	0	0
T2	446255	444341	0	0
T3	135348	127726	0	0
T4	140284	139545	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	1991	0	0
T22	85882	85830	0	0
T23	77477	15019	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T214,T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	758595158	6425	0	0
DisabledNoTrigBkwd_A	758595158	204644	0	0
DisabledNoTrigFwd_A	758595158	417435477	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	6425	0	0
T62	749222	0	0	0
T63	294996	0	0	0
T102	25754	0	0	0
T104	351446	0	0	0
T210	5498	1638	0	0
T214	0	405	0	0
T218	0	1138	0	0
T219	0	1030	0	0
T221	0	638	0	0
T222	0	698	0	0
T225	0	878	0	0
T242	144426	0	0	0
T243	158002	0	0	0
T244	69616	0	0	0
T245	31842	0	0	0
T246	438795	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	204644	0	0
T2	446255	1856	0	0
T3	135348	0	0	0
T4	140284	1441	0	0
T5	233203	1282	0	0
T6	515589	4	0	0
T8	0	462	0	0
T15	0	2	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	23	0	0
T58	0	47	0	0
T60	0	2431	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	417435477	0	0
T1	125703	336016	0	0
T2	446255	8332	0	0
T3	135348	131966	0	0
T4	140284	156854	0	0
T5	233203	3380	0	0
T19	64934	64860	0	0
T20	5658	2668	0	0
T21	347154	334029	0	0
T22	85882	85830	0	0
T23	77477	14184	0	0