Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T33
1	1	1	Covered	T2,T3,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T3,T19
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T34
1	0	Covered	T2,T35,T36

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T35,T36

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T37
1	1	Covered	T3,T4,T34

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T2,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T2,T23,T6

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T4,T21,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T19,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T38,T39
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T41,T42
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T9,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T15,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1293	0	0
CheckAccumTrig0_A	2147483647	2597	0	0
CheckAccumTrig1_A	2147483647	134	0	0
CheckClr_A	2147483647	1230	0	0
CheckEn_A	2147483647	1313890438	0	0
CheckPhase0_A	2147483647	2991	0	0
CheckPhase1_A	2147483647	2944	0	0
CheckPhase2_A	2147483647	2898	0	0
CheckPhase3_A	2147483647	2853	0	0
CheckTimeout0_A	2147483647	4499	0	0
CheckTimeoutSt1_A	2147483647	533032	0	0
CheckTimeoutSt2_A	2147483647	4072	0	0
CheckTimeoutStTrig_A	2147483647	293	0	0
ErrorStAllEscAsserted_A	2147483647	6526	0	0
ErrorStIsTerminal_A	2147483647	5446	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293	0	0
T11	131196	265	0	0
T12	0	303	0	0
T13	0	145	0	0
T43	0	311	0	0
T44	0	269	0	0
T45	16256	0	0	0
T46	22668	0	0	0
T47	14320	0	0	0
T48	190080	0	0	0
T49	345148	0	0	0
T50	138252	0	0	0
T51	495704	0	0	0
T52	2621940	0	0	0
T53	3915964	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2597	0	0
T2	892510	3	0	0
T3	270696	4	0	0
T4	420852	3	0	0
T5	932812	4	0	0
T6	2062356	3	0	0
T7	38748	0	0	0
T8	0	2	0	0
T15	0	9	0	0
T16	0	6	0	0
T17	0	1	0	0
T19	129868	2	0	0
T20	16974	0	0	0
T21	1388616	3	0	0
T22	343528	2	0	0
T23	309908	4	0	0
T35	70559	2	0	0
T54	71316	2	0	0
T55	108024	1	0	0
T56	3439	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	1	0	0
T60	0	6	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	134	0	0
T2	446255	1	0	0
T35	0	1	0	0
T36	114384	1	0	0
T48	0	1	0	0
T61	107282	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	94362	1	0	0
T65	0	1	0	0
T66	236702	1	0	0
T67	0	3	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	4	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	35953	0	0	0
T79	22774	0	0	0
T80	2068	0	0	0
T81	333254	0	0	0
T82	164621	0	0	0
T83	1369	0	0	0
T84	285611	0	0	0
T85	460170	0	0	0
T86	38613	0	0	0
T87	826126	0	0	0
T88	278244	0	0	0
T89	27800	0	0	0
T90	76241	0	0	0
T91	86983	0	0	0
T92	9051	0	0	0
T93	286912	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1230	0	0
T2	446255	1	0	0
T3	270696	2	0	0
T4	280568	1	0	0
T5	699609	2	0	0
T6	2062356	1	0	0
T7	38748	0	0	0
T8	421192	0	0	0
T9	0	1	0	0
T15	282559	7	0	0
T16	0	3	0	0
T18	0	1	0	0
T19	129868	1	0	0
T20	11316	0	0	0
T21	1041462	0	0	0
T22	257646	1	0	0
T23	232431	0	0	0
T34	0	1	0	0
T35	141118	2	0	0
T36	0	3	0	0
T39	0	25	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	2	0	0
T54	106974	0	0	0
T55	108024	0	0	0
T56	6878	0	0	0
T57	117146	0	0	0
T58	35232	2	0	0
T85	0	1	0	0
T94	0	11	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313890438	0	0
T1	502812	705852	0	0
T2	1785020	29990	0	0
T3	541392	2517618	0	0
T4	561136	493361	0	0
T5	932812	473087	0	0
T19	259736	197627	0	0
T20	22632	19474	0	0
T21	1388616	673246	0	0
T22	343528	260610	0	0
T23	309908	36723	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2991	0	0
T2	1785020	5	0	0
T3	541392	5	0	0
T4	561136	6	0	0
T5	932812	4	0	0
T6	2062356	3	0	0
T8	0	2	0	0
T15	0	9	0	0
T16	0	2	0	0
T19	259736	2	0	0
T20	22632	0	0	0
T21	1388616	3	0	0
T22	343528	2	0	0
T23	309908	4	0	0
T34	0	1	0	0
T35	0	3	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T60	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2944	0	0
T2	1785020	5	0	0
T3	541392	5	0	0
T4	561136	6	0	0
T5	932812	4	0	0
T6	2062356	3	0	0
T8	0	2	0	0
T15	0	9	0	0
T16	0	2	0	0
T19	259736	2	0	0
T20	22632	0	0	0
T21	1388616	3	0	0
T22	343528	2	0	0
T23	309908	4	0	0
T34	0	1	0	0
T35	0	3	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T60	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2898	0	0
T2	1785020	5	0	0
T3	541392	5	0	0
T4	561136	6	0	0
T5	932812	4	0	0
T6	2062356	3	0	0
T8	0	2	0	0
T15	0	9	0	0
T16	0	2	0	0
T19	259736	2	0	0
T20	22632	0	0	0
T21	1388616	3	0	0
T22	343528	2	0	0
T23	309908	4	0	0
T34	0	1	0	0
T35	0	3	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T60	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2853	0	0
T2	1785020	5	0	0
T3	541392	5	0	0
T4	561136	6	0	0
T5	932812	4	0	0
T6	2062356	3	0	0
T8	0	2	0	0
T15	0	7	0	0
T16	0	2	0	0
T19	259736	2	0	0
T20	22632	0	0	0
T21	1388616	3	0	0
T22	343528	2	0	0
T23	309908	4	0	0
T34	0	1	0	0
T35	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T60	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4499	0	0
T2	892510	1	0	0
T3	406044	30	0	0
T4	561136	8	0	0
T5	932812	0	0	0
T6	2062356	0	0	0
T7	19374	0	0	0
T15	0	1	0	0
T19	194802	0	0	0
T20	22632	0	0	0
T21	1388616	0	0	0
T22	343528	2	0	0
T23	309908	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T38	0	11	0	0
T40	0	3	0	0
T42	0	1	0	0
T54	71316	0	0	0
T55	54012	1	0	0
T60	0	1	0	0
T78	0	1	0	0
T94	0	179	0	0
T95	0	1	0	0
T96	0	3	0	0
T97	0	10	0	0
T98	0	4	0	0
T99	0	2	0	0
T100	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	533032	0	0
T2	892510	8	0	0
T3	406044	6529	0	0
T4	561136	1667	0	0
T5	932812	0	0	0
T6	2062356	0	0	0
T7	19374	0	0	0
T15	0	167	0	0
T19	194802	0	0	0
T20	22632	0	0	0
T21	1388616	0	0	0
T22	343528	124	0	0
T23	309908	0	0	0
T34	0	258	0	0
T35	0	42	0	0
T36	0	462	0	0
T38	0	667	0	0
T40	0	367	0	0
T42	0	155	0	0
T54	71316	0	0	0
T55	54012	183	0	0
T60	0	74	0	0
T61	0	6	0	0
T78	0	136	0	0
T94	0	22506	0	0
T95	0	52	0	0
T96	0	289	0	0
T97	0	438	0	0
T98	0	292	0	0
T100	0	686	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4072	0	0
T3	135348	29	0	0
T4	280568	5	0	0
T5	466406	0	0	0
T6	1031178	0	0	0
T7	19374	0	0	0
T8	421192	0	0	0
T15	282559	1	0	0
T19	64934	0	0	0
T20	11316	0	0	0
T21	694308	0	0	0
T22	171764	2	0	0
T23	154954	0	0	0
T34	0	1	0	0
T35	70559	1	0	0
T36	0	1	0	0
T38	0	11	0	0
T40	0	3	0	0
T42	0	1	0	0
T54	71316	0	0	0
T55	54012	1	0	0
T57	117146	0	0	0
T58	35232	0	0	0
T60	304909	1	0	0
T78	0	1	0	0
T94	792131	174	0	0
T96	16203	3	0	0
T97	0	12	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	4	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	141539	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	293	0	0
T3	135348	1	0	0
T4	561136	3	0	0
T5	932812	0	0	0
T6	2062356	0	0	0
T7	58122	0	0	0
T19	64934	0	0	0
T20	22632	0	0	0
T21	1388616	0	0	0
T22	343528	0	0	0
T23	309908	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T54	142632	0	0	0
T55	162036	0	0	0
T62	0	3	0	0
T69	0	1	0	0
T89	0	1	0	0
T94	0	5	0	0
T95	0	1	0	0
T98	0	3	0	0
T100	0	2	0	0
T101	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	7	0	0
T111	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6526	0	0
T11	131196	1385	0	0
T12	0	1470	0	0
T13	0	718	0	0
T43	0	1500	0	0
T44	0	1453	0	0
T45	16256	0	0	0
T46	22668	0	0	0
T47	14320	0	0	0
T48	190080	0	0	0
T49	345148	0	0	0
T50	138252	0	0	0
T51	495704	0	0	0
T52	2621940	0	0	0
T53	3915964	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5446	0	0
T11	131196	1145	0	0
T12	0	1230	0	0
T13	0	598	0	0
T43	0	1260	0	0
T44	0	1213	0	0
T45	16256	0	0	0
T46	22668	0	0	0
T47	14320	0	0	0
T48	190080	0	0	0
T49	345148	0	0	0
T50	138252	0	0	0
T51	495704	0	0	0
T52	2621940	0	0	0
T53	3915964	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	502812	502788	0	0
T2	1785020	1785000	0	0
T3	541392	541344	0	0
T4	561136	560972	0	0
T5	932812	932792	0	0
T19	259736	259440	0	0
T20	22632	22412	0	0
T21	1388616	1388356	0	0
T22	343528	343320	0	0
T23	309908	309552	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T21

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T21,T54,T56
1	1	0	Covered	T2,T4,T20
1	1	1	Covered	T3,T4,T94

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T94
0	1	Covered	T4,T36,T98
1	0	Covered	T64,T66,T68

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T94
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T64,T66,T68

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T94
1	0	Not Covered
1	1	Covered	T4,T36,T98

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T3,T56,T58

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T23
1	Covered	T2,T4,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T54,T40,T113

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T23,T59

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T21,T54

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T94
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T36,T98
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T94
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T94
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T67,T114,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T116,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T73,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T118,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T15,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	758595158	331	0	0
CheckAccumTrig0_A	758595158	525	0	0
CheckAccumTrig1_A	758595158	27	0	0
CheckClr_A	758595158	237	0	0
CheckEn_A	758325757	359405200	0	0
CheckPhase0_A	758595158	626	0	0
CheckPhase1_A	758595158	615	0	0
CheckPhase2_A	758595158	607	0	0
CheckPhase3_A	758595158	597	0	0
CheckTimeout0_A	758595158	1149	0	0
CheckTimeoutSt1_A	758595158	154039	0	0
CheckTimeoutSt2_A	758595158	1045	0	0
CheckTimeoutStTrig_A	758595158	77	0	0
ErrorStAllEscAsserted_A	758595158	1661	0	0
ErrorStIsTerminal_A	758595158	1391	0	0
u_state_regs_A	758595158	758407872	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	331	0	0
T11	32799	85	0	0
T12	0	75	0	0
T13	0	22	0	0
T43	0	78	0	0
T44	0	71	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	525	0	0
T2	446255	1	0	0
T3	135348	2	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	8	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	27	0	0
T64	94362	1	0	0
T66	236702	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T86	38613	0	0	0
T87	826126	0	0	0
T88	278244	0	0	0
T89	27800	0	0	0
T90	76241	0	0	0
T91	86983	0	0	0
T92	9051	0	0	0
T93	286912	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	237	0	0
T3	135348	2	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T9	0	1	0	0
T15	0	7	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	2	0	0
T39	0	7	0	0
T40	0	1	0	0
T42	0	1	0	0
T54	35658	0	0	0
T58	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758325757	359405200	0	0
T1	125703	123147	0	0
T2	446255	15570	0	0
T3	135348	846450	0	0
T4	140284	164426	0	0
T5	233203	233198	0	0
T19	64934	64859	0	0
T20	5658	5602	0	0
T21	347154	13407	0	0
T22	85882	85829	0	0
T23	77477	9317	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	626	0	0
T2	446255	1	0	0
T3	135348	2	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	8	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	615	0	0
T2	446255	1	0	0
T3	135348	2	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	8	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	607	0	0
T2	446255	1	0	0
T3	135348	2	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	8	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	597	0	0
T2	446255	1	0	0
T3	135348	2	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	6	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1149	0	0
T3	135348	29	0	0
T4	140284	2	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	2	0	0
T38	0	10	0	0
T40	0	2	0	0
T42	0	1	0	0
T54	35658	0	0	0
T94	0	87	0	0
T97	0	6	0	0
T98	0	1	0	0
T100	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	154039	0	0
T3	135348	6267	0	0
T4	140284	234	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	462	0	0
T38	0	622	0	0
T40	0	346	0	0
T42	0	155	0	0
T54	35658	0	0	0
T94	0	11025	0	0
T97	0	260	0	0
T98	0	125	0	0
T100	0	686	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1045	0	0
T3	135348	29	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	1	0	0
T38	0	10	0	0
T40	0	2	0	0
T42	0	1	0	0
T54	35658	0	0	0
T94	0	87	0	0
T97	0	6	0	0
T100	0	2	0	0
T102	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	77	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	1	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T69	0	1	0	0
T98	0	1	0	0
T100	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1661	0	0
T11	32799	325	0	0
T12	0	393	0	0
T13	0	174	0	0
T43	0	387	0	0
T44	0	382	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1391	0	0
T11	32799	265	0	0
T12	0	333	0	0
T13	0	144	0	0
T43	0	327	0	0
T44	0	322	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	758407872	0	0
T1	125703	125697	0	0
T2	446255	446250	0	0
T3	135348	135336	0	0
T4	140284	140243	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	347089	0	0
T22	85882	85830	0	0
T23	77477	77388	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T21,T23

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T3,T21,T23
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T2,T3,T35

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T35
0	1	Covered	T3,T94,T98
1	0	Covered	T2,T35,T100

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T35
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T35,T100

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T35
1	0	Not Covered
1	1	Covered	T3,T94,T98

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T23,T6
1	Covered	T2,T4,T21

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T3,T16,T17

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T23,T6,T58

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T35,T57,T103

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T21,T23,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T21,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T23
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T35
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T35
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T35
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T35,T15,T60
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T39,T120,T121
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T42,T122,T62
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T38,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T38,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T35,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	758595158	322	0	0
CheckAccumTrig0_A	758595158	547	0	0
CheckAccumTrig1_A	758595158	27	0	0
CheckClr_A	758595158	271	0	0
CheckEn_A	758325757	331460193	0	0
CheckPhase0_A	758595158	633	0	0
CheckPhase1_A	758595158	623	0	0
CheckPhase2_A	758595158	614	0	0
CheckPhase3_A	758595158	598	0	0
CheckTimeout0_A	758595158	1083	0	0
CheckTimeoutSt1_A	758595158	113345	0	0
CheckTimeoutSt2_A	758595158	990	0	0
CheckTimeoutStTrig_A	758595158	66	0	0
ErrorStAllEscAsserted_A	758595158	1611	0	0
ErrorStIsTerminal_A	758595158	1341	0	0
u_state_regs_A	758595158	758407872	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	322	0	0
T11	32799	59	0	0
T12	0	73	0	0
T13	0	38	0	0
T43	0	89	0	0
T44	0	63	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	547	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2	0	0
T7	19374	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	0	2	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	27	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T35	0	1	0	0
T67	0	2	0	0
T70	0	1	0	0
T101	0	1	0	0
T107	0	1	0	0
T112	0	1	0	0
T123	0	3	0	0
T124	0	1	0	0
T125	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	271	0	0
T6	515589	1	0	0
T7	19374	0	0	0
T8	421192	0	0	0
T15	282559	0	0	0
T35	70559	2	0	0
T36	0	1	0	0
T38	0	7	0	0
T39	0	18	0	0
T41	0	3	0	0
T42	0	1	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T56	3439	0	0	0
T57	117146	0	0	0
T58	35232	1	0	0
T60	0	1	0	0
T94	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758325757	331460193	0	0
T1	125703	125697	0	0
T2	446255	3062	0	0
T3	135348	859014	0	0
T4	140284	164430	0	0
T5	233203	233198	0	0
T19	64934	64859	0	0
T20	5658	5602	0	0
T21	347154	1991	0	0
T22	85882	85829	0	0
T23	77477	15019	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	633	0	0
T2	446255	1	0	0
T3	135348	1	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	623	0	0
T2	446255	1	0	0
T3	135348	1	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	614	0	0
T2	446255	1	0	0
T3	135348	1	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	598	0	0
T2	446255	1	0	0
T3	135348	1	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	2	0	0
T16	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1083	0	0
T2	446255	1	0	0
T3	135348	1	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T60	0	1	0	0
T94	0	48	0	0
T97	0	4	0	0
T98	0	3	0	0
T99	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	113345	0	0
T2	446255	8	0	0
T3	135348	262	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T15	0	167	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T35	0	42	0	0
T38	0	45	0	0
T60	0	74	0	0
T94	0	5819	0	0
T97	0	178	0	0
T98	0	167	0	0
T99	0	371	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	990	0	0
T8	421192	0	0	0
T15	282559	1	0	0
T35	70559	1	0	0
T38	0	1	0	0
T57	117146	0	0	0
T58	35232	0	0	0
T60	304909	1	0	0
T94	792131	45	0	0
T96	16203	0	0	0
T97	0	4	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	1	0	0
T103	141539	0	0	0
T126	367484	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	66	0	0
T3	135348	1	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T54	35658	0	0	0
T62	0	2	0	0
T70	0	6	0	0
T94	0	3	0	0
T98	0	2	0	0
T104	0	1	0	0
T105	0	1	0	0
T110	0	6	0	0
T118	0	1	0	0
T127	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1611	0	0
T11	32799	364	0	0
T12	0	360	0	0
T13	0	178	0	0
T43	0	369	0	0
T44	0	340	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1341	0	0
T11	32799	304	0	0
T12	0	300	0	0
T13	0	148	0	0
T43	0	309	0	0
T44	0	280	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	758407872	0	0
T1	125703	125697	0	0
T2	446255	446250	0	0
T3	135348	135336	0	0
T4	140284	140243	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	347089	0	0
T22	85882	85830	0	0
T23	77477	77388	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T5,T23

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T54,T57
1	1	0	Covered	T3,T4,T35
1	1	1	Covered	T2,T3,T4

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T96,T94
1	0	Covered	T2,T60,T42

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T60,T42

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T4,T96,T94

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T21,T5,T6
1	Covered	T2,T4,T23

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T96,T94,T103

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T21
1	Covered	T6,T8,T58

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T23
1	Covered	T21,T5,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T21,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T23,T60,T94

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T5,T23
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T68,T128,T129
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T130,T114
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T120,T69,T121
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T131,T68,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T8,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	758595158	304	0	0
CheckAccumTrig0_A	758595158	592	0	0
CheckAccumTrig1_A	758595158	32	0	0
CheckClr_A	758595158	289	0	0
CheckEn_A	758325757	332957220	0	0
CheckPhase0_A	758595158	703	0	0
CheckPhase1_A	758595158	694	0	0
CheckPhase2_A	758595158	680	0	0
CheckPhase3_A	758595158	672	0	0
CheckTimeout0_A	758595158	1358	0	0
CheckTimeoutSt1_A	758595158	157127	0	0
CheckTimeoutSt2_A	758595158	1242	0	0
CheckTimeoutStTrig_A	758595158	84	0	0
ErrorStAllEscAsserted_A	758595158	1609	0	0
ErrorStIsTerminal_A	758595158	1339	0	0
u_state_regs_A	758595158	758407872	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	304	0	0
T11	32799	63	0	0
T12	0	73	0	0
T13	0	42	0	0
T43	0	58	0	0
T44	0	68	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	592	0	0
T5	233203	1	0	0
T6	515589	1	0	0
T7	19374	0	0	0
T8	0	2	0	0
T15	0	1	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T35	70559	0	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T56	3439	0	0	0
T58	0	2	0	0
T60	0	2	0	0
T94	0	6	0	0
T103	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	32	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	0	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T42	0	1	0	0
T49	0	2	0	0
T60	0	1	0	0
T62	0	1	0	0
T69	0	1	0	0
T98	0	1	0	0
T101	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	289	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T8	0	1	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T35	70559	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T56	3439	0	0	0
T58	0	1	0	0
T60	0	1	0	0
T94	0	3	0	0
T113	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758325757	332957220	0	0
T1	125703	336016	0	0
T2	446255	8332	0	0
T3	135348	131966	0	0
T4	140284	154938	0	0
T5	233203	3380	0	0
T19	64934	64859	0	0
T20	5658	2668	0	0
T21	347154	334028	0	0
T22	85882	85829	0	0
T23	77477	3088	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	703	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	1	0	0
T6	515589	1	0	0
T8	0	2	0	0
T15	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T58	0	2	0	0
T60	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	694	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	1	0	0
T6	515589	1	0	0
T8	0	2	0	0
T15	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T58	0	2	0	0
T60	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	680	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	1	0	0
T6	515589	1	0	0
T8	0	2	0	0
T15	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T58	0	2	0	0
T60	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	672	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	1	0	0
T6	515589	1	0	0
T8	0	2	0	0
T15	0	1	0	0
T19	64934	0	0	0
T20	5658	0	0	0
T21	347154	1	0	0
T22	85882	0	0	0
T23	77477	1	0	0
T58	0	2	0	0
T60	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1358	0	0
T2	446255	2	0	0
T3	135348	3	0	0
T4	140284	2	0	0
T5	233203	8	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	1	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	1	0	0
T42	0	1	0	0
T60	0	3	0	0
T94	0	56	0	0
T96	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	157127	0	0
T2	446255	34	0	0
T3	135348	952	0	0
T4	140284	353	0	0
T5	233203	837	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	199	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	7	0	0
T42	0	4	0	0
T60	0	509	0	0
T94	0	6589	0	0
T96	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1242	0	0
T2	446255	1	0	0
T3	135348	3	0	0
T4	140284	1	0	0
T5	233203	8	0	0
T6	515589	0	0	0
T19	64934	0	0	0
T20	5658	1	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T36	0	1	0	0
T60	0	2	0	0
T94	0	55	0	0
T96	0	1	0	0
T97	0	12	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	84	0	0
T4	140284	1	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T38	0	2	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T62	0	1	0	0
T94	0	1	0	0
T96	0	1	0	0
T98	0	1	0	0
T107	0	1	0	0
T109	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1609	0	0
T11	32799	348	0	0
T12	0	345	0	0
T13	0	191	0	0
T43	0	381	0	0
T44	0	344	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1339	0	0
T11	32799	288	0	0
T12	0	285	0	0
T13	0	161	0	0
T43	0	321	0	0
T44	0	284	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	758407872	0	0
T1	125703	125697	0	0
T2	446255	446250	0	0
T3	135348	135336	0	0
T4	140284	140243	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	347089	0	0
T22	85882	85830	0	0
T23	77477	77388	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T33
1	1	1	Covered	T2,T3,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T3,T19,T4
1	1	0	Covered	T3,T20,T55
1	1	1	Covered	T4,T22,T55

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T22,T55
0	1	Covered	T4,T34,T95
1	0	Covered	T36,T61,T101

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T22,T55
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T61,T101

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T55
1	0	Covered	T37
1	1	Covered	T4,T34,T95

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T3,T4,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T2,T23,T34

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T4,T55,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T19,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T19,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14
IdleSt	176	Covered	T14
Phase0St	147	Covered	T14
Phase1St	193	Covered	T14
Phase2St	210	Covered	T14
Phase3St	228	Covered	T14
TerminalSt	244	Covered	T14
TimeoutSt	154	Covered	T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14
IdleSt->Phase0St	147	Covered	T14
IdleSt->TimeoutSt	154	Covered	T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T14
Phase0St->Phase1St	193	Covered	T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14
Phase1St->Phase2St	210	Covered	T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14
Phase2St->Phase3St	228	Covered	T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14
Phase3St->TerminalSt	244	Covered	T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14
TimeoutSt->Phase0St	167	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T22,T55
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T34,T95
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T22,T55
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T22,T55
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T38,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T41,T63,T136
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T137,T138,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T139,T140,T69
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	758595158	336	0	0
CheckAccumTrig0_A	758595158	933	0	0
CheckAccumTrig1_A	758595158	48	0	0
CheckClr_A	758595158	433	0	0
CheckEn_A	758325757	290067825	0	0
CheckPhase0_A	758595158	1029	0	0
CheckPhase1_A	758595158	1012	0	0
CheckPhase2_A	758595158	997	0	0
CheckPhase3_A	758595158	986	0	0
CheckTimeout0_A	758595158	909	0	0
CheckTimeoutSt1_A	758595158	108521	0	0
CheckTimeoutSt2_A	758595158	795	0	0
CheckTimeoutStTrig_A	758595158	66	0	0
ErrorStAllEscAsserted_A	758595158	1645	0	0
ErrorStIsTerminal_A	758595158	1375	0	0
u_state_regs_A	758595158	758407872	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	336	0	0
T11	32799	58	0	0
T12	0	82	0	0
T13	0	43	0	0
T43	0	86	0	0
T44	0	67	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	933	0	0
T2	446255	2	0	0
T3	135348	2	0	0
T4	140284	2	0	0
T5	233203	3	0	0
T6	515589	0	0	0
T16	0	4	0	0
T19	64934	2	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	48	0	0
T36	114384	1	0	0
T48	0	1	0	0
T61	107282	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T65	0	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T78	35953	0	0	0
T79	22774	0	0	0
T80	2068	0	0	0
T81	333254	0	0	0
T82	164621	0	0	0
T83	1369	0	0	0
T84	285611	0	0	0
T85	460170	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	433	0	0
T2	446255	1	0	0
T3	135348	0	0	0
T4	140284	1	0	0
T5	233203	2	0	0
T6	515589	0	0	0
T16	0	3	0	0
T18	0	1	0	0
T19	64934	1	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	1	0	0
T23	77477	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T94	0	7	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758325757	290067825	0	0
T1	125703	120992	0	0
T2	446255	3026	0	0
T3	135348	680188	0	0
T4	140284	9567	0	0
T5	233203	3311	0	0
T19	64934	3050	0	0
T20	5658	5602	0	0
T21	347154	323820	0	0
T22	85882	3123	0	0
T23	77477	9299	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1029	0	0
T2	446255	2	0	0
T3	135348	2	0	0
T4	140284	3	0	0
T5	233203	3	0	0
T6	515589	0	0	0
T19	64934	2	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	1	0	0
T34	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1012	0	0
T2	446255	2	0	0
T3	135348	2	0	0
T4	140284	3	0	0
T5	233203	3	0	0
T6	515589	0	0	0
T19	64934	2	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	1	0	0
T34	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	997	0	0
T2	446255	2	0	0
T3	135348	2	0	0
T4	140284	3	0	0
T5	233203	3	0	0
T6	515589	0	0	0
T19	64934	2	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	1	0	0
T34	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	986	0	0
T2	446255	2	0	0
T3	135348	2	0	0
T4	140284	3	0	0
T5	233203	3	0	0
T6	515589	0	0	0
T19	64934	2	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	1	0	0
T34	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	909	0	0
T4	140284	6	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T40	0	1	0	0
T54	35658	0	0	0
T55	54012	1	0	0
T78	0	1	0	0
T94	0	44	0	0
T95	0	1	0	0
T96	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	108521	0	0
T4	140284	1433	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	124	0	0
T23	77477	0	0	0
T34	0	258	0	0
T40	0	21	0	0
T54	35658	0	0	0
T55	54012	183	0	0
T61	0	6	0	0
T78	0	136	0	0
T94	0	5662	0	0
T95	0	52	0	0
T96	0	289	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	795	0	0
T4	140284	4	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	2	0	0
T23	77477	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T54	35658	0	0	0
T55	54012	1	0	0
T78	0	1	0	0
T94	0	42	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	66	0	0
T4	140284	2	0	0
T5	233203	0	0	0
T6	515589	0	0	0
T7	19374	0	0	0
T20	5658	0	0	0
T21	347154	0	0	0
T22	85882	0	0	0
T23	77477	0	0	0
T34	0	1	0	0
T54	35658	0	0	0
T55	54012	0	0	0
T62	0	1	0	0
T89	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1645	0	0
T11	32799	348	0	0
T12	0	372	0	0
T13	0	175	0	0
T43	0	363	0	0
T44	0	387	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	1375	0	0
T11	32799	288	0	0
T12	0	312	0	0
T13	0	145	0	0
T43	0	303	0	0
T44	0	327	0	0
T45	4064	0	0	0
T46	5667	0	0	0
T47	3580	0	0	0
T48	47520	0	0	0
T49	86287	0	0	0
T50	34563	0	0	0
T51	123926	0	0	0
T52	655485	0	0	0
T53	978991	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758595158	758407872	0	0
T1	125703	125697	0	0
T2	446255	446250	0	0
T3	135348	135336	0	0
T4	140284	140243	0	0
T5	233203	233198	0	0
T19	64934	64860	0	0
T20	5658	5603	0	0
T21	347154	347089	0	0
T22	85882	85830	0	0
T23	77477	77388	0	0