Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99,T89,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13872	0	0
DisabledNoTrigBkwd_A	2147483647	738311	0	0
DisabledNoTrigFwd_A	2147483647	1536357011	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13872	0	0
T55	416743	0	0	0
T79	184346	0	0	0
T80	534548	0	0	0
T89	3024	627	0	0
T90	6443	0	0	0
T91	128006	0	0	0
T92	35930	0	0	0
T93	450863	0	0	0
T94	246582	0	0	0
T99	0	933	0	0
T195	3061	563	0	0
T196	0	349	0	0
T197	0	696	0	0
T198	0	732	0	0
T199	0	1177	0	0
T200	0	954	0	0
T201	0	599	0	0
T202	1222	508	0	0
T203	0	338	0	0
T204	0	818	0	0
T205	0	807	0	0
T206	0	595	0	0
T207	0	613	0	0
T208	0	560	0	0
T209	0	754	0	0
T210	0	175	0	0
T211	0	1192	0	0
T212	0	882	0	0
T213	27921	0	0	0
T214	67761	0	0	0
T215	286250	0	0	0
T216	541300	0	0	0
T217	263549	0	0	0
T218	7153	0	0	0
T219	433379	0	0	0
T220	392925	0	0	0
T221	33306	0	0	0
T222	183501	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	738311	0	0
T1	378816	1938	0	0
T2	3920804	619	0	0
T3	593988	109	0	0
T4	572288	814	0	0
T5	874692	1	0	0
T6	0	1683	0	0
T7	0	4341	0	0
T13	0	20	0	0
T16	0	18537	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	6	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	0	0	0
T26	0	800	0	0
T27	0	276	0	0
T28	0	804	0	0
T29	0	39	0	0
T32	0	9	0	0
T33	0	68	0	0
T34	0	38	0	0
T49	0	7	0	0
T50	0	112	0	0
T51	0	104	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1536357011	0	0
T1	505088	379168	0	0
T2	3920804	2360401	0	0
T3	593988	434168	0	0
T4	572288	149438	0	0
T18	51152	28109	0	0
T19	82500	82188	0	0
T20	27388	18091	0	0
T21	40844	21444	0	0
T22	89176	70831	0	0
T23	199804	108283	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662815529	508	0	0
DisabledNoTrigBkwd_A	662815529	207912	0	0
DisabledNoTrigFwd_A	662815529	362968503	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	508	0	0
T202	1222	508	0	0
T214	67761	0	0	0
T215	286250	0	0	0
T216	541300	0	0	0
T217	263549	0	0	0
T218	7153	0	0	0
T219	433379	0	0	0
T220	392925	0	0	0
T221	33306	0	0	0
T222	183501	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	207912	0	0
T1	126272	12	0	0
T2	980201	358	0	0
T3	148497	0	0	0
T4	143072	399	0	0
T6	0	406	0	0
T7	0	1001	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T26	0	800	0	0
T29	0	39	0	0
T33	0	68	0	0
T50	0	112	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	362968503	0	0
T1	126272	125310	0	0
T2	980201	20965	0	0
T3	148497	142522	0	0
T4	143072	1901	0	0
T18	12788	6095	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	582	0	0
T22	22294	22197	0	0
T23	49951	27245	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89,T198,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662815529	4650	0	0
DisabledNoTrigBkwd_A	662815529	169024	0	0
DisabledNoTrigFwd_A	662815529	388031252	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	4650	0	0
T55	416743	0	0	0
T79	184346	0	0	0
T80	534548	0	0	0
T89	3024	627	0	0
T90	6443	0	0	0
T91	128006	0	0	0
T92	35930	0	0	0
T93	450863	0	0	0
T94	246582	0	0	0
T198	0	732	0	0
T200	0	954	0	0
T203	0	338	0	0
T205	0	807	0	0
T211	0	1192	0	0
T213	27921	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	169024	0	0
T2	980201	261	0	0
T3	148497	109	0	0
T4	143072	415	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	20	0	0
T16	0	15988	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	10	0	0
T32	0	3	0	0
T34	0	38	0	0
T49	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	388031252	0	0
T1	126272	126146	0	0
T2	980201	397705	0	0
T3	148497	586	0	0
T4	143072	4009	0	0
T18	12788	11694	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	586	0	0
T22	22294	20663	0	0
T23	49951	33756	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T196,T197
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662815529	5449	0	0
DisabledNoTrigBkwd_A	662815529	183002	0	0
DisabledNoTrigFwd_A	662815529	370122959	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	5449	0	0
T102	538829	0	0	0
T110	307239	0	0	0
T121	434992	0	0	0
T195	3061	563	0	0
T196	2762	349	0	0
T197	0	696	0	0
T201	0	599	0	0
T204	0	818	0	0
T207	0	613	0	0
T209	0	754	0	0
T210	0	175	0	0
T212	0	882	0	0
T223	27823	0	0	0
T224	172275	0	0	0
T225	826024	0	0	0
T226	182259	0	0	0
T227	480094	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	183002	0	0
T1	126272	1926	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1276	0	0
T7	0	3340	0	0
T16	0	2549	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	6	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T27	0	276	0	0
T28	0	794	0	0
T32	0	6	0	0
T51	0	104	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	370122959	0	0
T1	126272	1763	0	0
T2	980201	967380	0	0
T3	148497	145530	0	0
T4	143072	142934	0	0
T18	12788	8699	0	0
T19	20625	20547	0	0
T20	6847	2909	0	0
T21	10211	10138	0	0
T22	22294	9239	0	0
T23	49951	37990	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99,T199,T206
1	1	Covered	T1,T3,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662815529	3265	0	0
DisabledNoTrigBkwd_A	662815529	178373	0	0
DisabledNoTrigFwd_A	662815529	415234297	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	3265	0	0
T17	667350	0	0	0
T27	136342	0	0	0
T51	72886	0	0	0
T52	10692	0	0	0
T68	391978	0	0	0
T72	8871	0	0	0
T73	73589	0	0	0
T99	1740	933	0	0
T106	387915	0	0	0
T199	0	1177	0	0
T206	0	595	0	0
T208	0	560	0	0
T228	76154	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	178373	0	0
T1	126272	3	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	393	0	0
T6	0	717	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T26	0	102	0	0
T27	0	59	0	0
T32	0	5	0	0
T49	0	8	0	0
T51	0	36	0	0
T99	0	24	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	415234297	0	0
T1	126272	125949	0	0
T2	980201	974351	0	0
T3	148497	145530	0	0
T4	143072	594	0	0
T18	12788	1621	0	0
T19	20625	20547	0	0
T20	6847	1596	0	0
T21	10211	10138	0	0
T22	22294	18732	0	0
T23	49951	9292	0	0