Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24,T25
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T20,T21
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T21,T22,T23
1	1	1	Covered	T20,T21,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T23,T26,T27
1	0	Covered	T28,T7,T29

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T21,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T7,T29

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T30,T31
1	1	Covered	T23,T26,T27

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T3,T20

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T32,T29

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T7,T33

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T20,T21,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T20,T21,T22
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T1,T26,T34
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T28,T7,T26
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T29,T16,T27
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T7,T35,T36
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T2,T18
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T21,T22,T23
TimeoutSt->Phase0St	167	Covered	T23,T28,T7

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T28,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T34,T37
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T7,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T16,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T35,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1262	0	0
CheckAccumTrig0_A	2147483647	2282	0	0
CheckAccumTrig1_A	2147483647	140	0	0
CheckClr_A	2147483647	1059	0	0
CheckEn_A	2147483647	1162191105	0	0
CheckPhase0_A	2147483647	2632	0	0
CheckPhase1_A	2147483647	2576	0	0
CheckPhase2_A	2147483647	2530	0	0
CheckPhase3_A	2147483647	2478	0	0
CheckTimeout0_A	2147483647	3034	0	0
CheckTimeoutSt1_A	2147483647	386466	0	0
CheckTimeoutSt2_A	2147483647	2619	0	0
CheckTimeoutStTrig_A	2147483647	271	0	0
ErrorStAllEscAsserted_A	2147483647	6490	0	0
ErrorStIsTerminal_A	2147483647	5410	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1262	0	0
T10	65952	129	0	0
T11	0	270	0	0
T12	0	302	0	0
T38	0	235	0	0
T39	0	326	0	0
T40	110772	0	0	0
T41	16932	0	0	0
T42	1793608	0	0	0
T43	885752	0	0	0
T44	168712	0	0	0
T45	106640	0	0	0
T46	580124	0	0	0
T47	21132	0	0	0
T48	3406828	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T1	378816	9	0	0
T2	3920804	6	0	0
T3	593988	1	0	0
T4	572288	2	0	0
T5	874692	1	0	0
T6	0	3	0	0
T7	0	8	0	0
T13	0	1	0	0
T16	0	4	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	1	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	0	0	0
T26	0	7	0	0
T27	0	4	0	0
T28	0	1	0	0
T29	0	5	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	3	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	140	0	0
T4	143072	0	0	0
T5	874692	0	0	0
T6	144524	0	0	0
T7	1156140	1	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T24	0	2	0	0
T26	555111	0	0	0
T27	0	1	0	0
T28	2612526	2	0	0
T29	157740	1	0	0
T32	165492	0	0	0
T33	126480	0	0	0
T34	268044	0	0	0
T36	0	1	0	0
T42	0	1	0	0
T49	140946	0	0	0
T50	280185	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	26596	0	0	0
T67	226707	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1059	0	0
T1	378816	7	0	0
T2	2940603	1	0	0
T3	445491	0	0	0
T4	429216	0	0	0
T6	0	1	0	0
T7	289035	7	0	0
T9	0	2	0	0
T18	38364	1	0	0
T19	61875	0	0	0
T20	20541	0	0	0
T21	30633	0	0	0
T22	66882	0	0	0
T23	149853	1	0	0
T26	185037	4	0	0
T27	0	11	0	0
T28	870842	1	0	0
T29	52580	5	0	0
T32	55164	0	0	0
T33	31620	1	0	0
T34	89348	2	0	0
T35	0	2	0	0
T49	46982	1	0	0
T50	93395	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T67	75569	0	0	0
T68	0	5	0	0
T69	0	3	0	0
T70	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1162191105	0	0
T1	505088	257503	0	0
T2	3920804	2360383	0	0
T3	593988	434165	0	0
T4	572288	149438	0	0
T18	51152	28106	0	0
T19	82500	82184	0	0
T20	27388	18089	0	0
T21	40844	21442	0	0
T22	89176	70829	0	0
T23	199804	103435	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2632	0	0
T1	378816	8	0	0
T2	3920804	6	0	0
T3	593988	1	0	0
T4	572288	2	0	0
T5	874692	1	0	0
T6	0	2	0	0
T7	0	9	0	0
T13	0	1	0	0
T16	0	4	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	1	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	2	0	0
T26	0	7	0	0
T28	0	3	0	0
T29	0	6	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576	0	0
T1	378816	8	0	0
T2	3920804	6	0	0
T3	593988	1	0	0
T4	572288	2	0	0
T5	874692	1	0	0
T6	0	2	0	0
T7	0	8	0	0
T13	0	1	0	0
T16	0	4	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	1	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	2	0	0
T26	0	5	0	0
T28	0	2	0	0
T29	0	6	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2530	0	0
T1	378816	8	0	0
T2	3920804	6	0	0
T3	593988	1	0	0
T4	572288	2	0	0
T5	874692	1	0	0
T6	0	2	0	0
T7	0	8	0	0
T13	0	1	0	0
T16	0	3	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	1	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	2	0	0
T26	0	5	0	0
T28	0	2	0	0
T29	0	5	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2478	0	0
T1	378816	8	0	0
T2	3920804	6	0	0
T3	593988	1	0	0
T4	572288	2	0	0
T5	874692	1	0	0
T6	0	2	0	0
T7	0	7	0	0
T13	0	1	0	0
T16	0	3	0	0
T18	51152	1	0	0
T19	82500	0	0	0
T20	27388	1	0	0
T21	40844	0	0	0
T22	89176	0	0	0
T23	199804	2	0	0
T26	0	5	0	0
T28	0	2	0	0
T29	0	5	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3034	0	0
T4	143072	0	0	0
T5	3498768	0	0	0
T7	1156140	3	0	0
T16	0	1	0	0
T20	6847	1	0	0
T21	30633	10	0	0
T22	89176	4	0	0
T23	199804	7	0	0
T26	555111	12	0	0
T27	0	18	0	0
T28	3483368	4	0	0
T29	0	2	0	0
T32	55164	1	0	0
T33	126480	0	0	0
T34	0	1	0	0
T49	140946	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T66	106384	1	0	0
T69	0	7	0	0
T71	0	5	0	0
T72	0	3	0	0
T73	0	13	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386466	0	0
T4	143072	0	0	0
T5	3498768	0	0	0
T7	1156140	185	0	0
T16	0	48	0	0
T20	6847	3	0	0
T21	30633	751	0	0
T22	89176	486	0	0
T23	199804	1423	0	0
T26	555111	2902	0	0
T27	0	2937	0	0
T28	3483368	85	0	0
T29	0	60	0	0
T32	55164	52	0	0
T33	126480	0	0	0
T34	0	257	0	0
T49	140946	1565	0	0
T52	0	1304	0	0
T53	0	10	0	0
T66	106384	124	0	0
T69	0	945	0	0
T71	0	936	0	0
T72	0	284	0	0
T73	0	2095	0	0
T74	0	368	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2619	0	0
T5	3498768	0	0	0
T7	1156140	2	0	0
T16	0	1	0	0
T21	20422	10	0	0
T22	89176	3	0	0
T23	199804	3	0	0
T24	0	11	0	0
T26	740148	6	0	0
T27	0	10	0	0
T28	3483368	2	0	0
T29	0	1	0	0
T32	110328	0	0	0
T33	126480	0	0	0
T34	0	1	0	0
T49	187928	0	0	0
T66	106384	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	13	0	0
T74	0	1	0	0
T75	0	7	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271	0	0
T5	2624076	0	0	0
T7	867105	0	0	0
T23	149853	2	0	0
T24	744485	5	0	0
T26	555111	1	0	0
T27	0	3	0	0
T28	2612526	0	0	0
T32	165492	0	0	0
T33	94860	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	140946	0	0	0
T50	280185	0	0	0
T52	0	1	0	0
T55	416743	2	0	0
T66	79788	0	0	0
T69	0	2	0	0
T78	0	1	0	0
T79	184346	2	0	0
T80	0	1	0	0
T81	0	4	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	144702	0	0	0
T89	3024	0	0	0
T90	6443	0	0	0
T91	128006	0	0	0
T92	35930	0	0	0
T93	450863	0	0	0
T94	246582	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6490	0	0
T10	65952	723	0	0
T11	0	1486	0	0
T12	0	1449	0	0
T38	0	1452	0	0
T39	0	1380	0	0
T40	110772	0	0	0
T41	16932	0	0	0
T42	1793608	0	0	0
T43	885752	0	0	0
T44	168712	0	0	0
T45	106640	0	0	0
T46	580124	0	0	0
T47	21132	0	0	0
T48	3406828	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5410	0	0
T10	65952	603	0	0
T11	0	1246	0	0
T12	0	1209	0	0
T38	0	1212	0	0
T39	0	1140	0	0
T40	110772	0	0	0
T41	16932	0	0	0
T42	1793608	0	0	0
T43	885752	0	0	0
T44	168712	0	0	0
T45	106640	0	0	0
T46	580124	0	0	0
T47	21132	0	0	0
T48	3406828	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	505088	505052	0	0
T2	3920804	3918908	0	0
T3	593988	593632	0	0
T4	572288	572264	0	0
T18	51152	50852	0	0
T19	82500	82188	0	0
T20	27388	27172	0	0
T21	40844	40552	0	0
T22	89176	88788	0	0
T23	199804	199428	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T22,T23
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T22,T23,T7
1	1	1	Covered	T21,T23,T28

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T23,T28
0	1	Covered	T24,T55,T81
1	0	Covered	T28,T52,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T23,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T52,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T23,T28
1	0	Not Covered
1	1	Covered	T24,T55,T81

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T28,T49
1	Covered	T3,T4,T28

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T28
1	Covered	T2,T32,T34

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T16,T8,T35

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T49,T34,T6

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T49,T32,T27

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T32,T34,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T28

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T21,T23,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T21,T23,T28
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T34,T83,T84
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T28,T70,T37
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T37,T24,T61
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T24,T95,T96
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T49,T34
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T21,T23,T28
TimeoutSt->Phase0St	167	Covered	T28,T52,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T28,T52,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T97,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T70,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T24,T61
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T95,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T49,T34,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662815529	282	0	0
CheckAccumTrig0_A	662815529	484	0	0
CheckAccumTrig1_A	662815529	31	0	0
CheckClr_A	662815529	216	0	0
CheckEn_A	662568162	291731051	0	0
CheckPhase0_A	662815529	575	0	0
CheckPhase1_A	662815529	560	0	0
CheckPhase2_A	662815529	553	0	0
CheckPhase3_A	662815529	546	0	0
CheckTimeout0_A	662815529	679	0	0
CheckTimeoutSt1_A	662815529	92068	0	0
CheckTimeoutSt2_A	662815529	579	0	0
CheckTimeoutStTrig_A	662815529	68	0	0
ErrorStAllEscAsserted_A	662815529	1581	0	0
ErrorStIsTerminal_A	662815529	1311	0	0
u_state_regs_A	662815529	662627033	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	282	0	0
T10	16488	23	0	0
T11	0	44	0	0
T12	0	79	0	0
T38	0	53	0	0
T39	0	83	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	484	0	0
T2	980201	1	0	0
T3	148497	1	0	0
T4	143072	1	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	1	0	0
T16	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	3	0	0
T49	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	31	0	0
T7	289035	0	0	0
T24	0	2	0	0
T26	185037	0	0	0
T28	870842	1	0	0
T29	52580	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T34	89348	0	0	0
T42	0	1	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T67	75569	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	216	0	0
T6	0	1	0	0
T7	289035	0	0	0
T9	0	2	0	0
T26	185037	0	0	0
T28	870842	1	0	0
T29	52580	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T34	89348	2	0	0
T35	0	1	0	0
T49	46982	1	0	0
T50	93395	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T67	75569	0	0	0
T68	0	5	0	0
T70	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662568162	291731051	0	0
T1	126272	126145	0	0
T2	980201	397700	0	0
T3	148497	586	0	0
T4	143072	4009	0	0
T18	12788	11693	0	0
T19	20625	20546	0	0
T20	6847	6792	0	0
T21	10211	586	0	0
T22	22294	20663	0	0
T23	49951	33756	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	575	0	0
T2	980201	1	0	0
T3	148497	1	0	0
T4	143072	1	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	1	0	0
T16	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T49	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	560	0	0
T2	980201	1	0	0
T3	148497	1	0	0
T4	143072	1	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	1	0	0
T16	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T49	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	553	0	0
T2	980201	1	0	0
T3	148497	1	0	0
T4	143072	1	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	1	0	0
T16	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T49	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	546	0	0
T2	980201	1	0	0
T3	148497	1	0	0
T4	143072	1	0	0
T5	874692	0	0	0
T6	0	1	0	0
T13	0	1	0	0
T16	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T49	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	679	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T16	0	1	0	0
T21	10211	6	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	185037	0	0	0
T27	0	3	0	0
T28	870842	2	0	0
T33	31620	0	0	0
T34	0	1	0	0
T49	46982	0	0	0
T52	0	1	0	0
T66	26596	0	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	92068	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T16	0	48	0	0
T21	10211	448	0	0
T22	22294	0	0	0
T23	49951	320	0	0
T26	185037	0	0	0
T27	0	607	0	0
T28	870842	57	0	0
T33	31620	0	0	0
T34	0	257	0	0
T49	46982	0	0	0
T52	0	6	0	0
T66	26596	0	0	0
T71	0	373	0	0
T72	0	92	0	0
T73	0	1027	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	579	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T16	0	1	0	0
T21	10211	6	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	185037	0	0	0
T27	0	3	0	0
T28	870842	1	0	0
T33	31620	0	0	0
T34	0	1	0	0
T49	46982	0	0	0
T66	26596	0	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	6	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	68	0	0
T24	744485	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T55	416743	2	0	0
T79	184346	0	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	144702	0	0	0
T89	3024	0	0	0
T90	6443	0	0	0
T91	128006	0	0	0
T92	35930	0	0	0
T93	450863	0	0	0
T94	246582	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1581	0	0
T10	16488	167	0	0
T11	0	352	0	0
T12	0	349	0	0
T38	0	376	0	0
T39	0	337	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1311	0	0
T10	16488	137	0	0
T11	0	292	0	0
T12	0	289	0	0
T38	0	316	0	0
T39	0	277	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	662627033	0	0
T1	126272	126263	0	0
T2	980201	979727	0	0
T3	148497	148408	0	0
T4	143072	143066	0	0
T18	12788	12713	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	10138	0	0
T22	22294	22197	0	0
T23	49951	49857	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T49

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T20,T22
1	0	1	Covered	T18,T4,T49
1	1	0	Covered	T21,T22,T28
1	1	1	Covered	T20,T22,T23

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T23
0	1	Covered	T23,T32,T27
1	0	Covered	T20,T81,T86

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T22,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T81,T86

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T23
1	0	Not Covered
1	1	Covered	T23,T32,T27

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T4
1	Covered	T23,T99,T51

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T23
1	Covered	T20,T49,T51

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T23
1	Covered	T4,T49,T32

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T20,T4,T23
1	Covered	T1,T26,T27

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T49,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T23,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T49

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T20,T4
Phase1St	193	Covered	T1,T20,T4
Phase2St	210	Covered	T1,T20,T4
Phase3St	228	Covered	T1,T20,T4
TerminalSt	244	Covered	T1,T20,T4
TimeoutSt	154	Covered	T20,T22,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T4,T49
IdleSt->TimeoutSt	154	Covered	T20,T22,T23
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T81,T84
Phase0St->Phase1St	193	Covered	T1,T20,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T24,T100,T101
Phase1St->Phase2St	210	Covered	T1,T20,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T24,T102,T61
Phase2St->Phase3St	228	Covered	T1,T20,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T103,T95,T104
Phase3St->TerminalSt	244	Covered	T1,T20,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T23,T49
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T22,T23,T49
TimeoutSt->Phase0St	167	Covered	T20,T23,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T49
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T23,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T49
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T81,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T20,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T20,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T100,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T20,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T20,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T102,T61
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T20,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T20,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T103,T95,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T20,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T20,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T23,T49
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T20,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662815529	298	0	0
CheckAccumTrig0_A	662815529	459	0	0
CheckAccumTrig1_A	662815529	26	0	0
CheckClr_A	662815529	201	0	0
CheckEn_A	662568162	324501606	0	0
CheckPhase0_A	662815529	549	0	0
CheckPhase1_A	662815529	542	0	0
CheckPhase2_A	662815529	528	0	0
CheckPhase3_A	662815529	517	0	0
CheckTimeout0_A	662815529	889	0	0
CheckTimeoutSt1_A	662815529	106252	0	0
CheckTimeoutSt2_A	662815529	791	0	0
CheckTimeoutStTrig_A	662815529	72	0	0
ErrorStAllEscAsserted_A	662815529	1622	0	0
ErrorStIsTerminal_A	662815529	1352	0	0
u_state_regs_A	662815529	662627033	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	298	0	0
T10	16488	34	0	0
T11	0	69	0	0
T12	0	78	0	0
T38	0	62	0	0
T39	0	55	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	459	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T99	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	26	0	0
T4	143072	0	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T28	870842	0	0	0
T33	31620	0	0	0
T64	0	1	0	0
T66	26596	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T95	0	1	0	0
T97	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	201	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T9	0	2	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T24	0	8	0	0
T35	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T69	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662568162	324501606	0	0
T1	126272	125949	0	0
T2	980201	974345	0	0
T3	148497	145529	0	0
T4	143072	594	0	0
T18	12788	1621	0	0
T19	20625	20546	0	0
T20	6847	1596	0	0
T21	10211	10137	0	0
T22	22294	18731	0	0
T23	49951	9292	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	549	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T99	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	542	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T99	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	528	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T99	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	517	0	0
T1	126272	1	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T99	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	889	0	0
T4	143072	0	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	1	0	0
T23	49951	2	0	0
T26	0	5	0	0
T27	0	4	0	0
T28	870842	0	0	0
T32	0	1	0	0
T33	31620	0	0	0
T49	0	2	0	0
T52	0	1	0	0
T66	26596	0	0	0
T69	0	2	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	106252	0	0
T4	143072	0	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T20	6847	3	0	0
T21	10211	0	0	0
T22	22294	100	0	0
T23	49951	349	0	0
T26	0	1227	0	0
T27	0	507	0	0
T28	870842	0	0	0
T32	0	52	0	0
T33	31620	0	0	0
T49	0	1565	0	0
T52	0	881	0	0
T66	26596	0	0	0
T69	0	182	0	0
T72	0	99	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	791	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T22	22294	1	0	0
T23	49951	1	0	0
T26	185037	5	0	0
T27	0	2	0	0
T28	870842	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T49	46982	2	0	0
T66	26596	0	0	0
T69	0	1	0	0
T70	0	2	0	0
T72	0	1	0	0
T74	0	3	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	72	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T23	49951	1	0	0
T24	0	1	0	0
T26	185037	0	0	0
T27	0	2	0	0
T28	870842	0	0	0
T32	55164	1	0	0
T33	31620	0	0	0
T35	0	1	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T52	0	1	0	0
T55	0	2	0	0
T66	26596	0	0	0
T69	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1622	0	0
T10	16488	178	0	0
T11	0	382	0	0
T12	0	359	0	0
T38	0	365	0	0
T39	0	338	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1352	0	0
T10	16488	148	0	0
T11	0	322	0	0
T12	0	299	0	0
T38	0	305	0	0
T39	0	278	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	662627033	0	0
T1	126272	126263	0	0
T2	980201	979727	0	0
T3	148497	148408	0	0
T4	143072	143066	0	0
T18	12788	12713	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	10138	0	0
T22	22294	22197	0	0
T23	49951	49857	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24,T25
1	1	1	Covered	T1,T2,T18

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T21,T23
1	0	1	Covered	T2,T3,T18
1	1	0	Covered	T22,T23,T66
1	1	1	Covered	T21,T23,T66

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T23,T66
0	1	Covered	T23,T26,T27
1	0	Covered	T7,T29,T27

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T23,T66
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T29,T27

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T23,T66
1	0	Not Covered
1	1	Covered	T23,T26,T27

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T4,T23

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T2,T29,T112

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T33,T26,T50

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T18
Phase1St	193	Covered	T1,T2,T18
Phase2St	210	Covered	T1,T2,T18
Phase3St	228	Covered	T1,T2,T18
TerminalSt	244	Covered	T1,T2,T18
TimeoutSt	154	Covered	T21,T23,T66

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T18
IdleSt->TimeoutSt	154	Covered	T21,T23,T66
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T37,T113
Phase0St->Phase1St	193	Covered	T1,T2,T18
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T27,T37
Phase1St->Phase2St	210	Covered	T1,T2,T18
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T29,T27,T80
Phase2St->Phase3St	228	Covered	T1,T2,T18
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T35,T36,T37
Phase3St->TerminalSt	244	Covered	T1,T2,T18
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T2,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T21,T23,T66
TimeoutSt->Phase0St	167	Covered	T23,T7,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T66
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T7,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T66
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T66
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T37,T113,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T37
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T27,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T36,T37
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662815529	343	0	0
CheckAccumTrig0_A	662815529	852	0	0
CheckAccumTrig1_A	662815529	54	0	0
CheckClr_A	662815529	441	0	0
CheckEn_A	662568162	254670184	0	0
CheckPhase0_A	662815529	950	0	0
CheckPhase1_A	662815529	924	0	0
CheckPhase2_A	662815529	905	0	0
CheckPhase3_A	662815529	876	0	0
CheckTimeout0_A	662815529	707	0	0
CheckTimeoutSt1_A	662815529	90895	0	0
CheckTimeoutSt2_A	662815529	574	0	0
CheckTimeoutStTrig_A	662815529	78	0	0
ErrorStAllEscAsserted_A	662815529	1664	0	0
ErrorStIsTerminal_A	662815529	1394	0	0
u_state_regs_A	662815529	662627033	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	343	0	0
T10	16488	35	0	0
T11	0	83	0	0
T12	0	80	0	0
T38	0	51	0	0
T39	0	94	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	852	0	0
T1	126272	2	0	0
T2	980201	5	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T6	0	1	0	0
T7	0	1	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T26	0	7	0	0
T29	0	5	0	0
T33	0	2	0	0
T50	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	54	0	0
T6	144524	0	0	0
T7	289035	1	0	0
T26	185037	0	0	0
T27	0	1	0	0
T29	52580	1	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T34	89348	0	0	0
T36	0	1	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T67	75569	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	441	0	0
T1	126272	1	0	0
T2	980201	1	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T7	0	1	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T26	0	4	0	0
T27	0	10	0	0
T29	0	5	0	0
T33	0	1	0	0
T50	0	1	0	0
T69	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662568162	254670184	0	0
T1	126272	3646	0	0
T2	980201	20964	0	0
T3	148497	142521	0	0
T4	143072	1901	0	0
T18	12788	6094	0	0
T19	20625	20546	0	0
T20	6847	6792	0	0
T21	10211	582	0	0
T22	22294	22196	0	0
T23	49951	22398	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	950	0	0
T1	126272	2	0	0
T2	980201	5	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T7	0	2	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	7	0	0
T29	0	6	0	0
T33	0	2	0	0
T50	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	924	0	0
T1	126272	2	0	0
T2	980201	5	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T7	0	2	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	5	0	0
T29	0	6	0	0
T33	0	2	0	0
T50	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	905	0	0
T1	126272	2	0	0
T2	980201	5	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T7	0	2	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	5	0	0
T29	0	5	0	0
T33	0	2	0	0
T50	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	876	0	0
T1	126272	2	0	0
T2	980201	5	0	0
T3	148497	0	0	0
T4	143072	1	0	0
T7	0	2	0	0
T18	12788	1	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T26	0	5	0	0
T29	0	5	0	0
T33	0	2	0	0
T50	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	707	0	0
T5	874692	0	0	0
T7	289035	3	0	0
T21	10211	4	0	0
T22	22294	0	0	0
T23	49951	3	0	0
T26	185037	1	0	0
T27	0	7	0	0
T28	870842	0	0	0
T29	0	2	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T66	26596	1	0	0
T69	0	3	0	0
T73	0	7	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	90895	0	0
T5	874692	0	0	0
T7	289035	185	0	0
T21	10211	303	0	0
T22	22294	0	0	0
T23	49951	576	0	0
T26	185037	187	0	0
T27	0	942	0	0
T28	870842	0	0	0
T29	0	60	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T66	26596	124	0	0
T69	0	686	0	0
T73	0	1068	0	0
T74	0	368	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	574	0	0
T5	874692	0	0	0
T7	289035	2	0	0
T21	10211	4	0	0
T22	22294	0	0	0
T23	49951	2	0	0
T26	185037	0	0	0
T27	0	5	0	0
T28	870842	0	0	0
T29	0	1	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T66	26596	1	0	0
T69	0	2	0	0
T73	0	7	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	78	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T23	49951	1	0	0
T24	0	2	0	0
T26	185037	1	0	0
T27	0	1	0	0
T28	870842	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T45	0	1	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T66	26596	0	0	0
T69	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1664	0	0
T10	16488	179	0	0
T11	0	385	0	0
T12	0	400	0	0
T38	0	366	0	0
T39	0	334	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1394	0	0
T10	16488	149	0	0
T11	0	325	0	0
T12	0	340	0	0
T38	0	306	0	0
T39	0	274	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	662627033	0	0
T1	126272	126263	0	0
T2	980201	979727	0	0
T3	148497	148408	0	0
T4	143072	143066	0	0
T18	12788	12713	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	10138	0	0
T22	22294	22197	0	0
T23	49951	49857	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T22
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T20,T22

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T20,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T22,T23
1	0	1	Covered	T107,T114,T69
1	1	0	Covered	T21,T22,T23
1	1	1	Covered	T22,T23,T28

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T28
0	1	Covered	T23,T27,T52
1	0	Covered	T28,T53,T69

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T22,T23,T28
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T53,T69

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T28
1	0	Covered	T30,T31
1	1	Covered	T23,T27,T52

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T23,T5,T28
1	Covered	T1,T20,T16

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T23
1	Covered	T6,T27,T52

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T23
1	Covered	T28,T7,T32

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T28
1	Covered	T23,T5,T107

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T20,T5,T28

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T23,T32,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T20,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T20,T23
Phase1St	193	Covered	T1,T20,T23
Phase2St	210	Covered	T1,T20,T23
Phase3St	228	Covered	T1,T20,T23
TerminalSt	244	Covered	T1,T20,T23
TimeoutSt	154	Covered	T22,T23,T28

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T20,T5
IdleSt->TimeoutSt	154	Covered	T22,T23,T28
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T83,T115
Phase0St->Phase1St	193	Covered	T1,T20,T23
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T7,T37,T62
Phase1St->Phase2St	210	Covered	T1,T20,T23
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T16,T62,T116
Phase2St->Phase3St	228	Covered	T1,T20,T23
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T7,T117,T64
Phase3St->TerminalSt	244	Covered	T1,T20,T23
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T23,T7
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T22,T28,T26
TimeoutSt->Phase0St	167	Covered	T23,T28,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T28
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T28,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T28
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T28,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T115,T118
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T20,T23
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T20,T23
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T37,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T20,T23
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T20,T23
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T62,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T20,T23
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T20,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T117,T64
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T20,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T20,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T23,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T20,T23
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662815529	339	0	0
CheckAccumTrig0_A	662815529	487	0	0
CheckAccumTrig1_A	662815529	29	0	0
CheckClr_A	662815529	201	0	0
CheckEn_A	662568162	291288264	0	0
CheckPhase0_A	662815529	558	0	0
CheckPhase1_A	662815529	550	0	0
CheckPhase2_A	662815529	544	0	0
CheckPhase3_A	662815529	539	0	0
CheckTimeout0_A	662815529	759	0	0
CheckTimeoutSt1_A	662815529	97251	0	0
CheckTimeoutSt2_A	662815529	675	0	0
CheckTimeoutStTrig_A	662815529	53	0	0
ErrorStAllEscAsserted_A	662815529	1623	0	0
ErrorStIsTerminal_A	662815529	1353	0	0
u_state_regs_A	662815529	662627033	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	339	0	0
T10	16488	37	0	0
T11	0	74	0	0
T12	0	65	0	0
T38	0	69	0	0
T39	0	94	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	487	0	0
T1	126272	7	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	7	0	0
T16	0	3	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	0	0	0
T27	0	4	0	0
T32	0	1	0	0
T51	0	1	0	0
T107	0	6	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	29	0	0
T7	289035	0	0	0
T26	185037	0	0	0
T28	870842	1	0	0
T29	52580	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T34	89348	0	0	0
T35	0	1	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T53	0	1	0	0
T58	0	1	0	0
T67	75569	0	0	0
T69	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T108	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	201	0	0
T1	126272	6	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T7	0	6	0	0
T16	0	2	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	0	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T27	0	1	0	0
T35	0	1	0	0
T37	0	5	0	0
T69	0	1	0	0
T77	0	1	0	0
T107	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662568162	291288264	0	0
T1	126272	1763	0	0
T2	980201	967374	0	0
T3	148497	145529	0	0
T4	143072	142934	0	0
T18	12788	8698	0	0
T19	20625	20546	0	0
T20	6847	2909	0	0
T21	10211	10137	0	0
T22	22294	9239	0	0
T23	49951	37989	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	558	0	0
T1	126272	6	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	7	0	0
T16	0	3	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	550	0	0
T1	126272	6	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	6	0	0
T16	0	3	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	544	0	0
T1	126272	6	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	6	0	0
T16	0	2	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	539	0	0
T1	126272	6	0	0
T2	980201	0	0	0
T3	148497	0	0	0
T4	143072	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	5	0	0
T16	0	2	0	0
T18	12788	0	0	0
T19	20625	0	0	0
T20	6847	1	0	0
T21	10211	0	0	0
T22	22294	0	0	0
T23	49951	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	759	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T22	22294	3	0	0
T23	49951	1	0	0
T26	185037	6	0	0
T27	0	4	0	0
T28	870842	2	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T66	26596	0	0	0
T69	0	2	0	0
T71	0	3	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	97251	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T22	22294	386	0	0
T23	49951	178	0	0
T26	185037	1488	0	0
T27	0	881	0	0
T28	870842	28	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T52	0	417	0	0
T53	0	10	0	0
T66	26596	0	0	0
T69	0	77	0	0
T71	0	563	0	0
T72	0	93	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	675	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T22	22294	3	0	0
T23	49951	0	0	0
T24	0	11	0	0
T26	185037	6	0	0
T27	0	2	0	0
T28	870842	1	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T49	46982	0	0	0
T66	26596	0	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0
T75	0	6	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	53	0	0
T5	874692	0	0	0
T7	289035	0	0	0
T23	49951	1	0	0
T24	0	1	0	0
T26	185037	0	0	0
T27	0	2	0	0
T28	870842	0	0	0
T32	55164	0	0	0
T33	31620	0	0	0
T40	0	2	0	0
T49	46982	0	0	0
T50	93395	0	0	0
T52	0	1	0	0
T66	26596	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T122	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1623	0	0
T10	16488	199	0	0
T11	0	367	0	0
T12	0	341	0	0
T38	0	345	0	0
T39	0	371	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	1353	0	0
T10	16488	169	0	0
T11	0	307	0	0
T12	0	281	0	0
T38	0	285	0	0
T39	0	311	0	0
T40	27693	0	0	0
T41	4233	0	0	0
T42	448402	0	0	0
T43	221438	0	0	0
T44	42178	0	0	0
T45	26660	0	0	0
T46	145031	0	0	0
T47	5283	0	0	0
T48	851707	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662815529	662627033	0	0
T1	126272	126263	0	0
T2	980201	979727	0	0
T3	148497	148408	0	0
T4	143072	143066	0	0
T18	12788	12713	0	0
T19	20625	20547	0	0
T20	6847	6793	0	0
T21	10211	10138	0	0
T22	22294	22197	0	0
T23	49951	49857	0	0