Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T87,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14024	0	0
DisabledNoTrigBkwd_A	2147483647	900519	0	0
DisabledNoTrigFwd_A	2147483647	1651680453	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14024	0	0
T3	0	1375	0	0
T11	387939	0	0	0
T23	26266	0	0	0
T63	141523	0	0	0
T64	1018	297	0	0
T72	888311	0	0	0
T73	298655	0	0	0
T74	125624	0	0	0
T76	17665	0	0	0
T87	1024	255	0	0
T113	68094	0	0	0
T199	2787	485	0	0
T200	0	290	0	0
T201	0	825	0	0
T202	0	1083	0	0
T203	0	559	0	0
T204	0	182	0	0
T205	0	299	0	0
T206	0	890	0	0
T207	0	436	0	0
T208	0	888	0	0
T209	0	1848	0	0
T210	4371	940	0	0
T211	0	347	0	0
T212	0	284	0	0
T213	0	979	0	0
T214	0	660	0	0
T215	0	1102	0	0
T216	22758	0	0	0
T217	193550	0	0	0
T218	181914	0	0	0
T219	627201	0	0	0
T220	152718	0	0	0
T221	97436	0	0	0
T222	23266	0	0	0
T223	31024	0	0	0
T224	111344	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	900519	0	0
T2	913308	1657	0	0
T3	3731	32	0	0
T4	3710144	654	0	0
T5	1977660	4677	0	0
T6	172982	65	0	0
T7	1124164	756	0	0
T8	0	3846	0	0
T15	442284	3958	0	0
T17	0	2185	0	0
T18	0	282	0	0
T19	350428	20	0	0
T20	417076	101	0	0
T21	68260	0	0	0
T26	0	17	0	0
T43	134949	15	0	0
T44	500280	340	0	0
T45	0	48	0	0
T46	0	348	0	0
T47	171112	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1651680453	0	0
T1	1400096	1396118	0	0
T2	3653232	2736404	0	0
T3	14924	8094	0	0
T4	3710144	1856104	0	0
T5	1977660	988975	0	0
T6	345964	262331	0	0
T7	1124164	323537	0	0
T15	442284	238870	0	0
T19	350428	245163	0	0
T20	417076	319914	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T19
1	0	Covered	T1,T2,T19
1	1	Covered	T6,T19,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T213,T215
1	1	Covered	T6,T19,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T19,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	745477658	3021	0	0
DisabledNoTrigBkwd_A	745477658	279519	0	0
DisabledNoTrigFwd_A	745477658	360052827	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	3021	0	0
T63	141523	0	0	0
T210	4371	940	0	0
T213	0	979	0	0
T215	0	1102	0	0
T217	193550	0	0	0
T218	181914	0	0	0
T219	627201	0	0	0
T220	152718	0	0	0
T221	97436	0	0	0
T222	23266	0	0	0
T223	31024	0	0	0
T224	111344	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	279519	0	0
T4	927536	225	0	0
T5	494415	0	0	0
T6	86491	65	0	0
T7	281041	2	0	0
T8	0	3341	0	0
T15	110571	2180	0	0
T17	0	2	0	0
T19	87607	1	0	0
T20	104269	101	0	0
T21	17065	0	0	0
T26	0	17	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	31	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	360052827	0	0
T1	350024	349956	0	0
T2	913308	913235	0	0
T3	3731	2000	0	0
T4	927536	2666	0	0
T5	494415	492957	0	0
T6	86491	3101	0	0
T7	281041	19209	0	0
T15	110571	10355	0	0
T19	87607	80142	0	0
T20	104269	7341	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T87,T203,T205
1	1	Covered	T1,T2,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T5,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	745477658	2350	0	0
DisabledNoTrigBkwd_A	745477658	243541	0	0
DisabledNoTrigFwd_A	745477658	418714190	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	2350	0	0
T11	387939	0	0	0
T23	26266	0	0	0
T72	888311	0	0	0
T73	298655	0	0	0
T74	125624	0	0	0
T76	17665	0	0	0
T87	1024	255	0	0
T113	68094	0	0	0
T199	2787	0	0	0
T203	0	559	0	0
T205	0	299	0	0
T206	0	890	0	0
T211	0	347	0	0
T216	22758	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	243541	0	0
T4	927536	0	0	0
T5	494415	11	0	0
T7	281041	259	0	0
T8	0	173	0	0
T15	110571	1753	0	0
T17	0	2181	0	0
T18	0	205	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	10	0	0
T44	166760	0	0	0
T45	0	17	0	0
T46	0	3	0	0
T47	85556	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	418714190	0	0
T1	350024	346250	0	0
T2	913308	911276	0	0
T3	3731	2018	0	0
T4	927536	925382	0	0
T5	494415	490656	0	0
T6	86491	86410	0	0
T7	281041	3119	0	0
T15	110571	8866	0	0
T19	87607	74766	0	0
T20	104269	104191	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T19
1	1	Covered	T2,T19,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T201,T208
1	1	Covered	T2,T19,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	745477658	4518	0	0
DisabledNoTrigBkwd_A	745477658	186932	0	0
DisabledNoTrigFwd_A	745477658	442145464	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	4518	0	0
T31	367044	0	0	0
T51	673747	0	0	0
T64	1018	297	0	0
T65	200863	0	0	0
T66	160387	0	0	0
T67	764962	0	0	0
T68	168232	0	0	0
T69	2241	0	0	0
T70	80941	0	0	0
T201	0	825	0	0
T208	0	888	0	0
T209	0	1848	0	0
T214	0	660	0	0
T225	69195	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	186932	0	0
T4	927536	429	0	0
T5	494415	2109	0	0
T7	281041	495	0	0
T8	0	196	0	0
T15	110571	9	0	0
T17	0	2	0	0
T18	0	5	0	0
T19	87607	15	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	4	0	0
T44	166760	131	0	0
T47	85556	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	442145464	0	0
T1	350024	349956	0	0
T2	913308	911276	0	0
T3	3731	2034	0	0
T4	927536	2674	0	0
T5	494415	2676	0	0
T6	86491	86410	0	0
T7	281041	20175	0	0
T15	110571	109585	0	0
T19	87607	10110	0	0
T20	104269	104191	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T19,T4
1	1	Covered	T2,T3,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T199,T200
1	1	Covered	T2,T3,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	745477658	4135	0	0
DisabledNoTrigBkwd_A	745477658	190527	0	0
DisabledNoTrigFwd_A	745477658	430767972	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	4135	0	0
T3	3731	1375	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	0	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	0	0	0
T199	0	485	0	0
T200	0	290	0	0
T202	0	1083	0	0
T204	0	182	0	0
T207	0	436	0	0
T212	0	284	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	190527	0	0
T2	913308	1657	0	0
T3	3731	32	0	0
T4	927536	0	0	0
T5	494415	2557	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	136	0	0
T15	110571	16	0	0
T18	0	72	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	209	0	0
T46	0	345	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	430767972	0	0
T1	350024	349956	0	0
T2	913308	617	0	0
T3	3731	2042	0	0
T4	927536	925382	0	0
T5	494415	2686	0	0
T6	86491	86410	0	0
T7	281041	281034	0	0
T15	110571	110064	0	0
T19	87607	80145	0	0
T20	104269	104191	0	0