Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T18,T22
1	1	1	Covered	T2,T3,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T19
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T2,T19,T5
1	1	1	Covered	T6,T19,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T19,T5
0	1	Covered	T19,T8,T18
1	0	Covered	T6,T8,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T5
1	0	Not Covered
1	1	Covered	T19,T8,T18

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T19
1	Covered	T19,T5,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T19,T4,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T19,T4,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T4
1	Covered	T6,T5,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T6,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T19,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T12,T13,T14
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T6
Phase1St	193	Covered	T2,T3,T6
Phase2St	210	Covered	T2,T3,T6
Phase3St	228	Covered	T2,T3,T6
TerminalSt	244	Covered	T2,T3,T6
TimeoutSt	154	Covered	T6,T19,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T12,T13,T14
IdleSt->Phase0St	147	Covered	T2,T3,T6
IdleSt->TimeoutSt	154	Covered	T6,T19,T5
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T17,T24,T25
Phase0St->Phase1St	193	Covered	T2,T3,T6
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T15,T26,T18
Phase1St->Phase2St	210	Covered	T2,T3,T6
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T18,T27,T28
Phase2St->Phase3St	228	Covered	T2,T3,T6
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T8,T29,T30
Phase3St->TerminalSt	244	Covered	T2,T3,T6
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T6,T19
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T19,T5,T15
TimeoutSt->Phase0St	167	Covered	T6,T19,T8

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T17,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T26,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T6,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1105	0	0
CheckAccumTrig0_A	2147483647	2501	0	0
CheckAccumTrig1_A	2147483647	121	0	0
CheckClr_A	2147483647	1195	0	0
CheckEn_A	2147483647	1312265730	0	0
CheckPhase0_A	2147483647	2806	0	0
CheckPhase1_A	2147483647	2748	0	0
CheckPhase2_A	2147483647	2683	0	0
CheckPhase3_A	2147483647	2633	0	0
CheckTimeout0_A	2147483647	4624	0	0
CheckTimeoutSt1_A	2147483647	413690	0	0
CheckTimeoutSt2_A	2147483647	4271	0	0
CheckTimeoutStTrig_A	2147483647	227	0	0
ErrorStAllEscAsserted_A	2147483647	5699	0	0
ErrorStIsTerminal_A	2147483647	4739	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1105	0	0
T12	124972	253	0	0
T13	0	278	0	0
T14	0	186	0	0
T32	0	266	0	0
T33	0	122	0	0
T34	156344	0	0	0
T35	151512	0	0	0
T36	2009176	0	0	0
T37	3595764	0	0	0
T38	757848	0	0	0
T39	513196	0	0	0
T40	1960260	0	0	0
T41	671816	0	0	0
T42	3533844	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	3710144	2	0	0
T5	1977660	13	0	0
T6	172982	4	0	0
T7	1124164	4	0	0
T8	649214	16	0	0
T15	442284	8	0	0
T17	0	5	0	0
T18	0	6	0	0
T19	262821	3	0	0
T20	417076	10	0	0
T21	68260	0	0	0
T26	0	4	0	0
T43	134949	3	0	0
T44	500280	2	0	0
T45	0	2	0	0
T46	0	12	0	0
T47	171112	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	1	0	0
T7	281041	0	0	0
T8	0	1	0	0
T15	110571	0	0	0
T19	87607	0	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	367044	0	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T48	0	1	0	0
T49	379987	1	0	0
T50	46614	1	0	0
T51	673747	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	4	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	3	0	0
T64	2036	0	0	0
T65	401726	0	0	0
T66	320774	0	0	0
T67	1529924	0	0	0
T68	168232	0	0	0
T69	2241	0	0	0
T70	80941	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1195	0	0
T2	913308	9	0	0
T3	3731	0	0	0
T4	3710144	0	0	0
T5	1977660	10	0	0
T6	172982	4	0	0
T7	1124164	1	0	0
T8	0	5	0	0
T10	0	1	0	0
T15	442284	4	0	0
T17	0	4	0	0
T18	0	2	0	0
T19	350428	5	0	0
T20	417076	9	0	0
T21	68260	0	0	0
T26	0	3	0	0
T27	0	11	0	0
T29	0	8	0	0
T43	134949	0	0	0
T44	500280	0	0	0
T46	0	8	0	0
T47	171112	0	0	0
T48	0	1	0	0
T71	0	5	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1312265730	0	0
T1	1400096	1396114	0	0
T2	3653232	2736401	0	0
T3	14924	8094	0	0
T4	3710144	1856102	0	0
T5	1977660	585720	0	0
T6	345964	262328	0	0
T7	1124164	310428	0	0
T15	442284	28898	0	0
T19	350428	245160	0	0
T20	417076	319911	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2806	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	3710144	2	0	0
T5	1977660	12	0	0
T6	172982	5	0	0
T7	1124164	4	0	0
T8	0	19	0	0
T15	442284	8	0	0
T17	0	4	0	0
T18	0	8	0	0
T19	350428	6	0	0
T20	417076	10	0	0
T21	68260	0	0	0
T26	0	4	0	0
T43	134949	3	0	0
T44	500280	2	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	171112	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2748	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	3710144	2	0	0
T5	1977660	10	0	0
T6	172982	5	0	0
T7	1124164	4	0	0
T8	0	19	0	0
T15	442284	7	0	0
T17	0	4	0	0
T18	0	8	0	0
T19	350428	6	0	0
T20	417076	10	0	0
T21	68260	0	0	0
T26	0	3	0	0
T43	134949	3	0	0
T44	500280	2	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	171112	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2683	0	0
T2	913308	9	0	0
T3	3731	1	0	0
T4	3710144	2	0	0
T5	1977660	10	0	0
T6	172982	5	0	0
T7	1124164	4	0	0
T8	0	19	0	0
T15	442284	7	0	0
T17	0	4	0	0
T18	0	7	0	0
T19	350428	6	0	0
T20	417076	10	0	0
T21	68260	0	0	0
T26	0	3	0	0
T43	134949	3	0	0
T44	500280	2	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	171112	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2633	0	0
T2	913308	9	0	0
T3	3731	1	0	0
T4	3710144	2	0	0
T5	1977660	9	0	0
T6	172982	5	0	0
T7	1124164	4	0	0
T8	0	18	0	0
T15	442284	7	0	0
T17	0	4	0	0
T18	0	7	0	0
T19	350428	6	0	0
T20	417076	10	0	0
T21	68260	0	0	0
T26	0	3	0	0
T43	134949	3	0	0
T44	500280	2	0	0
T45	0	2	0	0
T46	0	10	0	0
T47	171112	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4624	0	0
T4	2782608	0	0	0
T5	1483245	1	0	0
T6	86491	1	0	0
T7	843123	0	0	0
T8	649214	7	0	0
T9	631470	0	0	0
T15	331713	2	0	0
T16	14718	0	0	0
T17	190995	2	0	0
T18	872345	3	0	0
T19	262821	5	0	0
T20	312807	0	0	0
T21	51195	1	0	0
T23	0	2	0	0
T26	42833	0	0	0
T29	0	3	0	0
T43	134949	6	0	0
T44	500280	0	0	0
T45	83193	0	0	0
T46	579751	2	0	0
T47	171112	7	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	3	0	0
T71	0	1	0	0
T73	0	2	0	0
T75	0	2	0	0
T76	0	5	0	0
T77	40281	0	0	0
T78	30179	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	413690	0	0
T4	2782608	0	0	0
T5	1483245	30	0	0
T6	86491	1	0	0
T7	843123	0	0	0
T8	649214	481	0	0
T9	631470	0	0	0
T15	331713	136	0	0
T16	14718	0	0	0
T17	190995	55	0	0
T18	872345	1126	0	0
T19	262821	817	0	0
T20	312807	0	0	0
T21	51195	197	0	0
T23	0	58	0	0
T26	42833	0	0	0
T29	0	324	0	0
T43	134949	575	0	0
T44	500280	0	0	0
T45	83193	0	0	0
T46	579751	582	0	0
T47	171112	1539	0	0
T48	0	246	0	0
T49	0	307	0	0
T50	0	7	0	0
T51	0	248	0	0
T71	0	124	0	0
T73	0	317	0	0
T75	0	320	0	0
T76	0	499	0	0
T77	40281	0	0	0
T78	30179	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4271	0	0
T4	1855072	0	0	0
T5	988830	1	0	0
T7	843123	0	0	0
T8	1298428	4	0	0
T9	1262940	0	0	0
T15	331713	2	0	0
T16	29436	0	0	0
T17	190995	2	0	0
T18	872345	1	0	0
T19	175214	2	0	0
T20	208538	0	0	0
T21	51195	1	0	0
T23	0	1	0	0
T26	42833	0	0	0
T27	0	98	0	0
T29	0	2	0	0
T31	0	4	0	0
T43	134949	6	0	0
T44	500280	0	0	0
T45	166386	0	0	0
T46	579751	1	0	0
T47	256668	7	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	74	0	0
T71	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	40281	0	0	0
T78	30179	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	227	0	0
T4	1855072	0	0	0
T5	988830	0	0	0
T7	562082	0	0	0
T8	0	2	0	0
T10	1654360	0	0	0
T15	221142	0	0	0
T18	1744690	2	0	0
T19	175214	3	0	0
T20	208538	0	0	0
T21	34130	0	0	0
T22	0	1	0	0
T25	0	2	0	0
T27	0	7	0	0
T28	0	2	0	0
T29	441832	1	0	0
T31	0	3	0	0
T43	89966	0	0	0
T44	333520	0	0	0
T46	1159502	1	0	0
T47	171112	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T71	803992	0	0	0
T73	0	2	0	0
T75	0	2	0	0
T77	80562	0	0	0
T78	60358	0	0	0
T79	0	4	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	6	0	0
T85	85710	0	0	0
T86	56140	0	0	0
T87	2048	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5699	0	0
T12	124972	1460	0	0
T13	0	1427	0	0
T14	0	721	0	0
T32	0	1382	0	0
T33	0	709	0	0
T34	156344	0	0	0
T35	151512	0	0	0
T36	2009176	0	0	0
T37	3595764	0	0	0
T38	757848	0	0	0
T39	513196	0	0	0
T40	1960260	0	0	0
T41	671816	0	0	0
T42	3533844	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4739	0	0
T12	124972	1220	0	0
T13	0	1187	0	0
T14	0	601	0	0
T32	0	1142	0	0
T33	0	589	0	0
T34	156344	0	0	0
T35	151512	0	0	0
T36	2009176	0	0	0
T37	3595764	0	0	0
T38	757848	0	0	0
T39	513196	0	0	0
T40	1960260	0	0	0
T41	671816	0	0	0
T42	3533844	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1400096	1399824	0	0
T2	3653232	3652940	0	0
T3	14924	14568	0	0
T4	3710144	3709864	0	0
T5	1977660	1977636	0	0
T6	345964	345640	0	0
T7	1124164	1124136	0	0
T15	442284	442252	0	0
T19	350428	350124	0	0
T20	417076	416764	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T15

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T4,T7,T44
1	1	0	Covered	T2,T19,T15
1	1	1	Covered	T19,T43,T47

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T43,T47
0	1	Covered	T19,T29,T73
1	0	Covered	T49,T53,T88

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T43,T47
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T53,T88

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T43,T47
1	0	Not Covered
1	1	Covered	T19,T29,T73

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T4,T5
1	Covered	T15,T18,T29

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T15,T43
1	Covered	T19,T4,T7

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T4,T15
1	Covered	T5,T43,T44

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T4,T5
1	Covered	T15,T8,T17

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T15,T43

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T4,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T15,T43

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T12,T13,T14
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T19,T4,T5
Phase1St	193	Covered	T19,T4,T5
Phase2St	210	Covered	T19,T4,T5
Phase3St	228	Covered	T19,T4,T5
TerminalSt	244	Covered	T19,T4,T5
TimeoutSt	154	Covered	T19,T43,T47

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T12,T13,T14
IdleSt->Phase0St	147	Covered	T4,T5,T15
IdleSt->TimeoutSt	154	Covered	T19,T43,T47
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T25,T89,T90
Phase0St->Phase1St	193	Covered	T19,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T52,T54,T91
Phase1St->Phase2St	210	Covered	T19,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T18,T92,T93
Phase2St->Phase3St	228	Covered	T19,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T51,T93,T39
Phase3St->TerminalSt	244	Covered	T19,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T19,T15,T8
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T19,T43,T47
TimeoutSt->Phase0St	167	Covered	T19,T29,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T43,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T29,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T43,T47
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T43,T47
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T89,T94,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T19,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T19,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T52,T91,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T19,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T19,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T19,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T19,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T51,T93,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T19,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T19,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T15,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T19,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	745477658	280	0	0
CheckAccumTrig0_A	745477658	528	0	0
CheckAccumTrig1_A	745477658	18	0	0
CheckClr_A	745477658	235	0	0
CheckEn_A	745161462	363120153	0	0
CheckPhase0_A	745477658	593	0	0
CheckPhase1_A	745477658	585	0	0
CheckPhase2_A	745477658	571	0	0
CheckPhase3_A	745477658	564	0	0
CheckTimeout0_A	745477658	1215	0	0
CheckTimeoutSt1_A	745477658	98297	0	0
CheckTimeoutSt2_A	745477658	1141	0	0
CheckTimeoutStTrig_A	745477658	53	0	0
ErrorStAllEscAsserted_A	745477658	1371	0	0
ErrorStIsTerminal_A	745477658	1131	0	0
u_state_regs_A	745477658	745305173	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	280	0	0
T12	31243	41	0	0
T13	0	105	0	0
T14	0	42	0	0
T32	0	66	0	0
T33	0	26	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	528	0	0
T4	927536	1	0	0
T5	494415	1	0	0
T7	281041	1	0	0
T8	649214	4	0	0
T15	110571	3	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	1	0	0
T46	0	3	0	0
T47	85556	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	18	0	0
T27	800508	0	0	0
T49	379987	1	0	0
T50	23307	0	0	0
T53	0	2	0	0
T58	0	1	0	0
T63	0	2	0	0
T64	1018	0	0	0
T65	200863	0	0	0
T66	160387	0	0	0
T67	764962	0	0	0
T88	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	38533	0	0	0
T103	490594	0	0	0
T104	23329	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	235	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T15	110571	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T29	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T71	0	3	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745161462	363120153	0	0
T1	350024	349955	0	0
T2	913308	911275	0	0
T3	3731	2034	0	0
T4	927536	2674	0	0
T5	494415	2676	0	0
T6	86491	86409	0	0
T7	281041	8571	0	0
T15	110571	6966	0	0
T19	87607	10110	0	0
T20	104269	104190	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	593	0	0
T4	927536	1	0	0
T5	494415	1	0	0
T7	281041	1	0	0
T8	0	4	0	0
T15	110571	3	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	1	0	0
T47	85556	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	585	0	0
T4	927536	1	0	0
T5	494415	1	0	0
T7	281041	1	0	0
T8	0	4	0	0
T15	110571	3	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	1	0	0
T47	85556	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	571	0	0
T4	927536	1	0	0
T5	494415	1	0	0
T7	281041	1	0	0
T8	0	4	0	0
T15	110571	3	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	1	0	0
T47	85556	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	564	0	0
T4	927536	1	0	0
T5	494415	1	0	0
T7	281041	1	0	0
T8	0	4	0	0
T15	110571	3	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	1	0	0
T47	85556	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1215	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	3	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T29	0	1	0	0
T43	44983	2	0	0
T44	166760	0	0	0
T47	85556	7	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	3	0	0
T73	0	1	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	98297	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	581	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T29	0	4	0	0
T43	44983	127	0	0
T44	166760	0	0	0
T47	85556	1539	0	0
T48	0	246	0	0
T49	0	307	0	0
T50	0	7	0	0
T51	0	248	0	0
T73	0	273	0	0
T75	0	320	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1141	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T31	0	4	0	0
T43	44983	2	0	0
T44	166760	0	0	0
T47	85556	7	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T75	0	1	0	0
T105	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	53	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T29	0	1	0	0
T31	0	2	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T73	0	1	0	0
T75	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1371	0	0
T12	31243	336	0	0
T13	0	357	0	0
T14	0	164	0	0
T32	0	360	0	0
T33	0	154	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1131	0	0
T12	31243	276	0	0
T13	0	297	0	0
T14	0	134	0	0
T32	0	300	0	0
T33	0	124	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	745305173	0	0
T1	350024	349956	0	0
T2	913308	913235	0	0
T3	3731	3642	0	0
T4	927536	927466	0	0
T5	494415	494409	0	0
T6	86491	86410	0	0
T7	281041	281034	0	0
T15	110571	110563	0	0
T19	87607	87531	0	0
T20	104269	104191	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T3,T44,T8
1	1	0	Covered	T19,T21,T47
1	1	1	Covered	T8,T18,T46

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T18,T71
0	1	Covered	T18,T48,T51
1	0	Covered	T46,T53,T106

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T8,T18,T71
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T46,T53,T106

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T18,T46
1	0	Not Covered
1	1	Covered	T18,T48,T51

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T19,T15
1	Covered	T3,T5,T8

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T43,T18,T46

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T19,T15,T18

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T5
1	Covered	T2,T44,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T19,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T3,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T3,T8,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T12,T13,T14
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T19
Phase1St	193	Covered	T2,T3,T19
Phase2St	210	Covered	T2,T3,T19
Phase3St	228	Covered	T2,T3,T19
TerminalSt	244	Covered	T2,T3,T19
TimeoutSt	154	Covered	T8,T18,T46

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T12,T13,T14
IdleSt->Phase0St	147	Covered	T2,T3,T19
IdleSt->TimeoutSt	154	Covered	T8,T18,T46
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T54,T107
Phase0St->Phase1St	193	Covered	T2,T3,T19
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T5,T27,T31
Phase1St->Phase2St	210	Covered	T2,T3,T19
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T2,T108,T109
Phase2St->Phase3St	228	Covered	T2,T3,T19
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T5,T107,T36
Phase3St->TerminalSt	244	Covered	T2,T3,T19
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T19,T5
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T8,T71,T76
TimeoutSt->Phase0St	167	Covered	T18,T46,T48

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T18,T46
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T46,T48
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T18,T71
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T8,T71,T76
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T107,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T19,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T27,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T19,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T108,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T19,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T107,T36
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T19,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	745477658	292	0	0
CheckAccumTrig0_A	745477658	532	0	0
CheckAccumTrig1_A	745477658	25	0	0
CheckClr_A	745477658	256	0	0
CheckEn_A	745161462	363885896	0	0
CheckPhase0_A	745477658	598	0	0
CheckPhase1_A	745477658	579	0	0
CheckPhase2_A	745477658	567	0	0
CheckPhase3_A	745477658	559	0	0
CheckTimeout0_A	745477658	947	0	0
CheckTimeoutSt1_A	745477658	100775	0	0
CheckTimeoutSt2_A	745477658	871	0	0
CheckTimeoutStTrig_A	745477658	49	0	0
ErrorStAllEscAsserted_A	745477658	1388	0	0
ErrorStIsTerminal_A	745477658	1148	0	0
u_state_regs_A	745477658	745305173	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	292	0	0
T12	31243	69	0	0
T13	0	64	0	0
T14	0	42	0	0
T32	0	89	0	0
T33	0	28	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	532	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	927536	0	0	0
T5	494415	9	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	1	0	0
T18	0	2	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	8	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	25	0	0
T10	827180	0	0	0
T29	220916	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T42	0	3	0	0
T46	579751	1	0	0
T53	0	1	0	0
T71	401996	0	0	0
T72	888311	0	0	0
T78	30179	0	0	0
T85	42855	0	0	0
T86	28070	0	0	0
T87	1024	0	0	0
T89	0	1	0	0
T92	0	1	0	0
T106	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	68094	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	256	0	0
T2	913308	9	0	0
T3	3731	0	0	0
T4	927536	0	0	0
T5	494415	8	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T15	110571	0	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T27	0	4	0	0
T46	0	8	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0
T103	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745161462	363885896	0	0
T1	350024	349955	0	0
T2	913308	617	0	0
T3	3731	2042	0	0
T4	927536	925381	0	0
T5	494415	2686	0	0
T6	86491	86409	0	0
T7	281041	281034	0	0
T15	110571	2711	0	0
T19	87607	80144	0	0
T20	104269	104190	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	598	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	927536	0	0	0
T5	494415	8	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	1	0	0
T18	0	3	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	9	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	579	0	0
T2	913308	10	0	0
T3	3731	1	0	0
T4	927536	0	0	0
T5	494415	6	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	1	0	0
T18	0	3	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	9	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	567	0	0
T2	913308	9	0	0
T3	3731	1	0	0
T4	927536	0	0	0
T5	494415	6	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	1	0	0
T18	0	3	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	9	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	559	0	0
T2	913308	9	0	0
T3	3731	1	0	0
T4	927536	0	0	0
T5	494415	5	0	0
T6	86491	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	1	0	0
T18	0	3	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	9	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	947	0	0
T8	649214	4	0	0
T9	631470	0	0	0
T16	14718	0	0	0
T17	190995	0	0	0
T18	872345	1	0	0
T26	42833	0	0	0
T27	0	1	0	0
T31	0	4	0	0
T45	83193	0	0	0
T46	579751	1	0	0
T48	0	1	0	0
T51	0	8	0	0
T52	0	2	0	0
T71	0	2	0	0
T76	0	3	0	0
T77	40281	0	0	0
T78	30179	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	100775	0	0
T8	649214	464	0	0
T9	631470	0	0	0
T16	14718	0	0	0
T17	190995	0	0	0
T18	872345	121	0	0
T26	42833	0	0	0
T27	0	91	0	0
T31	0	1226	0	0
T45	83193	0	0	0
T46	579751	0	0	0
T48	0	71	0	0
T51	0	2471	0	0
T52	0	284	0	0
T53	0	41	0	0
T71	0	168	0	0
T76	0	303	0	0
T77	40281	0	0	0
T78	30179	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	871	0	0
T8	649214	4	0	0
T9	631470	0	0	0
T16	14718	0	0	0
T17	190995	0	0	0
T18	872345	0	0	0
T26	42833	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	4	0	0
T45	83193	0	0	0
T46	579751	0	0	0
T51	0	7	0	0
T52	0	2	0	0
T54	0	1	0	0
T71	0	2	0	0
T76	0	3	0	0
T77	40281	0	0	0
T78	30179	0	0	0
T114	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	49	0	0
T10	827180	0	0	0
T18	872345	1	0	0
T28	0	1	0	0
T29	220916	0	0	0
T46	579751	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T71	401996	0	0	0
T77	40281	0	0	0
T78	30179	0	0	0
T80	0	1	0	0
T82	0	1	0	0
T85	42855	0	0	0
T86	28070	0	0	0
T87	1024	0	0	0
T115	0	1	0	0
T116	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1388	0	0
T12	31243	366	0	0
T13	0	341	0	0
T14	0	184	0	0
T32	0	333	0	0
T33	0	164	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1148	0	0
T12	31243	306	0	0
T13	0	281	0	0
T14	0	154	0	0
T32	0	273	0	0
T33	0	134	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	745305173	0	0
T1	350024	349956	0	0
T2	913308	913235	0	0
T3	3731	3642	0	0
T4	927536	927466	0	0
T5	494415	494409	0	0
T6	86491	86410	0	0
T7	281041	281034	0	0
T15	110571	110563	0	0
T19	87607	87531	0	0
T20	104269	104191	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T6,T19,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T19,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T19,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T6,T19,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T19,T5
1	0	1	Covered	T4,T7,T8
1	1	0	Covered	T2,T19,T5
1	1	1	Covered	T6,T15,T8

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T15,T8
0	1	Covered	T18,T46,T73
1	0	Covered	T6,T8,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T15,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T8
1	0	Not Covered
1	1	Covered	T18,T46,T73

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T4,T20
1	Covered	T19,T15,T8

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T19,T4
1	Covered	T20,T8,T26

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T19,T20
1	Covered	T4,T7,T8

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T4,T20
1	Covered	T6,T7,T8

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T6,T20,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T6,T19,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T20,T15,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T7,T8,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T12,T13,T14
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T6,T19,T4
Phase1St	193	Covered	T6,T19,T4
Phase2St	210	Covered	T6,T19,T4
Phase3St	228	Covered	T6,T19,T4
TerminalSt	244	Covered	T6,T19,T4
TimeoutSt	154	Covered	T6,T15,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T12,T13,T14
IdleSt->Phase0St	147	Covered	T6,T19,T4
IdleSt->TimeoutSt	154	Covered	T6,T15,T8
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T117,T111
Phase0St->Phase1St	193	Covered	T6,T19,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T18,T31
Phase1St->Phase2St	210	Covered	T6,T19,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T118,T119
Phase2St->Phase3St	228	Covered	T6,T19,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T8,T29,T30
Phase3St->TerminalSt	244	Covered	T6,T19,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T6,T19,T20
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T15,T8,T18
TimeoutSt->Phase0St	167	Covered	T6,T8,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T8,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T111,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T19,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T19,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T31,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T19,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T19,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T118,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T19,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T19,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T19,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T19,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T19,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T19,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	745477658	256	0	0
CheckAccumTrig0_A	745477658	894	0	0
CheckAccumTrig1_A	745477658	55	0	0
CheckClr_A	745477658	445	0	0
CheckEn_A	745161462	262318168	0	0
CheckPhase0_A	745477658	990	0	0
CheckPhase1_A	745477658	971	0	0
CheckPhase2_A	745477658	947	0	0
CheckPhase3_A	745477658	921	0	0
CheckTimeout0_A	745477658	1174	0	0
CheckTimeoutSt1_A	745477658	105068	0	0
CheckTimeoutSt2_A	745477658	1060	0	0
CheckTimeoutStTrig_A	745477658	59	0	0
ErrorStAllEscAsserted_A	745477658	1487	0	0
ErrorStIsTerminal_A	745477658	1247	0	0
u_state_regs_A	745477658	745305173	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	256	0	0
T12	31243	60	0	0
T13	0	40	0	0
T14	0	53	0	0
T32	0	60	0	0
T33	0	43	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	894	0	0
T4	927536	1	0	0
T5	494415	0	0	0
T6	86491	4	0	0
T7	281041	2	0	0
T8	0	6	0	0
T15	110571	1	0	0
T17	0	1	0	0
T19	87607	1	0	0
T20	104269	10	0	0
T21	17065	0	0	0
T26	0	4	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	55	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	1	0	0
T7	281041	0	0	0
T8	0	1	0	0
T15	110571	0	0	0
T19	87607	0	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T30	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	445	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	4	0	0
T7	281041	1	0	0
T8	0	2	0	0
T15	110571	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	87607	1	0	0
T20	104269	9	0	0
T21	17065	0	0	0
T26	0	3	0	0
T29	0	6	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745161462	262318168	0	0
T1	350024	349955	0	0
T2	913308	913234	0	0
T3	3731	2000	0	0
T4	927536	2666	0	0
T5	494415	492957	0	0
T6	86491	3101	0	0
T7	281041	17704	0	0
T15	110571	10355	0	0
T19	87607	80141	0	0
T20	104269	7341	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	990	0	0
T4	927536	1	0	0
T5	494415	0	0	0
T6	86491	5	0	0
T7	281041	2	0	0
T8	0	7	0	0
T15	110571	1	0	0
T17	0	1	0	0
T19	87607	1	0	0
T20	104269	10	0	0
T21	17065	0	0	0
T26	0	4	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	971	0	0
T4	927536	1	0	0
T5	494415	0	0	0
T6	86491	5	0	0
T7	281041	2	0	0
T8	0	7	0	0
T15	110571	1	0	0
T17	0	1	0	0
T19	87607	1	0	0
T20	104269	10	0	0
T21	17065	0	0	0
T26	0	3	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	947	0	0
T4	927536	1	0	0
T5	494415	0	0	0
T6	86491	5	0	0
T7	281041	2	0	0
T8	0	7	0	0
T15	110571	1	0	0
T17	0	1	0	0
T19	87607	1	0	0
T20	104269	10	0	0
T21	17065	0	0	0
T26	0	3	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	921	0	0
T4	927536	1	0	0
T5	494415	0	0	0
T6	86491	5	0	0
T7	281041	2	0	0
T8	0	6	0	0
T15	110571	1	0	0
T17	0	1	0	0
T19	87607	1	0	0
T20	104269	10	0	0
T21	17065	0	0	0
T26	0	3	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1174	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	1	0	0
T7	281041	0	0	0
T8	0	4	0	0
T15	110571	1	0	0
T18	0	2	0	0
T19	87607	0	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T23	0	2	0	0
T29	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T46	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	105068	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T6	86491	1	0	0
T7	281041	0	0	0
T8	0	278	0	0
T15	110571	54	0	0
T18	0	420	0	0
T19	87607	0	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T23	0	58	0	0
T29	0	160	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T46	0	582	0	0
T71	0	124	0	0
T73	0	44	0	0
T76	0	88	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1060	0	0
T7	281041	0	0	0
T8	649214	3	0	0
T9	631470	0	0	0
T15	110571	1	0	0
T16	14718	0	0	0
T18	0	1	0	0
T21	17065	0	0	0
T23	0	1	0	0
T27	0	94	0	0
T29	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T45	83193	0	0	0
T46	0	1	0	0
T47	85556	0	0	0
T51	0	71	0	0
T71	0	1	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	59	0	0
T10	827180	0	0	0
T18	872345	1	0	0
T22	0	1	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	220916	0	0	0
T46	579751	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T71	401996	0	0	0
T73	0	1	0	0
T77	40281	0	0	0
T78	30179	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T85	42855	0	0	0
T86	28070	0	0	0
T87	1024	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1487	0	0
T12	31243	379	0	0
T13	0	352	0	0
T14	0	196	0	0
T32	0	351	0	0
T33	0	209	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1247	0	0
T12	31243	319	0	0
T13	0	292	0	0
T14	0	166	0	0
T32	0	291	0	0
T33	0	179	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	745305173	0	0
T1	350024	349956	0	0
T2	913308	913235	0	0
T3	3731	3642	0	0
T4	927536	927466	0	0
T5	494415	494409	0	0
T6	86491	86410	0	0
T7	281041	281034	0	0
T15	110571	110563	0	0
T19	87607	87531	0	0
T20	104269	104191	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T5,T15
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T19,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T5,T15

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T18
1	1	1	Covered	T19,T5,T15

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T19,T5
1	0	1	Covered	T4,T8,T45
1	1	0	Covered	T2,T19,T5
1	1	1	Covered	T19,T5,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T19,T5,T15
0	1	Covered	T19,T8,T18
1	0	Covered	T50,T52,T53

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T19,T5,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T52,T53

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T5,T15
1	0	Not Covered
1	1	Covered	T19,T8,T18

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T43
1	Covered	T19,T5,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T15
1	Covered	T5,T43,T8

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T15
1	Covered	T19,T8,T45

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T5,T15
1	Covered	T5,T8,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T15,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T15,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T5,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T19,T5,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T12,T13,T14
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T19,T5,T15
Phase1St	193	Covered	T19,T5,T15
Phase2St	210	Covered	T19,T5,T15
Phase3St	228	Covered	T19,T5,T15
TerminalSt	244	Covered	T19,T5,T15
TimeoutSt	154	Covered	T19,T5,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T12,T13,T14
IdleSt->Phase0St	147	Covered	T19,T5,T15
IdleSt->TimeoutSt	154	Covered	T19,T5,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T17,T120,T108
Phase0St->Phase1St	193	Covered	T19,T5,T15
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T15,T28,T97
Phase1St->Phase2St	210	Covered	T19,T5,T15
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T27,T121,T58
Phase2St->Phase3St	228	Covered	T19,T5,T15
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T122,T123,T98
Phase3St->TerminalSt	244	Covered	T19,T5,T15
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T19,T5,T15
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T19,T5,T15
TimeoutSt->Phase0St	167	Covered	T19,T8,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T8,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T5,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T120,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T19,T5,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T19,T5,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T28,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T19,T5,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T19,T5,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T121,T58
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T19,T5,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T19,T5,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T122,T123,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T19,T5,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T19,T5,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T5,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T19,T5,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	745477658	277	0	0
CheckAccumTrig0_A	745477658	547	0	0
CheckAccumTrig1_A	745477658	23	0	0
CheckClr_A	745477658	259	0	0
CheckEn_A	745161462	322941513	0	0
CheckPhase0_A	745477658	625	0	0
CheckPhase1_A	745477658	613	0	0
CheckPhase2_A	745477658	598	0	0
CheckPhase3_A	745477658	589	0	0
CheckTimeout0_A	745477658	1288	0	0
CheckTimeoutSt1_A	745477658	109550	0	0
CheckTimeoutSt2_A	745477658	1199	0	0
CheckTimeoutStTrig_A	745477658	66	0	0
ErrorStAllEscAsserted_A	745477658	1453	0	0
ErrorStIsTerminal_A	745477658	1213	0	0
u_state_regs_A	745477658	745305173	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	277	0	0
T12	31243	83	0	0
T13	0	69	0	0
T14	0	49	0	0
T32	0	51	0	0
T33	0	25	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	547	0	0
T4	927536	0	0	0
T5	494415	3	0	0
T7	281041	1	0	0
T8	0	4	0	0
T15	110571	3	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	85556	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	23	0	0
T31	367044	0	0	0
T50	23307	1	0	0
T51	673747	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	1018	0	0	0
T65	200863	0	0	0
T66	160387	0	0	0
T67	764962	0	0	0
T68	168232	0	0	0
T69	2241	0	0	0
T70	80941	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	259	0	0
T4	927536	0	0	0
T5	494415	2	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	2	0	0
T17	0	2	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T27	0	7	0	0
T29	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T71	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745161462	322941513	0	0
T1	350024	346249	0	0
T2	913308	911275	0	0
T3	3731	2018	0	0
T4	927536	925381	0	0
T5	494415	87401	0	0
T6	86491	86409	0	0
T7	281041	3119	0	0
T15	110571	8866	0	0
T19	87607	74765	0	0
T20	104269	104190	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	625	0	0
T4	927536	0	0	0
T5	494415	3	0	0
T7	281041	1	0	0
T8	0	6	0	0
T15	110571	3	0	0
T17	0	2	0	0
T18	0	3	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	85556	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	613	0	0
T4	927536	0	0	0
T5	494415	3	0	0
T7	281041	1	0	0
T8	0	6	0	0
T15	110571	2	0	0
T17	0	2	0	0
T18	0	3	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	85556	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	598	0	0
T4	927536	0	0	0
T5	494415	3	0	0
T7	281041	1	0	0
T8	0	6	0	0
T15	110571	2	0	0
T17	0	2	0	0
T18	0	3	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	85556	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	589	0	0
T4	927536	0	0	0
T5	494415	3	0	0
T7	281041	1	0	0
T8	0	6	0	0
T15	110571	2	0	0
T17	0	2	0	0
T18	0	3	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T43	44983	1	0	0
T44	166760	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	85556	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1288	0	0
T4	927536	0	0	0
T5	494415	1	0	0
T7	281041	0	0	0
T8	0	3	0	0
T15	110571	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	87607	2	0	0
T20	104269	0	0	0
T21	17065	1	0	0
T29	0	1	0	0
T43	44983	4	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T76	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	109550	0	0
T4	927536	0	0	0
T5	494415	30	0	0
T7	281041	0	0	0
T8	0	203	0	0
T15	110571	82	0	0
T17	0	55	0	0
T18	0	706	0	0
T19	87607	236	0	0
T20	104269	0	0	0
T21	17065	197	0	0
T29	0	160	0	0
T43	44983	448	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T76	0	411	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1199	0	0
T4	927536	0	0	0
T5	494415	1	0	0
T7	281041	0	0	0
T8	0	1	0	0
T15	110571	1	0	0
T17	0	2	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	1	0	0
T27	0	4	0	0
T29	0	1	0	0
T43	44983	4	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T76	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	66	0	0
T4	927536	0	0	0
T5	494415	0	0	0
T7	281041	0	0	0
T8	0	2	0	0
T15	110571	0	0	0
T18	0	1	0	0
T19	87607	1	0	0
T20	104269	0	0	0
T21	17065	0	0	0
T25	0	2	0	0
T27	0	6	0	0
T31	0	1	0	0
T43	44983	0	0	0
T44	166760	0	0	0
T47	85556	0	0	0
T57	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T84	0	6	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1453	0	0
T12	31243	379	0	0
T13	0	377	0	0
T14	0	177	0	0
T32	0	338	0	0
T33	0	182	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	1213	0	0
T12	31243	319	0	0
T13	0	317	0	0
T14	0	147	0	0
T32	0	278	0	0
T33	0	152	0	0
T34	39086	0	0	0
T35	37878	0	0	0
T36	502294	0	0	0
T37	898941	0	0	0
T38	189462	0	0	0
T39	128299	0	0	0
T40	490065	0	0	0
T41	167954	0	0	0
T42	883461	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745477658	745305173	0	0
T1	350024	349956	0	0
T2	913308	913235	0	0
T3	3731	3642	0	0
T4	927536	927466	0	0
T5	494415	494409	0	0
T6	86491	86410	0	0
T7	281041	281034	0	0
T15	110571	110563	0	0
T19	87607	87531	0	0
T20	104269	104191	0	0