Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65695428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31807386

1

T1

3222

T2

115692

T3

146093

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14750599	1			T1	1874		T2	45540		T3	56676
values[0x0]	40360003	1			T1	4005		T2	159423		T3	202094
values[0x1]	42392212	1			T1	4010		T2	160031		T3	202698

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56102015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41400799

1

T1

4071

T2

146459

T3

184857

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	304998	1			T1	41		T2	1466		T3	1854
valid_sources[0x01]	306735	1			T1	38		T2	1506		T3	1766
valid_sources[0x02]	719714	1			T1	46		T2	1431		T3	1805
valid_sources[0x03]	316627	1			T1	33		T2	1454		T3	1876
valid_sources[0x04]	690003	1			T1	31		T2	1415		T3	1850
valid_sources[0x05]	306616	1			T1	42		T2	1493		T3	1852
valid_sources[0x06]	319893	1			T1	34		T2	1363		T3	1764
valid_sources[0x07]	306476	1			T1	34		T2	1433		T3	1842
valid_sources[0x08]	321303	1			T1	32		T2	1476		T3	1808
valid_sources[0x09]	311910	1			T1	44		T2	1502		T3	1820
valid_sources[0x0a]	322893	1			T1	32		T2	1465		T3	1774
valid_sources[0x0b]	632556	1			T1	52		T2	1373		T3	1821
valid_sources[0x0c]	307247	1			T1	43		T2	1439		T3	1760
valid_sources[0x0d]	310474	1			T1	50		T2	1395		T3	1862
valid_sources[0x0e]	312447	1			T1	44		T2	1455		T3	1777
valid_sources[0x0f]	717071	1			T1	45		T2	1378		T3	1819
valid_sources[0x10]	309417	1			T1	41		T2	1429		T3	1832
valid_sources[0x11]	779369	1			T1	39		T2	1345		T3	1827
valid_sources[0x12]	320754	1			T1	40		T2	1298		T3	1814
valid_sources[0x13]	321379	1			T1	41		T2	1498		T3	1763
valid_sources[0x14]	504012	1			T1	44		T2	1440		T3	1804
valid_sources[0x15]	308189	1			T1	32		T2	1400		T3	1761
valid_sources[0x16]	312631	1			T1	34		T2	1385		T3	1813
valid_sources[0x17]	298611	1			T1	35		T2	1450		T3	1764
valid_sources[0x18]	314109	1			T1	39		T2	1456		T3	1831
valid_sources[0x19]	742492	1			T1	43		T2	1389		T3	1797
valid_sources[0x1a]	302445	1			T1	39		T2	1459		T3	1741
valid_sources[0x1b]	307888	1			T1	35		T2	1424		T3	1745
valid_sources[0x1c]	1308440	1			T1	38		T2	1441		T3	1832
valid_sources[0x1d]	312175	1			T1	33		T2	1439		T3	1777
valid_sources[0x1e]	301816	1			T1	38		T2	1399		T3	1788
valid_sources[0x1f]	303880	1			T1	44		T2	1457		T3	1739
valid_sources[0x20]	319744	1			T1	42		T2	1387		T3	1828
valid_sources[0x21]	303801	1			T1	31		T2	1383		T3	1857
valid_sources[0x22]	309727	1			T1	36		T2	1393		T3	1821
valid_sources[0x23]	299650	1			T1	39		T2	1403		T3	1876
valid_sources[0x24]	312918	1			T1	43		T2	1410		T3	1754
valid_sources[0x25]	310155	1			T1	35		T2	1368		T3	1823
valid_sources[0x26]	310638	1			T1	37		T2	1485		T3	1792
valid_sources[0x27]	318249	1			T1	39		T2	1445		T3	1726
valid_sources[0x28]	308973	1			T1	35		T2	1419		T3	1816
valid_sources[0x29]	306128	1			T1	41		T2	1417		T3	1824
valid_sources[0x2a]	313984	1			T1	38		T2	1521		T3	1874
valid_sources[0x2b]	306628	1			T1	36		T2	1491		T3	1803
valid_sources[0x2c]	314526	1			T1	33		T2	1406		T3	1788
valid_sources[0x2d]	537648	1			T1	36		T2	1408		T3	1775
valid_sources[0x2e]	301385	1			T1	39		T2	1512		T3	1814
valid_sources[0x2f]	311944	1			T1	38		T2	1383		T3	1784
valid_sources[0x30]	305451	1			T1	37		T2	1393		T3	1787
valid_sources[0x31]	813317	1			T1	38		T2	1411		T3	1798
valid_sources[0x32]	872176	1			T1	36		T2	1389		T3	1843
valid_sources[0x33]	647992	1			T1	45		T2	1348		T3	1802
valid_sources[0x34]	311747	1			T1	36		T2	1438		T3	1847
valid_sources[0x35]	306584	1			T1	31		T2	1382		T3	1853
valid_sources[0x36]	312963	1			T1	45		T2	1411		T3	1841
valid_sources[0x37]	309800	1			T1	35		T2	1449		T3	1786
valid_sources[0x38]	319624	1			T1	38		T2	1365		T3	1770
valid_sources[0x39]	314232	1			T1	43		T2	1454		T3	1801
valid_sources[0x3a]	303880	1			T1	26		T2	1388		T3	1801
valid_sources[0x3b]	309667	1			T1	38		T2	1469		T3	1776
valid_sources[0x3c]	306542	1			T1	43		T2	1414		T3	1754
valid_sources[0x3d]	304618	1			T1	40		T2	1433		T3	1798
valid_sources[0x3e]	751768	1			T1	37		T2	1427		T3	1777
valid_sources[0x3f]	985916	1			T1	46		T2	1383		T3	1793
valid_sources[0x40]	305528	1			T1	34		T2	1478		T3	1753
valid_sources[0x41]	300637	1			T1	32		T2	1428		T3	1784
valid_sources[0x42]	305282	1			T1	39		T2	1417		T3	1774
valid_sources[0x43]	304131	1			T1	38		T2	1411		T3	1804
valid_sources[0x44]	312406	1			T1	27		T2	1440		T3	1742
valid_sources[0x45]	303334	1			T1	36		T2	1424		T3	1780
valid_sources[0x46]	547123	1			T1	43		T2	1443		T3	1863
valid_sources[0x47]	323483	1			T1	40		T2	1330		T3	1786
valid_sources[0x48]	310343	1			T1	39		T2	1393		T3	1782
valid_sources[0x49]	537179	1			T1	39		T2	1392		T3	1786
valid_sources[0x4a]	309451	1			T1	43		T2	1367		T3	1826
valid_sources[0x4b]	317519	1			T1	35		T2	1466		T3	1800
valid_sources[0x4c]	311644	1			T1	39		T2	1398		T3	1830
valid_sources[0x4d]	309173	1			T1	37		T2	1420		T3	1855
valid_sources[0x4e]	337375	1			T1	31		T2	1440		T3	1788
valid_sources[0x4f]	305388	1			T1	38		T2	1427		T3	1847
valid_sources[0x50]	313823	1			T1	28		T2	1460		T3	1810
valid_sources[0x51]	843906	1			T1	31		T2	1396		T3	1803
valid_sources[0x52]	314398	1			T1	47		T2	1482		T3	1832
valid_sources[0x53]	301521	1			T1	38		T2	1334		T3	1795
valid_sources[0x54]	340492	1			T1	46		T2	1397		T3	1801
valid_sources[0x55]	310869	1			T1	25		T2	1457		T3	1818
valid_sources[0x56]	560725	1			T1	32		T2	1385		T3	1767
valid_sources[0x57]	303645	1			T1	44		T2	1428		T3	1824
valid_sources[0x58]	742328	1			T1	35		T2	1440		T3	1834
valid_sources[0x59]	309406	1			T1	37		T2	1405		T3	1815
valid_sources[0x5a]	350738	1			T1	36		T2	1451		T3	1759
valid_sources[0x5b]	541777	1			T1	29		T2	1467		T3	1786
valid_sources[0x5c]	590840	1			T1	39		T2	1430		T3	1837
valid_sources[0x5d]	305888	1			T1	32		T2	1391		T3	1792
valid_sources[0x5e]	306984	1			T1	35		T2	1467		T3	1792
valid_sources[0x5f]	313221	1			T1	33		T2	1369		T3	1737
valid_sources[0x60]	311700	1			T1	33		T2	1394		T3	1772
valid_sources[0x61]	327995	1			T1	38		T2	1463		T3	1796
valid_sources[0x62]	306031	1			T1	40		T2	1400		T3	1812
valid_sources[0x63]	320574	1			T1	33		T2	1522		T3	1765
valid_sources[0x64]	305787	1			T1	39		T2	1470		T3	1759
valid_sources[0x65]	627045	1			T1	39		T2	1448		T3	1811
valid_sources[0x66]	745068	1			T1	44		T2	1402		T3	1856
valid_sources[0x67]	316719	1			T1	40		T2	1392		T3	1792
valid_sources[0x68]	344785	1			T1	40		T2	1420		T3	1761
valid_sources[0x69]	643526	1			T1	39		T2	1423		T3	1772
valid_sources[0x6a]	310496	1			T1	30		T2	1310		T3	1790
valid_sources[0x6b]	633123	1			T1	27		T2	1441		T3	1933
valid_sources[0x6c]	306576	1			T1	40		T2	1416		T3	1800
valid_sources[0x6d]	303192	1			T1	33		T2	1384		T3	1791
valid_sources[0x6e]	320500	1			T1	38		T2	1390		T3	1794
valid_sources[0x6f]	601648	1			T1	56		T2	1352		T3	1762
valid_sources[0x70]	319415	1			T1	26		T2	1471		T3	1743
valid_sources[0x71]	314053	1			T1	45		T2	1341		T3	1845
valid_sources[0x72]	325780	1			T1	42		T2	1506		T3	1852
valid_sources[0x73]	317278	1			T1	36		T2	1416		T3	1777
valid_sources[0x74]	321253	1			T1	42		T2	1512		T3	1791
valid_sources[0x75]	304625	1			T1	34		T2	1406		T3	1888
valid_sources[0x76]	318682	1			T1	40		T2	1445		T3	1828
valid_sources[0x77]	307968	1			T1	40		T2	1417		T3	1843
valid_sources[0x78]	335356	1			T1	25		T2	1425		T3	1820
valid_sources[0x79]	314610	1			T1	33		T2	1441		T3	1718
valid_sources[0x7a]	325586	1			T1	39		T2	1472		T3	1834
valid_sources[0x7b]	379692	1			T1	36		T2	1459		T3	1779
valid_sources[0x7c]	302460	1			T1	39		T2	1462		T3	1850
valid_sources[0x7d]	309183	1			T1	31		T2	1455		T3	1768
valid_sources[0x7e]	305131	1			T1	42		T2	1478		T3	1831
valid_sources[0x7f]	694337	1			T1	36		T2	1443		T3	1816
valid_sources[0x80]	317712	1			T1	35		T2	1512		T3	1748

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7324590

1

T1

899

T2

22838

T3

28377

values[0x0]

all_enables

biggest_size

15453999

1

T1

1502

T2

59399

T3

75256

values[0x1]

all_enables

biggest_size

9028797

1

T1

821

T2

33455

T3

42460