Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T230,T231,T232
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14476	0	0
DisabledNoTrigBkwd_A	2147483647	812312	0	0
DisabledNoTrigFwd_A	2147483647	1503155115	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14476	0	0
T6	580314	0	0	0
T75	176829	0	0	0
T76	30072	0	0	0
T77	60747	0	0	0
T102	15490	0	0	0
T104	531030	0	0	0
T218	0	335	0	0
T224	45388	0	0	0
T230	1478	734	0	0
T231	0	652	0	0
T232	0	362	0	0
T233	0	343	0	0
T234	0	1152	0	0
T235	0	615	0	0
T236	0	354	0	0
T237	3246	945	0	0
T238	0	469	0	0
T239	4154	760	0	0
T240	0	749	0	0
T241	0	870	0	0
T242	0	1493	0	0
T243	0	771	0	0
T244	0	1225	0	0
T245	0	557	0	0
T246	0	715	0	0
T247	0	821	0	0
T248	0	554	0	0
T249	90089	0	0	0
T250	815917	0	0	0
T251	318454	0	0	0
T252	22149	0	0	0
T253	101669	0	0	0
T254	196954	0	0	0
T255	144477	0	0	0
T256	157106	0	0	0
T257	138859	0	0	0
T258	51798	0	0	0
T259	334829	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	812312	0	0
T1	52468	54	0	0
T2	1146440	5337	0	0
T3	1519536	935	0	0
T4	417812	2147	0	0
T12	79420	0	0	0
T13	1515064	3146	0	0
T14	1219000	6884	0	0
T15	49306	0	0	0
T16	0	8569	0	0
T17	0	811	0	0
T18	0	5868	0	0
T19	264352	0	0	0
T20	283316	1	0	0
T21	219788	21	0	0
T42	0	45	0	0
T43	0	210	0	0
T44	0	11	0	0
T45	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1503155115	0	0
T1	104936	56025	0	0
T2	1146440	331249	0	0
T3	1519536	414923	0	0
T4	417812	315652	0	0
T12	79420	2932	0	0
T13	1515064	778011	0	0
T14	1219000	310620	0	0
T19	264352	193456	0	0
T20	283316	253895	0	0
T21	219788	167873	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T230,T232,T233
1	1	Covered	T2,T3,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682582373	3760	0	0
DisabledNoTrigBkwd_A	682582373	251112	0	0
DisabledNoTrigFwd_A	682582373	343916449	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	3760	0	0
T6	580314	0	0	0
T75	176829	0	0	0
T76	30072	0	0	0
T77	60747	0	0	0
T102	15490	0	0	0
T224	45388	0	0	0
T230	1478	734	0	0
T232	0	362	0	0
T233	0	343	0	0
T234	0	1152	0	0
T235	0	615	0	0
T248	0	554	0	0
T249	90089	0	0	0
T250	815917	0	0	0
T251	318454	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	251112	0	0
T2	286610	1905	0	0
T3	379884	932	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	1387	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	2039	0	0
T17	0	29	0	0
T18	0	4183	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0
T42	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	343916449	0	0
T1	26234	26147	0	0
T2	286610	13610	0	0
T3	379884	15674	0	0
T4	104453	103553	0	0
T12	19855	727	0	0
T13	378766	10990	0	0
T14	304750	304313	0	0
T19	66088	60589	0	0
T20	70829	60253	0	0
T21	54947	50507	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T19,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T239,T241,T242
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682582373	4501	0	0
DisabledNoTrigBkwd_A	682582373	197604	0	0
DisabledNoTrigFwd_A	682582373	390100920	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	4501	0	0
T104	531030	0	0	0
T239	4154	760	0	0
T241	0	870	0	0
T242	0	1493	0	0
T245	0	557	0	0
T247	0	821	0	0
T252	22149	0	0	0
T253	101669	0	0	0
T254	196954	0	0	0
T255	144477	0	0	0
T256	157106	0	0	0
T257	138859	0	0	0
T258	51798	0	0	0
T259	334829	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	197604	0	0
T1	26234	36	0	0
T2	286610	1643	0	0
T3	379884	3	0	0
T4	104453	2146	0	0
T12	19855	0	0	0
T13	378766	1754	0	0
T14	304750	2039	0	0
T16	0	2	0	0
T17	0	281	0	0
T18	0	1326	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	390100920	0	0
T1	26234	586	0	0
T2	286610	14923	0	0
T3	379884	10108	0	0
T4	104453	3205	0	0
T12	19855	731	0	0
T13	378766	11001	0	0
T14	304750	2089	0	0
T19	66088	65989	0	0
T20	70829	57245	0	0
T21	54947	42411	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T237,T238,T244
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682582373	2639	0	0
DisabledNoTrigBkwd_A	682582373	160992	0	0
DisabledNoTrigFwd_A	682582373	392391764	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	2639	0	0
T108	261537	0	0	0
T237	3246	945	0	0
T238	0	469	0	0
T244	0	1225	0	0
T260	15804	0	0	0
T261	24338	0	0	0
T262	58059	0	0	0
T263	72391	0	0	0
T264	7463	0	0	0
T265	16091	0	0	0
T266	118589	0	0	0
T267	22992	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	160992	0	0
T1	26234	18	0	0
T2	286610	18	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	2004	0	0
T16	0	2	0	0
T17	0	501	0	0
T18	0	356	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	2	0	0
T42	0	5	0	0
T43	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	392391764	0	0
T1	26234	3145	0	0
T2	286610	283345	0	0
T3	379884	379019	0	0
T4	104453	104447	0	0
T12	19855	735	0	0
T13	378766	378059	0	0
T14	304750	2104	0	0
T19	66088	889	0	0
T20	70829	65665	0	0
T21	54947	39344	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T19
1	1	Covered	T2,T21,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T231,T236,T240
1	1	Covered	T2,T21,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T21,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	682582373	3576	0	0
DisabledNoTrigBkwd_A	682582373	202604	0	0
DisabledNoTrigFwd_A	682582373	376745982	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	3576	0	0
T8	109970	0	0	0
T78	263094	0	0	0
T81	18018	0	0	0
T93	146944	0	0	0
T94	205003	0	0	0
T117	71958	0	0	0
T118	41461	0	0	0
T218	0	335	0	0
T231	1395	652	0	0
T236	0	354	0	0
T240	0	749	0	0
T243	0	771	0	0
T246	0	715	0	0
T268	10709	0	0	0
T269	27439	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	202604	0	0
T2	286610	1771	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	3	0	0
T14	304750	2841	0	0
T15	24653	0	0	0
T16	0	6526	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	15	0	0
T42	0	20	0	0
T43	0	208	0	0
T44	0	11	0	0
T45	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	376745982	0	0
T1	26234	26147	0	0
T2	286610	19371	0	0
T3	379884	10122	0	0
T4	104453	104447	0	0
T12	19855	739	0	0
T13	378766	377961	0	0
T14	304750	2114	0	0
T19	66088	65989	0	0
T20	70829	70732	0	0
T21	54947	35611	0	0