Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T20,T21
1	0	1	Covered	T3,T19,T4
1	1	0	Covered	T1,T20,T13
1	1	1	Covered	T20,T13,T16

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T13,T16
0	1	Covered	T20,T18,T23
1	0	Covered	T20,T13,T18

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T13,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T20,T13,T18

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T13,T16
1	0	Covered	T24,T25
1	1	Covered	T20,T18,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T21

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T20

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T13

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T21,T13

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T20,T13,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T20,T13,T16
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T17,T18,T26
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T14,T26,T27
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T18,T28,T29
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T20,T17,T30
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T4,T13,T14
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T20,T16,T17
TimeoutSt->Phase0St	167	Covered	T20,T13,T18

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T16,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T18,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T26,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T17,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T13,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1108	0	0
CheckAccumTrig0_A	2147483647	2411	0	0
CheckAccumTrig1_A	2147483647	132	0	0
CheckClr_A	2147483647	1176	0	0
CheckEn_A	2147483647	1183290374	0	0
CheckPhase0_A	2147483647	2756	0	0
CheckPhase1_A	2147483647	2695	0	0
CheckPhase2_A	2147483647	2640	0	0
CheckPhase3_A	2147483647	2590	0	0
CheckTimeout0_A	2147483647	3337	0	0
CheckTimeoutSt1_A	2147483647	389687	0	0
CheckTimeoutSt2_A	2147483647	2939	0	0
CheckTimeoutStTrig_A	2147483647	258	0	0
ErrorStAllEscAsserted_A	2147483647	5757	0	0
ErrorStIsTerminal_A	2147483647	4797	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1108	0	0
T9	160524	307	0	0
T10	0	241	0	0
T11	0	270	0	0
T31	0	142	0	0
T32	0	148	0	0
T33	126068	0	0	0
T34	847228	0	0	0
T35	2696992	0	0	0
T36	478988	0	0	0
T37	190140	0	0	0
T38	157740	0	0	0
T39	1903580	0	0	0
T40	114508	0	0	0
T41	601052	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2411	0	0
T1	52468	2	0	0
T2	1146440	4	0	0
T3	1519536	2	0	0
T4	417812	2	0	0
T12	79420	0	0	0
T13	1515064	4	0	0
T14	1219000	7	0	0
T15	49306	0	0	0
T16	0	6	0	0
T17	0	12	0	0
T18	0	19	0	0
T19	264352	0	0	0
T20	283316	0	0	0
T21	219788	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	132	0	0
T5	878384	0	0	0
T13	757532	2	0	0
T14	609500	0	0	0
T15	49306	0	0	0
T16	220424	0	0	0
T17	725940	0	0	0
T18	871360	1	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T27	292657	2	0	0
T28	464982	0	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	188766	0	0	0
T43	842438	0	0	0
T44	443616	0	0	0
T47	0	1	0	0
T48	543529	1	0	0
T49	131675	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	127906	0	0	0
T63	59198	0	0	0
T64	462958	0	0	0
T65	177540	0	0	0
T66	109274	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1176	0	0
T4	104453	1	0	0
T5	2635152	0	0	0
T12	19855	0	0	0
T13	1515064	3	0	0
T14	1219000	4	0	0
T15	98612	0	0	0
T16	440848	3	0	0
T17	1451880	8	0	0
T18	1742720	10	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	1	0	0
T26	0	3	0	0
T30	0	1	0	0
T42	283149	0	0	0
T43	1263657	0	0	0
T44	1330848	3	0	0
T46	0	2	0	0
T47	0	4	0	0
T49	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	4	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1183290374	0	0
T1	104936	53468	0	0
T2	1146440	24744	0	0
T3	1519536	414922	0	0
T4	417812	313066	0	0
T12	79420	2928	0	0
T13	1515064	776908	0	0
T14	1219000	310620	0	0
T19	264352	193453	0	0
T20	283316	210650	0	0
T21	219788	17779	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2756	0	0
T1	52468	2	0	0
T2	1146440	4	0	0
T3	1519536	2	0	0
T4	417812	2	0	0
T12	79420	0	0	0
T13	1515064	6	0	0
T14	1219000	7	0	0
T15	49306	0	0	0
T16	0	7	0	0
T17	0	11	0	0
T18	0	19	0	0
T19	264352	0	0	0
T20	283316	2	0	0
T21	219788	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2695	0	0
T1	52468	2	0	0
T2	1146440	4	0	0
T3	1519536	2	0	0
T4	417812	2	0	0
T12	79420	0	0	0
T13	1515064	6	0	0
T14	1219000	6	0	0
T15	49306	0	0	0
T16	0	7	0	0
T17	0	11	0	0
T18	0	19	0	0
T19	264352	0	0	0
T20	283316	2	0	0
T21	219788	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2640	0	0
T1	52468	2	0	0
T2	1146440	4	0	0
T3	1519536	2	0	0
T4	417812	2	0	0
T12	79420	0	0	0
T13	1515064	6	0	0
T14	1219000	6	0	0
T15	49306	0	0	0
T16	0	7	0	0
T17	0	11	0	0
T18	0	18	0	0
T19	264352	0	0	0
T20	283316	2	0	0
T21	219788	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2590	0	0
T1	52468	2	0	0
T2	1146440	4	0	0
T3	1519536	2	0	0
T4	417812	2	0	0
T12	79420	0	0	0
T13	1515064	6	0	0
T14	1219000	6	0	0
T15	49306	0	0	0
T16	0	7	0	0
T17	0	9	0	0
T18	0	18	0	0
T19	264352	0	0	0
T20	283316	1	0	0
T21	219788	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	5	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3337	0	0
T5	1756768	0	0	0
T13	757532	2	0	0
T14	609500	0	0	0
T15	49306	0	0	0
T16	330636	2	0	0
T17	1451880	6	0	0
T18	1742720	43	0	0
T20	141658	3	0	0
T21	109894	0	0	0
T23	0	18	0	0
T27	0	1	0	0
T28	0	21	0	0
T42	377532	1	0	0
T43	1684876	0	0	0
T44	887232	0	0	0
T45	104682	1	0	0
T47	77042	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T69	0	1	0	0
T73	16610	2	0	0
T74	0	16	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	254350	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	389687	0	0
T5	1756768	0	0	0
T13	757532	8	0	0
T14	609500	0	0	0
T15	49306	0	0	0
T16	330636	72	0	0
T17	1451880	1371	0	0
T18	1742720	3581	0	0
T20	141658	223	0	0
T21	109894	0	0	0
T23	0	2893	0	0
T27	0	4	0	0
T28	0	2405	0	0
T42	377532	653	0	0
T43	1684876	0	0	0
T44	887232	0	0	0
T45	104682	11	0	0
T47	77042	197	0	0
T48	0	286	0	0
T49	0	7	0	0
T69	0	371	0	0
T73	16610	156	0	0
T74	0	1133	0	0
T75	0	243	0	0
T76	0	440	0	0
T77	0	1346	0	0
T78	0	219	0	0
T79	0	22	0	0
T80	254350	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2939	0	0
T5	2635152	0	0	0
T13	378766	0	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	220424	1	0	0
T17	1088910	6	0	0
T18	1742720	25	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	9	0	0
T27	0	6	0	0
T28	0	21	0	0
T42	377532	0	0	0
T43	1684876	0	0	0
T44	1330848	0	0	0
T45	157023	0	0	0
T47	115563	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	3	0	0
T73	24915	2	0	0
T74	29974	11	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	8	0	0
T79	0	1	0	0
T80	508700	0	0	0
T81	0	3	0	0
T82	0	2	0	0
T83	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258	0	0
T5	878384	0	0	0
T13	378766	0	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	0	0	0
T18	871360	2	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T29	0	4	0	0
T38	0	1	0	0
T42	188766	0	0	0
T43	842438	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T69	0	1	0	0
T73	8305	0	0	0
T74	29974	0	0	0
T78	263094	1	0	0
T80	254350	0	0	0
T81	18018	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	6	0	0
T89	0	3	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	146944	0	0	0
T94	205003	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5757	0	0
T9	160524	1414	0	0
T10	0	1409	0	0
T11	0	1469	0	0
T31	0	716	0	0
T32	0	749	0	0
T33	126068	0	0	0
T34	847228	0	0	0
T35	2696992	0	0	0
T36	478988	0	0	0
T37	190140	0	0	0
T38	157740	0	0	0
T39	1903580	0	0	0
T40	114508	0	0	0
T41	601052	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4797	0	0
T9	160524	1174	0	0
T10	0	1169	0	0
T11	0	1229	0	0
T31	0	596	0	0
T32	0	629	0	0
T33	126068	0	0	0
T34	847228	0	0	0
T35	2696992	0	0	0
T36	478988	0	0	0
T37	190140	0	0	0
T38	157740	0	0	0
T39	1903580	0	0	0
T40	114508	0	0	0
T41	601052	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104936	104588	0	0
T2	1146440	1146400	0	0
T3	1519536	1519500	0	0
T4	417812	417788	0	0
T12	79420	78992	0	0
T13	1515064	1515024	0	0
T14	1219000	1218972	0	0
T19	264352	263956	0	0
T20	283316	282928	0	0
T21	219788	219528	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T20,T21
1	0	1	Covered	T21,T43,T44
1	1	0	Covered	T20,T16,T17
1	1	1	Covered	T20,T13,T16

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T13,T16
0	1	Covered	T20,T18,T23
1	0	Covered	T13,T47,T50

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T13,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T47,T50

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T13,T16
1	0	Not Covered
1	1	Covered	T20,T18,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T21,T13

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T16,T44

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T13

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T42,T46

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T21,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T14,T17,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T20,T13,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T20,T13,T16
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T17,T26,T51
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T95,T96
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T92,T97
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T17,T28,T98
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T13,T16,T17
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T16,T17,T18
TimeoutSt->Phase0St	167	Covered	T20,T13,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T26,T51
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T95,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T92,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T28,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T16,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682582373	281	0	0
CheckAccumTrig0_A	682582373	510	0	0
CheckAccumTrig1_A	682582373	21	0	0
CheckClr_A	682582373	227	0	0
CheckEn_A	682339515	314014669	0	0
CheckPhase0_A	682582373	581	0	0
CheckPhase1_A	682582373	568	0	0
CheckPhase2_A	682582373	559	0	0
CheckPhase3_A	682582373	552	0	0
CheckTimeout0_A	682582373	527	0	0
CheckTimeoutSt1_A	682582373	65470	0	0
CheckTimeoutSt2_A	682582373	441	0	0
CheckTimeoutStTrig_A	682582373	64	0	0
ErrorStAllEscAsserted_A	682582373	1463	0	0
ErrorStIsTerminal_A	682582373	1223	0	0
u_state_regs_A	682582373	682408176	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	281	0	0
T9	40131	90	0	0
T10	0	55	0	0
T11	0	55	0	0
T31	0	35	0	0
T32	0	46	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	510	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	2	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	21	0	0
T5	878384	0	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	0	0	0
T18	435680	0	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T56	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	227	0	0
T5	878384	0	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	1	0	0
T17	362970	8	0	0
T18	435680	1	0	0
T23	0	1	0	0
T26	0	3	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682339515	314014669	0	0
T1	26234	586	0	0
T2	286610	1983	0	0
T3	379884	10108	0	0
T4	104453	619	0	0
T12	19855	730	0	0
T13	378766	11001	0	0
T14	304750	2089	0	0
T19	66088	65988	0	0
T20	70829	14003	0	0
T21	54947	6307	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	581	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	568	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	559	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	1	0	0
T16	0	1	0	0
T17	0	9	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	552	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	1	0	0
T16	0	1	0	0
T17	0	7	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	527	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	1	0	0
T17	362970	2	0	0
T18	435680	18	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T47	0	1	0	0
T73	0	1	0	0
T74	0	7	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	65470	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	62	0	0
T17	362970	627	0	0
T18	435680	1232	0	0
T20	70829	65	0	0
T21	54947	0	0	0
T23	0	13	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T73	0	78	0	0
T74	0	474	0	0
T75	0	122	0	0
T77	0	912	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	441	0	0
T5	878384	0	0	0
T16	110212	1	0	0
T17	362970	2	0	0
T18	435680	17	0	0
T27	0	6	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T49	0	1	0	0
T73	8305	1	0	0
T74	0	7	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	64	0	0
T13	378766	0	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	0	0	0
T18	435680	1	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	1	0	0
T38	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T51	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1463	0	0
T9	40131	345	0	0
T10	0	355	0	0
T11	0	375	0	0
T31	0	182	0	0
T32	0	206	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1223	0	0
T9	40131	285	0	0
T10	0	295	0	0
T11	0	315	0	0
T31	0	152	0	0
T32	0	176	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	682408176	0	0
T1	26234	26147	0	0
T2	286610	286600	0	0
T3	379884	379875	0	0
T4	104453	104447	0	0
T12	19855	19748	0	0
T13	378766	378756	0	0
T14	304750	304743	0	0
T19	66088	65989	0	0
T20	70829	70732	0	0
T21	54947	54882	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T13,T16
1	0	1	Covered	T3,T19,T4
1	1	0	Covered	T1,T20,T13
1	1	1	Covered	T20,T13,T17

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T13,T17
0	1	Covered	T18,T69,T48
1	0	Covered	T20,T13,T18

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T13,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T13,T18

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T13,T17
1	0	Not Covered
1	1	Covered	T18,T69,T48

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T4,T21,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T20,T13,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T2,T13,T16

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T20
1	Covered	T3,T18,T47

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T20,T21,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T21,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T20,T13,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T20,T13,T17
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T18,T99,T100
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T27,T35,T101
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T18,T28,T29
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T20,T27,T90
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T13,T16
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T20,T17,T18
TimeoutSt->Phase0St	167	Covered	T20,T13,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T13,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T18,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T35,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T27,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T13,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682582373	267	0	0
CheckAccumTrig0_A	682582373	921	0	0
CheckAccumTrig1_A	682582373	64	0	0
CheckClr_A	682582373	495	0	0
CheckEn_A	682339515	258448175	0	0
CheckPhase0_A	682582373	1026	0	0
CheckPhase1_A	682582373	1001	0	0
CheckPhase2_A	682582373	972	0	0
CheckPhase3_A	682582373	949	0	0
CheckTimeout0_A	682582373	952	0	0
CheckTimeoutSt1_A	682582373	115421	0	0
CheckTimeoutSt2_A	682582373	821	0	0
CheckTimeoutStTrig_A	682582373	62	0	0
ErrorStAllEscAsserted_A	682582373	1476	0	0
ErrorStIsTerminal_A	682582373	1236	0	0
u_state_regs_A	682582373	682408176	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	267	0	0
T9	40131	72	0	0
T10	0	72	0	0
T11	0	57	0	0
T31	0	31	0	0
T32	0	35	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	921	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T44	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	64	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	0	0	0
T18	435680	1	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T27	0	1	0	0
T35	0	1	0	0
T41	0	2	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T48	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	495	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	2	0	0
T17	362970	0	0	0
T18	435680	7	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T68	0	3	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682339515	258448175	0	0
T1	26234	26146	0	0
T2	286610	6008	0	0
T3	379884	15674	0	0
T4	104453	103553	0	0
T12	19855	726	0	0
T13	378766	10990	0	0
T14	304750	304313	0	0
T19	66088	60588	0	0
T20	70829	60252	0	0
T21	54947	6293	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1026	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	13	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1001	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	13	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	972	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	66088	0	0	0
T20	70829	1	0	0
T21	54947	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	949	0	0
T2	286610	1	0	0
T3	379884	1	0	0
T4	104453	1	0	0
T12	19855	0	0	0
T13	378766	2	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T44	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	952	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	1	0	0
T18	435680	9	0	0
T20	70829	2	0	0
T21	54947	0	0	0
T23	0	9	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T47	0	1	0	0
T69	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	115421	0	0
T13	378766	7	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	45	0	0
T18	435680	832	0	0
T20	70829	158	0	0
T21	54947	0	0	0
T23	0	1446	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T47	0	197	0	0
T69	0	371	0	0
T73	0	78	0	0
T74	0	223	0	0
T77	0	434	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	821	0	0
T13	378766	0	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	1	0	0
T18	435680	7	0	0
T20	70829	1	0	0
T21	54947	0	0	0
T23	0	9	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T47	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0
T77	0	1	0	0
T81	0	3	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	62	0	0
T5	878384	0	0	0
T18	435680	1	0	0
T24	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	2	0	0
T50	0	2	0	0
T69	0	1	0	0
T73	8305	0	0	0
T74	29974	0	0	0
T80	254350	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1476	0	0
T9	40131	368	0	0
T10	0	375	0	0
T11	0	366	0	0
T31	0	178	0	0
T32	0	189	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1236	0	0
T9	40131	308	0	0
T10	0	315	0	0
T11	0	306	0	0
T31	0	148	0	0
T32	0	159	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	682408176	0	0
T1	26234	26147	0	0
T2	286610	286600	0	0
T3	379884	379875	0	0
T4	104453	104447	0	0
T12	19855	19748	0	0
T13	378766	378756	0	0
T14	304750	304743	0	0
T19	66088	65989	0	0
T20	70829	70732	0	0
T21	54947	54882	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T21

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T20,T13
1	0	1	Covered	T3,T19,T43
1	1	0	Covered	T20,T13,T16
1	1	1	Covered	T17,T18,T74

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T74
0	1	Covered	T78,T24,T29
1	0	Covered	T27,T49,T56

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T74
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T49,T56

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T74
1	0	Covered	T25
1	1	Covered	T78,T24,T29

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T21,T17,T42

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T21,T13,T17
1	Covered	T1,T2,T14

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T44,T75,T102

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T13,T18,T46

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T13,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T14,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T21,T16,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T21
Phase1St	193	Covered	T1,T2,T21
Phase2St	210	Covered	T1,T2,T21
Phase3St	228	Covered	T1,T2,T21
TerminalSt	244	Covered	T1,T2,T21
TimeoutSt	154	Covered	T17,T18,T74

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T21
IdleSt->TimeoutSt	154	Covered	T17,T18,T74
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T29,T57,T103
Phase0St->Phase1St	193	Covered	T1,T2,T21
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14,T71,T57
Phase1St->Phase2St	210	Covered	T1,T2,T21
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T57,T104,T105
Phase2St->Phase3St	228	Covered	T1,T2,T21
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T106,T61,T107
Phase3St->TerminalSt	244	Covered	T1,T2,T21
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T13,T14,T17
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T18,T74
TimeoutSt->Phase0St	167	Covered	T78,T27,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T74
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T78,T27,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T74
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T57,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T71,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T57,T104,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T106,T61,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T14,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682582373	297	0	0
CheckAccumTrig0_A	682582373	504	0	0
CheckAccumTrig1_A	682582373	24	0	0
CheckClr_A	682582373	232	0	0
CheckEn_A	682339515	316324223	0	0
CheckPhase0_A	682582373	585	0	0
CheckPhase1_A	682582373	571	0	0
CheckPhase2_A	682582373	562	0	0
CheckPhase3_A	682582373	556	0	0
CheckTimeout0_A	682582373	1033	0	0
CheckTimeoutSt1_A	682582373	109603	0	0
CheckTimeoutSt2_A	682582373	944	0	0
CheckTimeoutStTrig_A	682582373	63	0	0
ErrorStAllEscAsserted_A	682582373	1416	0	0
ErrorStIsTerminal_A	682582373	1176	0	0
u_state_regs_A	682582373	682408176	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	297	0	0
T9	40131	69	0	0
T10	0	62	0	0
T11	0	85	0	0
T31	0	50	0	0
T32	0	31	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	504	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	5	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	24	0	0
T27	292657	1	0	0
T28	464982	0	0	0
T48	543529	0	0	0
T49	131675	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	127906	0	0	0
T63	59198	0	0	0
T64	462958	0	0	0
T65	177540	0	0	0
T66	109274	0	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	9054	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	232	0	0
T5	878384	0	0	0
T13	378766	1	0	0
T14	304750	4	0	0
T15	24653	0	0	0
T16	110212	0	0	0
T17	362970	0	0	0
T18	435680	2	0	0
T29	0	4	0	0
T30	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T49	0	1	0	0
T65	0	1	0	0
T70	0	1	0	0
T71	0	4	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682339515	316324223	0	0
T1	26234	590	0	0
T2	286610	6027	0	0
T3	379884	379018	0	0
T4	104453	104447	0	0
T12	19855	734	0	0
T13	378766	377856	0	0
T14	304750	2104	0	0
T19	66088	889	0	0
T20	70829	65664	0	0
T21	54947	2581	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	585	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	5	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	571	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	562	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	556	0	0
T1	26234	1	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	4	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1033	0	0
T5	878384	0	0	0
T17	362970	3	0	0
T18	435680	1	0	0
T27	0	1	0	0
T28	0	21	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T73	8305	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	254350	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	109603	0	0
T5	878384	0	0	0
T17	362970	699	0	0
T18	435680	64	0	0
T27	0	4	0	0
T28	0	2405	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	286	0	0
T49	0	7	0	0
T73	8305	0	0	0
T74	0	69	0	0
T76	0	350	0	0
T78	0	219	0	0
T79	0	22	0	0
T80	254350	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	944	0	0
T5	878384	0	0	0
T17	362970	3	0	0
T18	435680	1	0	0
T28	0	21	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	2	0	0
T51	0	3	0	0
T73	8305	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	254350	0	0	0
T83	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	63	0	0
T24	0	1	0	0
T29	0	4	0	0
T30	556257	0	0	0
T41	0	4	0	0
T57	0	2	0	0
T78	263094	1	0	0
T81	18018	0	0	0
T82	62463	0	0	0
T88	0	5	0	0
T89	0	2	0	0
T92	0	1	0	0
T93	146944	0	0	0
T94	205003	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	71958	0	0	0
T118	41461	0	0	0
T119	2712	0	0	0
T120	188064	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1416	0	0
T9	40131	344	0	0
T10	0	343	0	0
T11	0	378	0	0
T31	0	180	0	0
T32	0	171	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1176	0	0
T9	40131	284	0	0
T10	0	283	0	0
T11	0	318	0	0
T31	0	150	0	0
T32	0	141	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	682408176	0	0
T1	26234	26147	0	0
T2	286610	286600	0	0
T3	379884	379875	0	0
T4	104453	104447	0	0
T12	19855	19748	0	0
T13	378766	378756	0	0
T14	304750	304743	0	0
T19	66088	65989	0	0
T20	70829	70732	0	0
T21	54947	54882	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T21,T13
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T21,T13

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T21,T13

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T16,T17
1	0	1	Covered	T14,T18,T43
1	1	0	Covered	T1,T20,T13
1	1	1	Covered	T16,T18,T42

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T42
0	1	Covered	T18,T42,T76
1	0	Covered	T16,T102,T30

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T18,T42
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T102,T30

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T42
1	0	Covered	T24
1	1	Covered	T18,T42,T76

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T16,T18
1	Covered	T2,T21,T13

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T13
1	Covered	T14,T42,T44

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T13
1	Covered	T16,T18,T45

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T13
1	Covered	T18,T43,T46

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T21,T16,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T14,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T21,T13,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T21,T16,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T21,T13
Phase1St	193	Covered	T2,T21,T13
Phase2St	210	Covered	T2,T21,T13
Phase3St	228	Covered	T2,T21,T13
TerminalSt	244	Covered	T2,T21,T13
TimeoutSt	154	Covered	T16,T18,T42

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T21,T13
IdleSt->TimeoutSt	154	Covered	T16,T18,T42
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T56,T121
Phase0St->Phase1St	193	Covered	T2,T21,T13
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T122,T123
Phase1St->Phase2St	210	Covered	T2,T21,T13
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T124,T125,T126
Phase2St->Phase3St	228	Covered	T2,T21,T13
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T30,T127,T29
Phase3St->TerminalSt	244	Covered	T2,T21,T13
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T13,T16,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T18,T45,T74
TimeoutSt->Phase0St	167	Covered	T16,T18,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T42
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T18,T42
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T45,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T121,T128
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T21,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T21,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T122,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T21,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T21,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T124,T125,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T21,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T21,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T127,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T21,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T21,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T16,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T21,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	682582373	263	0	0
CheckAccumTrig0_A	682582373	476	0	0
CheckAccumTrig1_A	682582373	23	0	0
CheckClr_A	682582373	222	0	0
CheckEn_A	682339515	294503307	0	0
CheckPhase0_A	682582373	564	0	0
CheckPhase1_A	682582373	555	0	0
CheckPhase2_A	682582373	547	0	0
CheckPhase3_A	682582373	533	0	0
CheckTimeout0_A	682582373	825	0	0
CheckTimeoutSt1_A	682582373	99193	0	0
CheckTimeoutSt2_A	682582373	733	0	0
CheckTimeoutStTrig_A	682582373	69	0	0
ErrorStAllEscAsserted_A	682582373	1402	0	0
ErrorStIsTerminal_A	682582373	1162	0	0
u_state_regs_A	682582373	682408176	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	263	0	0
T9	40131	76	0	0
T10	0	52	0	0
T11	0	73	0	0
T31	0	26	0	0
T32	0	36	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	476	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T15	24653	0	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	23	0	0
T5	878384	0	0	0
T16	110212	1	0	0
T17	362970	0	0	0
T18	435680	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T48	0	1	0	0
T56	0	1	0	0
T73	8305	0	0	0
T102	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	222	0	0
T5	878384	0	0	0
T6	0	1	0	0
T13	378766	1	0	0
T14	304750	0	0	0
T15	24653	0	0	0
T16	110212	1	0	0
T17	362970	0	0	0
T18	435680	1	0	0
T26	0	7	0	0
T30	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	1	0	0
T45	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682339515	294503307	0	0
T1	26234	26146	0	0
T2	286610	10726	0	0
T3	379884	10122	0	0
T4	104453	104447	0	0
T12	19855	738	0	0
T13	378766	377061	0	0
T14	304750	2114	0	0
T19	66088	65988	0	0
T20	70829	70731	0	0
T21	54947	2598	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	564	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T15	24653	0	0	0
T16	0	2	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	555	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T15	24653	0	0	0
T16	0	2	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	547	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T15	24653	0	0	0
T16	0	2	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	533	0	0
T2	286610	1	0	0
T3	379884	0	0	0
T4	104453	0	0	0
T12	19855	0	0	0
T13	378766	1	0	0
T14	304750	1	0	0
T15	24653	0	0	0
T16	0	2	0	0
T18	0	3	0	0
T19	66088	0	0	0
T20	70829	0	0	0
T21	54947	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	825	0	0
T5	878384	0	0	0
T16	110212	1	0	0
T17	362970	0	0	0
T18	435680	15	0	0
T23	0	8	0	0
T42	94383	1	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	1	0	0
T47	38521	0	0	0
T73	8305	0	0	0
T74	0	5	0	0
T75	0	1	0	0
T76	0	1	0	0
T102	0	1	0	0
T129	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	99193	0	0
T5	878384	0	0	0
T16	110212	10	0	0
T17	362970	0	0	0
T18	435680	1453	0	0
T23	0	1434	0	0
T42	94383	653	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	11	0	0
T47	38521	0	0	0
T73	8305	0	0	0
T74	0	367	0	0
T75	0	121	0	0
T76	0	90	0	0
T102	0	4	0	0
T129	0	71	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	733	0	0
T5	878384	0	0	0
T18	435680	14	0	0
T23	0	8	0	0
T30	0	1	0	0
T42	94383	0	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	1	0	0
T47	38521	0	0	0
T73	8305	0	0	0
T74	29974	5	0	0
T75	0	1	0	0
T78	0	2	0	0
T80	254350	0	0	0
T82	0	2	0	0
T129	0	1	0	0
T130	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	69	0	0
T5	878384	0	0	0
T18	435680	1	0	0
T42	94383	1	0	0
T43	421219	0	0	0
T44	443616	0	0	0
T45	52341	0	0	0
T47	38521	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T73	8305	0	0	0
T74	29974	0	0	0
T76	0	1	0	0
T80	254350	0	0	0
T86	0	1	0	0
T92	0	1	0	0
T120	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1402	0	0
T9	40131	357	0	0
T10	0	336	0	0
T11	0	350	0	0
T31	0	176	0	0
T32	0	183	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	1162	0	0
T9	40131	297	0	0
T10	0	276	0	0
T11	0	290	0	0
T31	0	146	0	0
T32	0	153	0	0
T33	31517	0	0	0
T34	211807	0	0	0
T35	674248	0	0	0
T36	119747	0	0	0
T37	47535	0	0	0
T38	39435	0	0	0
T39	475895	0	0	0
T40	28627	0	0	0
T41	150263	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682582373	682408176	0	0
T1	26234	26147	0	0
T2	286610	286600	0	0
T3	379884	379875	0	0
T4	104453	104447	0	0
T12	19855	19748	0	0
T13	378766	378756	0	0
T14	304750	304743	0	0
T19	66088	65989	0	0
T20	70829	70732	0	0
T21	54947	54882	0	0