Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62583564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30333597

1

T1

2804

T2

6760

T3

2060

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14058562	1			T1	1088		T2	2668		T3	1631
values[0x0]	38432952	1			T1	3784		T2	9982		T3	2110
values[0x1]	40425647	1			T1	3832		T2	10260		T3	2102

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53414412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39502749

1

T1

3534

T2

8747

T3

2553

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	303114	1			T2	116		T3	15		T7	6
valid_sources[0x01]	303990	1			T2	92		T3	22		T7	10
valid_sources[0x02]	302723	1			T2	73		T3	16		T7	5
valid_sources[0x03]	320563	1			T2	97		T3	22		T7	4
valid_sources[0x04]	302961	1			T2	100		T3	32		T7	9
valid_sources[0x05]	702011	1			T2	81		T3	23		T7	11
valid_sources[0x06]	308462	1			T2	84		T3	16		T7	5
valid_sources[0x07]	301186	1			T2	107		T3	28		T7	6
valid_sources[0x08]	313508	1			T2	79		T3	15		T7	9
valid_sources[0x09]	318079	1			T2	74		T3	17		T7	11
valid_sources[0x0a]	509599	1			T2	106		T3	19		T7	8
valid_sources[0x0b]	321471	1			T2	90		T3	23		T7	3
valid_sources[0x0c]	339469	1			T2	100		T3	25		T7	7
valid_sources[0x0d]	303844	1			T2	99		T3	23		T7	6
valid_sources[0x0e]	313012	1			T2	85		T3	14		T7	9
valid_sources[0x0f]	313092	1			T2	94		T3	37		T7	5
valid_sources[0x10]	311315	1			T2	79		T3	19		T7	8
valid_sources[0x11]	310692	1			T2	78		T3	27		T7	8
valid_sources[0x12]	318544	1			T2	83		T3	24		T7	9
valid_sources[0x13]	313260	1			T2	83		T3	33		T7	4
valid_sources[0x14]	314009	1			T2	109		T3	19		T7	9
valid_sources[0x15]	595181	1			T2	93		T3	18		T7	7
valid_sources[0x16]	318281	1			T2	76		T3	28		T7	9
valid_sources[0x17]	303446	1			T2	94		T3	23		T7	8
valid_sources[0x18]	304387	1			T2	84		T3	11		T7	3
valid_sources[0x19]	331394	1			T2	90		T3	17		T7	8
valid_sources[0x1a]	308005	1			T2	87		T3	32		T7	7
valid_sources[0x1b]	650499	1			T2	88		T3	25		T7	9
valid_sources[0x1c]	305633	1			T2	92		T3	27		T7	7
valid_sources[0x1d]	348135	1			T2	72		T3	16		T7	9
valid_sources[0x1e]	344292	1			T2	94		T3	34		T7	5
valid_sources[0x1f]	313810	1			T2	78		T3	18		T7	5
valid_sources[0x20]	301641	1			T2	99		T3	18		T7	11
valid_sources[0x21]	523714	1			T2	73		T3	14		T7	7
valid_sources[0x22]	347683	1			T2	92		T3	22		T7	7
valid_sources[0x23]	316189	1			T2	94		T3	23		T7	3
valid_sources[0x24]	315760	1			T2	88		T3	22		T7	12
valid_sources[0x25]	321905	1			T2	99		T3	29		T7	5
valid_sources[0x26]	314586	1			T2	90		T3	20		T7	6
valid_sources[0x27]	728073	1			T2	86		T3	21		T7	3
valid_sources[0x28]	774648	1			T2	89		T3	19		T7	4
valid_sources[0x29]	313864	1			T2	86		T3	24		T7	8
valid_sources[0x2a]	320369	1			T2	90		T3	24		T7	7
valid_sources[0x2b]	314814	1			T2	78		T3	18		T7	5
valid_sources[0x2c]	308264	1			T2	86		T3	29		T7	2
valid_sources[0x2d]	324280	1			T2	85		T3	25		T7	6
valid_sources[0x2e]	310763	1			T2	67		T3	24		T7	10
valid_sources[0x2f]	311787	1			T2	89		T3	18		T7	7
valid_sources[0x30]	305928	1			T2	97		T3	16		T7	5
valid_sources[0x31]	305665	1			T2	98		T3	28		T7	7
valid_sources[0x32]	309634	1			T2	78		T3	29		T7	10
valid_sources[0x33]	313318	1			T2	95		T3	23		T7	3
valid_sources[0x34]	314436	1			T2	79		T3	19		T7	7
valid_sources[0x35]	305364	1			T2	85		T3	7		T7	8
valid_sources[0x36]	304025	1			T2	102		T3	20		T7	7
valid_sources[0x37]	308529	1			T2	91		T3	21		T7	6
valid_sources[0x38]	341948	1			T2	80		T3	28		T7	11
valid_sources[0x39]	305021	1			T2	80		T3	16		T7	7
valid_sources[0x3a]	313457	1			T2	88		T3	19		T7	3
valid_sources[0x3b]	307700	1			T2	87		T3	27		T7	8
valid_sources[0x3c]	310302	1			T2	89		T3	16		T7	14
valid_sources[0x3d]	312926	1			T2	88		T3	21		T7	5
valid_sources[0x3e]	321708	1			T2	70		T3	27		T7	8
valid_sources[0x3f]	314408	1			T2	102		T3	15		T7	2
valid_sources[0x40]	309609	1			T2	90		T3	31		T7	1
valid_sources[0x41]	307321	1			T2	82		T3	25		T7	4
valid_sources[0x42]	298048	1			T2	97		T3	18		T7	7
valid_sources[0x43]	307331	1			T2	105		T3	24		T7	5
valid_sources[0x44]	313186	1			T2	84		T3	19		T7	5
valid_sources[0x45]	309649	1			T2	100		T3	22		T7	5
valid_sources[0x46]	321382	1			T2	80		T3	17		T7	8
valid_sources[0x47]	310622	1			T2	89		T3	12		T7	7
valid_sources[0x48]	314636	1			T2	99		T3	20		T7	5
valid_sources[0x49]	565239	1			T2	91		T3	29		T7	4
valid_sources[0x4a]	323088	1			T2	98		T3	22		T7	6
valid_sources[0x4b]	311757	1			T2	99		T3	20		T7	10
valid_sources[0x4c]	314803	1			T2	83		T3	22		T7	5
valid_sources[0x4d]	307265	1			T2	80		T3	27		T7	9
valid_sources[0x4e]	518990	1			T2	98		T3	15		T7	3
valid_sources[0x4f]	315273	1			T2	95		T3	19		T7	4
valid_sources[0x50]	308210	1			T2	78		T3	21		T7	9
valid_sources[0x51]	308475	1			T2	93		T3	23		T7	5
valid_sources[0x52]	339679	1			T2	67		T3	22		T7	7
valid_sources[0x53]	318785	1			T2	84		T3	22		T7	4
valid_sources[0x54]	321272	1			T2	92		T3	22		T7	3
valid_sources[0x55]	1131850	1			T2	84		T3	26		T7	6
valid_sources[0x56]	301700	1			T2	84		T3	19		T7	3
valid_sources[0x57]	309160	1			T2	84		T3	33		T7	10
valid_sources[0x58]	321375	1			T2	78		T3	38		T7	5
valid_sources[0x59]	301344	1			T2	95		T3	22		T7	10
valid_sources[0x5a]	318932	1			T2	95		T3	21		T7	9
valid_sources[0x5b]	317482	1			T2	98		T3	21		T7	5
valid_sources[0x5c]	312216	1			T2	83		T3	42		T7	7
valid_sources[0x5d]	661170	1			T2	67		T3	10		T7	5
valid_sources[0x5e]	303321	1			T2	80		T3	28		T7	3
valid_sources[0x5f]	317294	1			T2	94		T3	24		T7	5
valid_sources[0x60]	315722	1			T2	103		T3	24		T7	11
valid_sources[0x61]	307599	1			T2	87		T3	15		T7	8
valid_sources[0x62]	306306	1			T2	94		T3	44		T7	5
valid_sources[0x63]	631982	1			T2	96		T3	27		T7	6
valid_sources[0x64]	311581	1			T2	85		T3	21		T7	8
valid_sources[0x65]	589882	1			T2	85		T3	20		T7	5
valid_sources[0x66]	309485	1			T2	99		T3	18		T7	6
valid_sources[0x67]	306415	1			T2	95		T3	11		T7	7
valid_sources[0x68]	305389	1			T2	78		T3	15		T7	10
valid_sources[0x69]	626730	1			T2	76		T3	23		T7	18
valid_sources[0x6a]	684806	1			T2	93		T3	18		T7	4
valid_sources[0x6b]	314055	1			T2	95		T3	28		T7	7
valid_sources[0x6c]	578380	1			T2	79		T3	28		T7	9
valid_sources[0x6d]	692148	1			T2	83		T3	26		T7	5
valid_sources[0x6e]	316913	1			T2	89		T3	36		T7	4
valid_sources[0x6f]	306139	1			T2	76		T3	28		T7	8
valid_sources[0x70]	317632	1			T2	84		T3	24		T7	7
valid_sources[0x71]	309668	1			T2	90		T3	19		T7	4
valid_sources[0x72]	306962	1			T2	75		T3	29		T7	5
valid_sources[0x73]	314019	1			T2	93		T3	21		T7	2
valid_sources[0x74]	348799	1			T2	99		T3	25		T7	9
valid_sources[0x75]	316756	1			T2	95		T3	8		T7	7
valid_sources[0x76]	319367	1			T2	67		T3	22		T7	11
valid_sources[0x77]	313644	1			T2	84		T3	27		T7	11
valid_sources[0x78]	327137	1			T2	97		T3	25		T7	2
valid_sources[0x79]	315627	1			T2	84		T3	21		T7	5
valid_sources[0x7a]	304742	1			T2	89		T3	27		T7	5
valid_sources[0x7b]	309326	1			T2	95		T3	21		T7	3
valid_sources[0x7c]	307569	1			T2	79		T3	30		T7	7
valid_sources[0x7d]	300941	1			T2	79		T3	17		T7	6
valid_sources[0x7e]	310760	1			T2	104		T3	15		T7	6
valid_sources[0x7f]	314594	1			T2	100		T3	24		T7	5
valid_sources[0x80]	300773	1			T2	75		T3	31		T7	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6992047

1

T1

552

T2

1295

T3

833

values[0x0]

all_enables

biggest_size

14726175

1

T1

1395

T2

3547

T3

793

values[0x1]

all_enables

biggest_size

8615375

1

T1

857

T2

1918

T3

434