Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T201,T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12477	0	0
DisabledNoTrigBkwd_A	2147483647	801832	0	0
DisabledNoTrigFwd_A	2147483647	1442712734	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12477	0	0
T23	385081	0	0	0
T25	169079	0	0	0
T26	323784	0	0	0
T28	467588	0	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T51	246374	0	0	0
T73	4001	0	0	0
T79	13236	0	0	0
T83	185130	0	0	0
T85	9710	0	0	0
T120	65727	0	0	0
T121	665766	0	0	0
T125	18714	0	0	0
T126	42595	0	0	0
T200	1523	584	0	0
T201	0	859	0	0
T202	3534	639	0	0
T203	0	235	0	0
T204	0	320	0	0
T205	0	272	0	0
T206	2788	539	0	0
T207	0	596	0	0
T208	0	420	0	0
T209	0	322	0	0
T210	0	925	0	0
T211	0	562	0	0
T212	0	1378	0	0
T213	0	432	0	0
T214	0	593	0	0
T215	0	1186	0	0
T216	0	213	0	0
T217	0	207	0	0
T218	0	1039	0	0
T219	0	1156	0	0
T220	93435	0	0	0
T221	429829	0	0	0
T222	117465	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	801832	0	0
T1	293928	136	0	0
T2	880830	0	0	0
T3	178568	377	0	0
T4	532176	20	0	0
T5	1340564	7399	0	0
T6	1590816	430	0	0
T7	52512	1	0	0
T8	609140	2519	0	0
T9	136747	0	0	0
T11	0	15	0	0
T12	0	18	0	0
T17	0	23	0	0
T18	1705976	160	0	0
T19	99836	8	0	0
T20	668086	0	0	0
T23	0	2869	0	0
T26	0	7723	0	0
T28	0	89	0	0
T31	0	50	0	0
T42	0	56	0	0
T43	0	8	0	0
T44	0	2370	0	0
T45	0	19	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1442712734	0	0
T1	391904	112759	0	0
T2	1174440	1142864	0	0
T3	178568	89562	0	0
T4	532176	530055	0	0
T5	1340564	1068439	0	0
T6	1590816	1195919	0	0
T7	52512	37916	0	0
T8	609140	457428	0	0
T18	1705976	874713	0	0
T19	99836	75347	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T204,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	653044715	2201	0	0
DisabledNoTrigBkwd_A	653044715	231560	0	0
DisabledNoTrigFwd_A	653044715	305985341	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	2201	0	0
T23	385081	0	0	0
T26	323784	0	0	0
T28	467588	0	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T73	4001	0	0	0
T79	13236	0	0	0
T83	185130	0	0	0
T120	65727	0	0	0
T200	1523	584	0	0
T204	0	320	0	0
T205	0	272	0	0
T213	0	432	0	0
T214	0	593	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	231560	0	0
T1	97976	27	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	11	0	0
T5	335141	158	0	0
T6	397704	430	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	4	0	0
T18	426494	97	0	0
T19	24959	8	0	0
T31	0	50	0	0
T42	0	56	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	305985341	0	0
T1	97976	3079	0	0
T2	293610	277863	0	0
T3	44642	39560	0	0
T4	133044	132604	0	0
T5	335141	304549	0	0
T6	397704	2834	0	0
T7	13128	5829	0	0
T8	152285	152278	0	0
T18	426494	5581	0	0
T19	24959	623	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T211,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	653044715	2387	0	0
DisabledNoTrigBkwd_A	653044715	166752	0	0
DisabledNoTrigFwd_A	653044715	371902621	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	2387	0	0
T25	169079	0	0	0
T51	246374	0	0	0
T85	9710	0	0	0
T121	665766	0	0	0
T125	18714	0	0	0
T126	42595	0	0	0
T202	3534	639	0	0
T211	0	562	0	0
T215	0	1186	0	0
T220	93435	0	0	0
T221	429829	0	0	0
T222	117465	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	166752	0	0
T1	97976	27	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	8	0	0
T5	335141	1159	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	104	0	0
T28	0	62	0	0
T43	0	4	0	0
T44	0	1104	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	371902621	0	0
T1	97976	3103	0	0
T2	293610	288405	0	0
T3	44642	40861	0	0
T4	133044	132294	0	0
T5	335141	219341	0	0
T6	397704	397695	0	0
T7	13128	13068	0	0
T8	152285	152278	0	0
T18	426494	426409	0	0
T19	24959	24908	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T207,T212
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	653044715	3669	0	0
DisabledNoTrigBkwd_A	653044715	212814	0	0
DisabledNoTrigFwd_A	653044715	375198084	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	3669	0	0
T206	2788	539	0	0
T207	4060	596	0	0
T212	0	1378	0	0
T219	0	1156	0	0
T223	231319	0	0	0
T224	682591	0	0	0
T225	188294	0	0	0
T226	532548	0	0	0
T227	451593	0	0	0
T228	550637	0	0	0
T229	295253	0	0	0
T230	128013	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	212814	0	0
T1	97976	82	0	0
T2	293610	0	0	0
T3	44642	41	0	0
T4	133044	0	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	5	0	0
T17	0	19	0	0
T18	426494	63	0	0
T19	24959	0	0	0
T23	0	947	0	0
T26	0	5393	0	0
T28	0	27	0	0
T43	0	4	0	0
T44	0	698	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	375198084	0	0
T1	97976	8695	0	0
T2	293610	283060	0	0
T3	44642	2050	0	0
T4	133044	132782	0	0
T5	335141	334210	0	0
T6	397704	397695	0	0
T7	13128	9564	0	0
T8	152285	152278	0	0
T18	426494	24664	0	0
T19	24959	24908	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T4
1	0	Covered	T1,T2,T7
1	1	Covered	T3,T7,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T203,T208
1	1	Covered	T3,T7,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	653044715	4220	0	0
DisabledNoTrigBkwd_A	653044715	190706	0	0
DisabledNoTrigFwd_A	653044715	389626688	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	4220	0	0
T50	101773	0	0	0
T81	52811	0	0	0
T82	140011	0	0	0
T84	33037	0	0	0
T96	33257	0	0	0
T116	160144	0	0	0
T201	4225	859	0	0
T203	0	235	0	0
T208	0	420	0	0
T209	0	322	0	0
T210	0	925	0	0
T216	0	213	0	0
T217	0	207	0	0
T218	0	1039	0	0
T231	5419	0	0	0
T232	54573	0	0	0
T233	130343	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	190706	0	0
T3	44642	336	0	0
T4	133044	1	0	0
T5	335141	6082	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	2519	0	0
T9	136747	0	0	0
T11	0	1	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	1818	0	0
T26	0	2330	0	0
T44	0	568	0	0
T45	0	19	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	389626688	0	0
T1	97976	97882	0	0
T2	293610	293536	0	0
T3	44642	7091	0	0
T4	133044	132375	0	0
T5	335141	210339	0	0
T6	397704	397695	0	0
T7	13128	9455	0	0
T8	152285	594	0	0
T18	426494	418059	0	0
T19	24959	24908	0	0