Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T4
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T3,T7,T4
1	1	1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T22
1	0	Covered	T3,T23,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T23,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T25
1	1	Covered	T3,T4,T22

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T4,T5,T6

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T7,T18,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T4,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T3,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T18

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T13,T14,T15
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T7
Phase1St	193	Covered	T1,T3,T7
Phase2St	210	Covered	T1,T3,T7
Phase3St	228	Covered	T1,T3,T7
TerminalSt	244	Covered	T1,T3,T7
TimeoutSt	154	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T13,T14,T15
IdleSt->Phase0St	147	Covered	T1,T3,T7
IdleSt->TimeoutSt	154	Covered	T3,T4,T5
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T5,T26,T27
Phase0St->Phase1St	193	Covered	T1,T3,T7
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T5,T28,T29
Phase1St->Phase2St	210	Covered	T1,T3,T7
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T5,T28,T23
Phase2St->Phase3St	228	Covered	T1,T3,T7
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T5,T28,T30
Phase3St->TerminalSt	244	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T3,T4,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T3,T5,T31
TimeoutSt->Phase0St	167	Covered	T3,T4,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T28,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T28,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	904	0	0
CheckAccumTrig0_A	2147483647	2223	0	0
CheckAccumTrig1_A	2147483647	109	0	0
CheckClr_A	2147483647	987	0	0
CheckEn_A	2147483647	1144258016	0	0
CheckPhase0_A	2147483647	2499	0	0
CheckPhase1_A	2147483647	2457	0	0
CheckPhase2_A	2147483647	2404	0	0
CheckPhase3_A	2147483647	2357	0	0
CheckTimeout0_A	2147483647	3691	0	0
CheckTimeoutSt1_A	2147483647	418389	0	0
CheckTimeoutSt2_A	2147483647	3356	0	0
CheckTimeoutStTrig_A	2147483647	220	0	0
ErrorStAllEscAsserted_A	2147483647	4943	0	0
ErrorStIsTerminal_A	2147483647	4103	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	904	0	0
T13	83416	161	0	0
T14	0	119	0	0
T15	0	260	0	0
T29	1165864	0	0	0
T32	0	250	0	0
T33	0	114	0	0
T34	107908	0	0	0
T35	14880	0	0	0
T36	1238652	0	0	0
T37	2720132	0	0	0
T38	628360	0	0	0
T39	2104380	0	0	0
T40	192588	0	0	0
T41	276788	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2223	0	0
T1	293928	3	0	0
T2	880830	0	0	0
T3	133926	2	0	0
T4	399132	2	0	0
T5	1340564	17	0	0
T6	1590816	1	0	0
T7	39384	1	0	0
T8	609140	1	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	3	0	0
T12	0	2	0	0
T17	0	4	0	0
T18	1279482	2	0	0
T19	74877	1	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	22	0	0
T26	0	6	0	0
T28	0	6	0	0
T31	57461	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	96026	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109	0	0
T3	44642	1	0	0
T4	133044	0	0	0
T7	13128	0	0	0
T18	426494	0	0	0
T23	385081	2	0	0
T24	243762	1	0	0
T27	0	3	0	0
T29	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	0	0	0
T48	206474	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	28877	0	0	0
T63	9960	0	0	0
T64	177082	0	0	0
T65	26024	0	0	0
T66	858414	0	0	0
T67	35397	0	0	0
T68	27197	0	0	0
T69	190880	0	0	0
T70	15125	0	0	0
T71	171690	0	0	0
T72	89668	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	987	0	0
T3	44642	4	0	0
T4	266088	1	0	0
T5	1340564	6	0	0
T6	1590816	0	0	0
T7	13128	0	0	0
T8	609140	0	0	0
T9	546988	0	0	0
T10	312168	0	0	0
T11	1856380	0	0	0
T18	852988	0	0	0
T19	49918	0	0	0
T20	2672344	0	0	0
T21	183909	0	0	0
T23	0	16	0	0
T24	0	1	0	0
T26	0	6	0	0
T28	0	5	0	0
T31	114922	1	0	0
T45	0	1	0	0
T47	192052	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T62	0	1	0	0
T66	0	2	0	0
T67	0	4	0	0
T70	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144258016	0	0
T1	391904	112758	0	0
T2	1174440	1142860	0	0
T3	178568	89560	0	0
T4	532176	151149	0	0
T5	1340564	785254	0	0
T6	1590816	1195919	0	0
T7	52512	37913	0	0
T8	609140	457428	0	0
T18	1705976	874711	0	0
T19	99836	75344	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2499	0	0
T1	293928	3	0	0
T2	880830	0	0	0
T3	178568	6	0	0
T4	532176	4	0	0
T5	1340564	15	0	0
T6	1590816	1	0	0
T7	52512	1	0	0
T8	609140	1	0	0
T9	136747	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T17	0	4	0	0
T18	1705976	2	0	0
T19	99836	1	0	0
T20	668086	0	0	0
T23	0	25	0	0
T26	0	4	0	0
T28	0	6	0	0
T31	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2457	0	0
T1	293928	3	0	0
T2	880830	0	0	0
T3	178568	6	0	0
T4	532176	4	0	0
T5	1340564	14	0	0
T6	1590816	1	0	0
T7	52512	1	0	0
T8	609140	1	0	0
T9	136747	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T17	0	4	0	0
T18	1705976	2	0	0
T19	99836	1	0	0
T20	668086	0	0	0
T23	0	25	0	0
T26	0	4	0	0
T28	0	5	0	0
T31	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T1	293928	3	0	0
T2	880830	0	0	0
T3	178568	6	0	0
T4	532176	4	0	0
T5	1340564	13	0	0
T6	1590816	1	0	0
T7	52512	1	0	0
T8	609140	1	0	0
T9	136747	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T17	0	4	0	0
T18	1705976	2	0	0
T19	99836	1	0	0
T20	668086	0	0	0
T23	0	23	0	0
T26	0	4	0	0
T28	0	5	0	0
T31	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2357	0	0
T1	293928	3	0	0
T2	880830	0	0	0
T3	178568	6	0	0
T4	532176	4	0	0
T5	1340564	11	0	0
T6	1590816	1	0	0
T7	52512	1	0	0
T8	609140	1	0	0
T9	136747	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T17	0	4	0	0
T18	1705976	2	0	0
T19	99836	1	0	0
T20	668086	0	0	0
T23	0	22	0	0
T26	0	4	0	0
T28	0	5	0	0
T31	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3691	0	0
T3	44642	5	0	0
T4	0	1	0	0
T5	670282	2	0	0
T6	795408	0	0	0
T8	304570	0	0	0
T9	273494	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	1336172	0	0	0
T21	61303	0	0	0
T22	0	1	0	0
T23	385081	19	0	0
T24	0	2	0	0
T28	467588	5	0	0
T31	57461	1	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	1	0	0
T47	96026	0	0	0
T48	0	1	0	0
T49	0	25	0	0
T62	28877	0	0	0
T63	9960	1	0	0
T65	0	1	0	0
T68	0	2	0	0
T70	0	1	0	0
T73	4001	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	17	0	0
T83	185130	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	418389	0	0
T3	44642	584	0	0
T4	0	135	0	0
T5	670282	169	0	0
T6	795408	0	0	0
T8	304570	0	0	0
T9	273494	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	1336172	0	0	0
T21	61303	0	0	0
T22	0	278	0	0
T23	385081	3087	0	0
T24	0	48	0	0
T28	467588	676	0	0
T31	57461	111	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	78	0	0
T47	96026	0	0	0
T48	0	1	0	0
T49	0	1566	0	0
T62	28877	0	0	0
T63	9960	131	0	0
T65	0	251	0	0
T68	0	318	0	0
T70	0	12	0	0
T73	4001	0	0	0
T75	0	891	0	0
T77	0	57	0	0
T79	0	150	0	0
T80	0	199	0	0
T81	0	457	0	0
T82	0	4261	0	0
T83	185130	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3356	0	0
T3	44642	2	0	0
T5	670282	2	0	0
T6	795408	0	0	0
T8	304570	0	0	0
T9	273494	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	1336172	0	0	0
T21	61303	0	0	0
T23	385081	30	0	0
T24	0	2	0	0
T27	0	336	0	0
T28	467588	7	0	0
T31	57461	1	0	0
T37	0	4	0	0
T39	0	2	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	1	0	0
T47	96026	0	0	0
T49	0	29	0	0
T62	28877	0	0	0
T63	9960	2	0	0
T65	0	1	0	0
T68	0	6	0	0
T70	0	1	0	0
T73	4001	0	0	0
T75	0	1	0	0
T79	0	6	0	0
T80	0	2	0	0
T81	0	5	0	0
T82	0	36	0	0
T83	185130	0	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	220	0	0
T3	44642	2	0	0
T4	0	1	0	0
T13	20854	0	0	0
T22	0	1	0	0
T25	0	2	0	0
T27	705533	4	0	0
T29	0	3	0	0
T36	0	1	0	0
T37	0	4	0	0
T49	122408	1	0	0
T50	101773	0	0	0
T51	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T75	87434	1	0	0
T76	807495	0	0	0
T77	179908	1	0	0
T78	712886	0	0	0
T82	140011	2	0	0
T85	0	1	0	0
T86	0	3	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	11054	0	0	0
T92	69624	0	0	0
T93	984770	0	0	0
T94	763627	0	0	0
T95	165801	0	0	0
T96	33257	0	0	0
T97	3884	0	0	0
T98	62268	0	0	0
T99	81323	0	0	0
T100	438845	0	0	0
T101	19472	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4943	0	0
T13	83416	713	0	0
T14	0	684	0	0
T15	0	1447	0	0
T29	1165864	0	0	0
T32	0	1411	0	0
T33	0	688	0	0
T34	107908	0	0	0
T35	14880	0	0	0
T36	1238652	0	0	0
T37	2720132	0	0	0
T38	628360	0	0	0
T39	2104380	0	0	0
T40	192588	0	0	0
T41	276788	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4103	0	0
T13	83416	593	0	0
T14	0	564	0	0
T15	0	1207	0	0
T29	1165864	0	0	0
T32	0	1171	0	0
T33	0	568	0	0
T34	107908	0	0	0
T35	14880	0	0	0
T36	1238652	0	0	0
T37	2720132	0	0	0
T38	628360	0	0	0
T39	2104380	0	0	0
T40	192588	0	0	0
T41	276788	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	391904	391528	0	0
T2	1174440	1174144	0	0
T3	178568	178356	0	0
T4	532176	532136	0	0
T5	1340564	1340400	0	0
T6	1590816	1590780	0	0
T7	52512	52272	0	0
T8	609140	609112	0	0
T18	1705976	1705636	0	0
T19	99836	99632	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T10,T12
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T28,T23,T46

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T28,T23,T46
0	1	Covered	T75,T77,T49
1	0	Covered	T23,T49,T27

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T28,T23,T46
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T49,T27

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T23,T46
1	0	Not Covered
1	1	Covered	T75,T77,T49

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T28,T23

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T17,T28

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T11
1	Covered	T4,T12,T43

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T11
1	Covered	T1,T5,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T5,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T5,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T13,T14,T15
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T4,T5
Phase1St	193	Covered	T1,T4,T5
Phase2St	210	Covered	T1,T4,T5
Phase3St	228	Covered	T1,T4,T5
TerminalSt	244	Covered	T1,T4,T5
TimeoutSt	154	Covered	T28,T23,T46

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T13,T14,T15
IdleSt->Phase0St	147	Covered	T1,T4,T5
IdleSt->TimeoutSt	154	Covered	T28,T23,T46
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T27,T52,T102
Phase0St->Phase1St	193	Covered	T1,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T28,T29,T55
Phase1St->Phase2St	210	Covered	T1,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T5,T76,T27
Phase2St->Phase3St	228	Covered	T1,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T58,T103,T104
Phase3St->TerminalSt	244	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T5,T28,T23
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T28,T23,T46
TimeoutSt->Phase0St	167	Covered	T23,T75,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T23,T46
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T75,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T28,T23,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T28,T23,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T52,T58
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T76,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T58,T103,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T23,T67,T70
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653044715	236	0	0
CheckAccumTrig0_A	653044715	497	0	0
CheckAccumTrig1_A	653044715	24	0	0
CheckClr_A	653044715	232	0	0
CheckEn_A	652870182	288998255	0	0
CheckPhase0_A	653044715	568	0	0
CheckPhase1_A	653044715	559	0	0
CheckPhase2_A	653044715	548	0	0
CheckPhase3_A	653044715	536	0	0
CheckTimeout0_A	653044715	814	0	0
CheckTimeoutSt1_A	653044715	102794	0	0
CheckTimeoutSt2_A	653044715	726	0	0
CheckTimeoutStTrig_A	653044715	63	0	0
ErrorStAllEscAsserted_A	653044715	1267	0	0
ErrorStIsTerminal_A	653044715	1057	0	0
u_state_regs_A	653044715	652885229	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	236	0	0
T13	20854	41	0	0
T14	0	37	0	0
T15	0	63	0	0
T29	291466	0	0	0
T32	0	62	0	0
T33	0	33	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	497	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	0	1	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	4	0	0
T28	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	24	0	0
T23	385081	1	0	0
T24	121881	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T37	0	2	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T58	0	2	0	0
T61	0	1	0	0
T62	28877	0	0	0
T63	9960	0	0	0
T64	177082	0	0	0
T65	13012	0	0	0
T66	429207	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	232	0	0
T5	335141	1	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	2	0	0
T28	0	1	0	0
T31	57461	0	0	0
T47	96026	0	0	0
T49	0	1	0	0
T67	0	2	0	0
T70	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652870182	288998255	0	0
T1	97976	3103	0	0
T2	293610	288404	0	0
T3	44642	40860	0	0
T4	133044	2925	0	0
T5	335141	219338	0	0
T6	397704	397695	0	0
T7	13128	13067	0	0
T8	152285	152278	0	0
T18	426494	426408	0	0
T19	24959	24907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	568	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	0	1	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	5	0	0
T28	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	559	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	0	1	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	5	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	548	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	2	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	0	1	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	5	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	536	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	2	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T17	0	1	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T23	0	5	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	814	0	0
T23	385081	9	0	0
T24	0	1	0	0
T28	467588	2	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	1	0	0
T49	0	2	0	0
T62	28877	0	0	0
T63	9960	0	0	0
T70	0	1	0	0
T73	4001	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T81	0	1	0	0
T82	0	17	0	0
T83	185130	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	102794	0	0
T23	385081	1908	0	0
T24	0	45	0	0
T28	467588	243	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	78	0	0
T49	0	26	0	0
T62	28877	0	0	0
T63	9960	0	0	0
T70	0	12	0	0
T73	4001	0	0	0
T75	0	891	0	0
T77	0	57	0	0
T81	0	246	0	0
T82	0	4261	0	0
T83	185130	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	726	0	0
T23	385081	8	0	0
T24	0	1	0	0
T27	0	2	0	0
T28	467588	2	0	0
T37	0	4	0	0
T39	0	2	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T45	20160	0	0	0
T46	484769	1	0	0
T62	28877	0	0	0
T63	9960	0	0	0
T70	0	1	0	0
T73	4001	0	0	0
T81	0	1	0	0
T82	0	16	0	0
T83	185130	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	63	0	0
T27	0	2	0	0
T29	0	1	0	0
T37	0	1	0	0
T49	122408	1	0	0
T51	0	1	0	0
T75	87434	1	0	0
T76	807495	0	0	0
T77	179908	1	0	0
T78	712886	0	0	0
T82	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0
T91	11054	0	0	0
T92	69624	0	0	0
T93	984770	0	0	0
T94	763627	0	0	0
T95	165801	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1267	0	0
T13	20854	182	0	0
T14	0	164	0	0
T15	0	345	0	0
T29	291466	0	0	0
T32	0	386	0	0
T33	0	190	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1057	0	0
T13	20854	152	0	0
T14	0	134	0	0
T15	0	285	0	0
T29	291466	0	0	0
T32	0	326	0	0
T33	0	160	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	652885229	0	0
T1	97976	97882	0	0
T2	293610	293536	0	0
T3	44642	44589	0	0
T4	133044	133034	0	0
T5	335141	335100	0	0
T6	397704	397695	0	0
T7	13128	13068	0	0
T8	152285	152278	0	0
T18	426494	426409	0	0
T19	24959	24908	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T18

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T2,T7,T18
1	1	0	Covered	T4,T5,T79
1	1	1	Covered	T3,T4,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T22
1	0	Covered	T3,T23,T48

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T23,T48

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T3,T4,T22

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T18
1	Covered	T4,T28,T43

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T28,T23,T24

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T18
1	Covered	T1,T17,T26

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T3,T18,T11

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T26

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T18,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T18,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T13,T14,T15
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T13,T14,T15
IdleSt->Phase0St	147	Covered	T1,T3,T18
IdleSt->TimeoutSt	154	Covered	T3,T4,T5
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T27,T51
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T106,T107,T108
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T23,T105,T109
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T58,T110,T111
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T26,T28
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T5,T23
TimeoutSt->Phase0St	167	Covered	T3,T4,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T27,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T106,T107,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T105,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T58,T110,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T26,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653044715	198	0	0
CheckAccumTrig0_A	653044715	448	0	0
CheckAccumTrig1_A	653044715	22	0	0
CheckClr_A	653044715	181	0	0
CheckEn_A	652870182	315058946	0	0
CheckPhase0_A	653044715	517	0	0
CheckPhase1_A	653044715	509	0	0
CheckPhase2_A	653044715	496	0	0
CheckPhase3_A	653044715	485	0	0
CheckTimeout0_A	653044715	793	0	0
CheckTimeoutSt1_A	653044715	91857	0	0
CheckTimeoutSt2_A	653044715	717	0	0
CheckTimeoutStTrig_A	653044715	52	0	0
ErrorStAllEscAsserted_A	653044715	1190	0	0
ErrorStIsTerminal_A	653044715	980	0	0
u_state_regs_A	653044715	652885229	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	198	0	0
T13	20854	33	0	0
T14	0	32	0	0
T15	0	51	0	0
T29	291466	0	0	0
T32	0	62	0	0
T33	0	20	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	448	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	2	0	0
T4	133044	0	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T17	0	1	0	0
T18	426494	1	0	0
T19	24959	0	0	0
T23	0	9	0	0
T26	0	4	0	0
T28	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	22	0	0
T3	44642	1	0	0
T4	133044	0	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T104	0	1	0	0
T109	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	181	0	0
T3	44642	4	0	0
T4	133044	0	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	6	0	0
T26	0	3	0	0
T45	0	1	0	0
T49	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T78	0	1	0	0
T84	0	4	0	0
T94	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652870182	315058946	0	0
T1	97976	8695	0	0
T2	293610	283059	0	0
T3	44642	2050	0	0
T4	133044	7808	0	0
T5	335141	334210	0	0
T6	397704	397695	0	0
T7	13128	9563	0	0
T8	152285	152278	0	0
T18	426494	24664	0	0
T19	24959	24907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	517	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	5	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T17	0	1	0	0
T18	426494	1	0	0
T19	24959	0	0	0
T23	0	10	0	0
T26	0	3	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	509	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	5	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T17	0	1	0	0
T18	426494	1	0	0
T19	24959	0	0	0
T23	0	10	0	0
T26	0	3	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	496	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	5	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T17	0	1	0	0
T18	426494	1	0	0
T19	24959	0	0	0
T23	0	9	0	0
T26	0	3	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	485	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	5	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T11	0	1	0	0
T17	0	1	0	0
T18	426494	1	0	0
T19	24959	0	0	0
T23	0	9	0	0
T26	0	3	0	0
T28	0	2	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	793	0	0
T3	44642	5	0	0
T4	133044	1	0	0
T5	335141	1	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T48	0	1	0	0
T49	0	13	0	0
T63	0	1	0	0
T68	0	1	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	91857	0	0
T3	44642	584	0	0
T4	133044	135	0	0
T5	335141	137	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T22	0	278	0	0
T23	0	126	0	0
T48	0	1	0	0
T49	0	919	0	0
T63	0	131	0	0
T68	0	165	0	0
T80	0	199	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	717	0	0
T3	44642	2	0	0
T4	133044	0	0	0
T5	335141	1	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	2	0	0
T49	0	13	0	0
T63	0	1	0	0
T68	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	20	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	52	0	0
T3	44642	2	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T29	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T114	0	1	0	0
T115	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1190	0	0
T13	20854	181	0	0
T14	0	167	0	0
T15	0	364	0	0
T29	291466	0	0	0
T32	0	330	0	0
T33	0	148	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	980	0	0
T13	20854	151	0	0
T14	0	137	0	0
T15	0	304	0	0
T29	291466	0	0	0
T32	0	270	0	0
T33	0	118	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	652885229	0	0
T1	97976	97882	0	0
T2	293610	293536	0	0
T3	44642	44589	0	0
T4	133044	133034	0	0
T5	335141	335100	0	0
T6	397704	397695	0	0
T7	13128	13068	0	0
T8	152285	152278	0	0
T18	426494	426409	0	0
T19	24959	24908	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T11

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T18,T10,T11
1	1	0	Covered	T7,T28,T43
1	1	1	Covered	T3,T4,T79

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T79,T28,T23
0	1	Covered	T75,T82,T40
1	0	Covered	T3,T4,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T79,T28,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T79
1	0	Not Covered
1	1	Covered	T75,T82,T40

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T8
1	Covered	T5,T11,T26

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T8
1	Covered	T4,T17,T23

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T3,T17,T23

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T8,T66,T48

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T8,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T13,T14,T15
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T5
Phase1St	193	Covered	T3,T4,T5
Phase2St	210	Covered	T3,T4,T5
Phase3St	228	Covered	T3,T4,T5
TerminalSt	244	Covered	T3,T4,T5
TimeoutSt	154	Covered	T3,T4,T79

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T13,T14,T15
IdleSt->Phase0St	147	Covered	T5,T8,T11
IdleSt->TimeoutSt	154	Covered	T3,T4,T79
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T26,T106
Phase0St->Phase1St	193	Covered	T3,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T49,T51,T106
Phase1St->Phase2St	210	Covered	T3,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T23,T49,T58
Phase2St->Phase3St	228	Covered	T3,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T5,T23,T116
Phase3St->TerminalSt	244	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T5,T11,T17
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T79,T28,T23
TimeoutSt->Phase0St	167	Covered	T3,T4,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T79
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T79,T28,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T79,T28,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T26,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T49,T106,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T49,T58
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T23,T116
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T17,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653044715	237	0	0
CheckAccumTrig0_A	653044715	490	0	0
CheckAccumTrig1_A	653044715	21	0	0
CheckClr_A	653044715	211	0	0
CheckEn_A	652870182	301564795	0	0
CheckPhase0_A	653044715	548	0	0
CheckPhase1_A	653044715	535	0	0
CheckPhase2_A	653044715	524	0	0
CheckPhase3_A	653044715	512	0	0
CheckTimeout0_A	653044715	601	0	0
CheckTimeoutSt1_A	653044715	73965	0	0
CheckTimeoutSt2_A	653044715	530	0	0
CheckTimeoutStTrig_A	653044715	47	0	0
ErrorStAllEscAsserted_A	653044715	1243	0	0
ErrorStIsTerminal_A	653044715	1033	0	0
u_state_regs_A	653044715	652885229	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	237	0	0
T13	20854	37	0	0
T14	0	23	0	0
T15	0	63	0	0
T29	291466	0	0	0
T32	0	85	0	0
T33	0	29	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	490	0	0
T5	335141	4	0	0
T6	397704	0	0	0
T8	152285	1	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	1	0	0
T17	0	2	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	9	0	0
T24	0	2	0	0
T26	0	2	0	0
T31	57461	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	96026	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	21	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	1	0	0
T49	0	3	0	0
T55	0	1	0	0
T69	0	1	0	0
T109	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	211	0	0
T5	335141	2	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	1	0	0
T17	0	1	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T26	0	1	0	0
T31	57461	0	0	0
T46	0	1	0	0
T47	96026	0	0	0
T66	0	1	0	0
T69	0	1	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652870182	301564795	0	0
T1	97976	97881	0	0
T2	293610	293535	0	0
T3	44642	7091	0	0
T4	133044	7812	0	0
T5	335141	210336	0	0
T6	397704	397695	0	0
T7	13128	9454	0	0
T8	152285	594	0	0
T18	426494	418058	0	0
T19	24959	24907	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	548	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	1	0	0
T9	136747	0	0	0
T11	0	1	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	10	0	0
T26	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	535	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	1	0	0
T9	136747	0	0	0
T11	0	1	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	10	0	0
T26	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	524	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	3	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	1	0	0
T9	136747	0	0	0
T11	0	1	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	9	0	0
T26	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	512	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	2	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	1	0	0
T9	136747	0	0	0
T11	0	1	0	0
T17	0	2	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	8	0	0
T26	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	601	0	0
T3	44642	1	0	0
T4	133044	1	0	0
T5	335141	0	0	0
T6	397704	0	0	0
T7	13128	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T23	0	14	0	0
T24	0	1	0	0
T28	0	2	0	0
T63	0	1	0	0
T68	0	4	0	0
T69	0	1	0	0
T75	0	2	0	0
T79	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	73965	0	0
T23	385081	2249	0	0
T24	0	45	0	0
T26	323784	0	0	0
T28	467588	183	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T49	0	361	0	0
T62	28877	0	0	0
T63	0	131	0	0
T68	0	635	0	0
T69	0	2	0	0
T73	4001	0	0	0
T75	0	391	0	0
T79	13236	528	0	0
T80	0	62	0	0
T83	185130	0	0	0
T120	65727	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	530	0	0
T23	385081	13	0	0
T24	0	1	0	0
T26	323784	0	0	0
T28	467588	2	0	0
T43	13438	0	0	0
T44	378534	0	0	0
T49	0	6	0	0
T62	28877	0	0	0
T63	0	1	0	0
T68	0	4	0	0
T73	4001	0	0	0
T75	0	1	0	0
T79	13236	5	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	185130	0	0	0
T120	65727	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	47	0	0
T25	0	2	0	0
T29	0	1	0	0
T40	0	1	0	0
T49	122408	0	0	0
T55	0	1	0	0
T75	87434	1	0	0
T76	807495	0	0	0
T77	179908	0	0	0
T78	712886	0	0	0
T82	0	1	0	0
T91	11054	0	0	0
T92	69624	0	0	0
T93	984770	0	0	0
T94	763627	0	0	0
T95	165801	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1243	0	0
T13	20854	156	0	0
T14	0	169	0	0
T15	0	371	0	0
T29	291466	0	0	0
T32	0	373	0	0
T33	0	174	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1033	0	0
T13	20854	126	0	0
T14	0	139	0	0
T15	0	311	0	0
T29	291466	0	0	0
T32	0	313	0	0
T33	0	144	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	652885229	0	0
T1	97976	97882	0	0
T2	293610	293536	0	0
T3	44642	44589	0	0
T4	133044	133034	0	0
T5	335141	335100	0	0
T6	397704	397695	0	0
T7	13128	13068	0	0
T8	152285	152278	0	0
T18	426494	426409	0	0
T19	24959	24908	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T4
1	0	1	Covered	T2,T18,T5
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T5,T31,T79

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T31,T79
0	1	Covered	T82,T37,T29
1	0	Covered	T24,T50,T39

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T31,T79
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T50,T39

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T31,T79
1	0	Covered	T25
1	1	Covered	T82,T37,T29

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T18
1	Covered	T4,T5,T6

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T7,T18,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T4
1	Covered	T19,T5,T26

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T4,T18
1	Covered	T1,T5,T31

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T7,T4,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T4,T18,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T19,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T13,T14,T15
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T7,T4
Phase1St	193	Covered	T1,T7,T4
Phase2St	210	Covered	T1,T7,T4
Phase3St	228	Covered	T1,T7,T4
TerminalSt	244	Covered	T1,T7,T4
TimeoutSt	154	Covered	T5,T31,T79

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T13,T14,T15
IdleSt->Phase0St	147	Covered	T1,T7,T4
IdleSt->TimeoutSt	154	Covered	T5,T31,T79
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T26,T41
Phase0St->Phase1St	193	Covered	T1,T7,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T5,T29,T125
Phase1St->Phase2St	210	Covered	T1,T7,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T82,T126
Phase2St->Phase3St	228	Covered	T1,T7,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T5,T28,T30
Phase3St->TerminalSt	244	Covered	T1,T7,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T5,T31
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T5,T31,T79
TimeoutSt->Phase0St	167	Covered	T24,T82,T50

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T31,T79
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T82,T50
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T31,T79
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T31,T79
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T26,T41
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T7,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T7,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T29,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T7,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T7,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T82,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T7,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T28,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T7,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T7,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653044715	233	0	0
CheckAccumTrig0_A	653044715	788	0	0
CheckAccumTrig1_A	653044715	42	0	0
CheckClr_A	653044715	363	0	0
CheckEn_A	652870182	238636020	0	0
CheckPhase0_A	653044715	866	0	0
CheckPhase1_A	653044715	854	0	0
CheckPhase2_A	653044715	836	0	0
CheckPhase3_A	653044715	824	0	0
CheckTimeout0_A	653044715	1483	0	0
CheckTimeoutSt1_A	653044715	149773	0	0
CheckTimeoutSt2_A	653044715	1383	0	0
CheckTimeoutStTrig_A	653044715	58	0	0
ErrorStAllEscAsserted_A	653044715	1243	0	0
ErrorStIsTerminal_A	653044715	1033	0	0
u_state_regs_A	653044715	652885229	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	233	0	0
T13	20854	50	0	0
T14	0	27	0	0
T15	0	83	0	0
T29	291466	0	0	0
T32	0	41	0	0
T33	0	32	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	788	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	10	0	0
T6	397704	1	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	1	0	0
T18	426494	1	0	0
T19	24959	1	0	0
T31	0	2	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	42	0	0
T24	121881	1	0	0
T39	0	1	0	0
T48	206474	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T65	13012	0	0	0
T66	429207	0	0	0
T67	35397	0	0	0
T68	27197	0	0	0
T69	190880	0	0	0
T70	15125	0	0	0
T71	171690	0	0	0
T72	89668	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	363	0	0
T4	133044	1	0	0
T5	335141	5	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T18	426494	0	0	0
T19	24959	0	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	8	0	0
T24	0	1	0	0
T26	0	3	0	0
T28	0	4	0	0
T31	0	1	0	0
T48	0	1	0	0
T62	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652870182	238636020	0	0
T1	97976	3079	0	0
T2	293610	277862	0	0
T3	44642	39559	0	0
T4	133044	132604	0	0
T5	335141	21370	0	0
T6	397704	2834	0	0
T7	13128	5829	0	0
T8	152285	152278	0	0
T18	426494	5581	0	0
T19	24959	623	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	866	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	9	0	0
T6	397704	1	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	1	0	0
T18	426494	1	0	0
T19	24959	1	0	0
T31	0	2	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	854	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	8	0	0
T6	397704	1	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	1	0	0
T18	426494	1	0	0
T19	24959	1	0	0
T31	0	2	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	836	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	8	0	0
T6	397704	1	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	1	0	0
T18	426494	1	0	0
T19	24959	1	0	0
T31	0	2	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	824	0	0
T1	97976	1	0	0
T2	293610	0	0	0
T3	44642	0	0	0
T4	133044	1	0	0
T5	335141	7	0	0
T6	397704	1	0	0
T7	13128	1	0	0
T8	152285	0	0	0
T12	0	1	0	0
T18	426494	1	0	0
T19	24959	1	0	0
T31	0	2	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1483	0	0
T5	335141	1	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	7	0	0
T24	0	1	0	0
T28	0	3	0	0
T31	57461	1	0	0
T47	96026	0	0	0
T49	0	10	0	0
T65	0	1	0	0
T68	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	149773	0	0
T5	335141	32	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	1053	0	0
T24	0	3	0	0
T28	0	433	0	0
T31	57461	111	0	0
T47	96026	0	0	0
T49	0	621	0	0
T65	0	251	0	0
T68	0	153	0	0
T79	0	150	0	0
T81	0	211	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1383	0	0
T5	335141	1	0	0
T6	397704	0	0	0
T8	152285	0	0	0
T9	136747	0	0	0
T10	104056	0	0	0
T11	928190	0	0	0
T20	668086	0	0	0
T21	61303	0	0	0
T23	0	7	0	0
T27	0	334	0	0
T28	0	3	0	0
T31	57461	1	0	0
T47	96026	0	0	0
T49	0	10	0	0
T65	0	1	0	0
T68	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	58	0	0
T13	20854	0	0	0
T25	0	1	0	0
T27	705533	0	0	0
T29	0	1	0	0
T37	0	1	0	0
T50	101773	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T82	140011	1	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T96	33257	0	0	0
T97	3884	0	0	0
T98	62268	0	0	0
T99	81323	0	0	0
T100	438845	0	0	0
T101	19472	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1243	0	0
T13	20854	194	0	0
T14	0	184	0	0
T15	0	367	0	0
T29	291466	0	0	0
T32	0	322	0	0
T33	0	176	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	1033	0	0
T13	20854	164	0	0
T14	0	154	0	0
T15	0	307	0	0
T29	291466	0	0	0
T32	0	262	0	0
T33	0	146	0	0
T34	26977	0	0	0
T35	3720	0	0	0
T36	309663	0	0	0
T37	680033	0	0	0
T38	157090	0	0	0
T39	526095	0	0	0
T40	48147	0	0	0
T41	69197	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653044715	652885229	0	0
T1	97976	97882	0	0
T2	293610	293536	0	0
T3	44642	44589	0	0
T4	133044	133034	0	0
T5	335141	335100	0	0
T6	397704	397695	0	0
T7	13128	13068	0	0
T8	152285	152278	0	0
T18	426494	426409	0	0
T19	24959	24908	0	0