Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.86	100.00	88.89	91.89			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	91.89			91.89

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T203,T38
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13529	0	0
DisabledNoTrigBkwd_A	2147483647	851725	0	0
DisabledNoTrigFwd_A	2147483647	1393853832	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13529	0	0
T1	4238	654	0	0
T2	127501	0	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T27	857523	0	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T32	101239	0	0	0
T33	485803	0	0	0
T38	0	293	0	0
T44	0	776	0	0
T69	0	334	0	0
T71	38900	0	0	0
T106	134470	0	0	0
T117	162652	0	0	0
T200	199627	0	0	0
T201	12191	0	0	0
T202	18359	0	0	0
T203	3806	691	0	0
T204	2922	754	0	0
T205	0	995	0	0
T206	0	950	0	0
T207	0	435	0	0
T208	0	387	0	0
T209	0	284	0	0
T210	0	625	0	0
T211	0	425	0	0
T212	0	653	0	0
T213	0	357	0	0
T214	0	778	0	0
T215	0	709	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	851725	0	0
T1	4238	9	0	0
T2	510004	5455	0	0
T3	121712	0	0	0
T4	3446708	342	0	0
T5	0	2417	0	0
T6	0	1782	0	0
T7	198448	17	0	0
T8	36720	2	0	0
T12	1063784	1201	0	0
T18	64580	0	0	0
T20	0	1088	0	0
T21	0	22	0	0
T24	0	2058	0	0
T25	0	4198	0	0
T28	164504	0	0	0
T29	30684	5	0	0
T30	46257	26	0	0
T31	0	2263	0	0
T46	0	15	0	0
T47	0	118	0	0
T48	0	88	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393853832	0	0
T1	16952	12781	0	0
T2	510004	135854	0	0
T3	121712	71160	0	0
T4	3446708	2564526	0	0
T7	198448	103283	0	0
T8	36720	27888	0	0
T12	1063784	602752	0	0
T18	64580	50389	0	0
T28	164504	120515	0	0
T29	30684	21990	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T2,T3,T18
1	1	Covered	T2,T18,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T18,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674113279	0	0	0
DisabledNoTrigBkwd_A	674113279	212580	0	0
DisabledNoTrigFwd_A	674113279	349160198	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	212580	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	75	0	0
T6	0	8	0	0
T7	49612	13	0	0
T8	9180	0	0	0
T12	265946	622	0	0
T18	16145	0	0	0
T20	0	353	0	0
T21	0	2	0	0
T24	0	823	0	0
T25	0	1315	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	166	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	349160198	0	0
T1	4238	3222	0	0
T2	127501	127286	0	0
T3	30428	30372	0	0
T4	861677	792563	0	0
T7	49612	2092	0	0
T8	9180	9102	0	0
T12	265946	36404	0	0
T18	16145	14411	0	0
T28	41126	38899	0	0
T29	7671	7601	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T18,T7
1	1	Covered	T2,T4,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T211
1	1	Covered	T2,T4,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674113279	1116	0	0
DisabledNoTrigBkwd_A	674113279	208221	0	0
DisabledNoTrigFwd_A	674113279	326853482	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1116	0	0
T27	857523	0	0	0
T32	101239	0	0	0
T33	485803	0	0	0
T71	38900	0	0	0
T106	134470	0	0	0
T117	162652	0	0	0
T200	199627	0	0	0
T201	12191	0	0	0
T202	18359	0	0	0
T203	3806	691	0	0
T211	0	425	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	208221	0	0
T2	127501	1889	0	0
T3	30428	0	0	0
T4	861677	337	0	0
T5	0	2259	0	0
T6	0	103	0	0
T7	49612	0	0	0
T8	9180	2	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	361	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	26	0	0
T31	0	664	0	0
T46	0	15	0	0
T47	0	118	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	326853482	0	0
T1	4238	3168	0	0
T2	127501	2852	0	0
T3	30428	30372	0	0
T4	861677	212063	0	0
T7	49612	49559	0	0
T8	9180	582	0	0
T12	265946	265551	0	0
T18	16145	16056	0	0
T28	41126	41051	0	0
T29	7671	7601	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T38,T44
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674113279	9112	0	0
DisabledNoTrigBkwd_A	674113279	247316	0	0
DisabledNoTrigFwd_A	674113279	366124249	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	9112	0	0
T1	4238	654	0	0
T2	127501	0	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T38	0	293	0	0
T44	0	776	0	0
T69	0	334	0	0
T205	0	995	0	0
T206	0	950	0	0
T208	0	387	0	0
T209	0	284	0	0
T212	0	653	0	0
T213	0	357	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	247316	0	0
T1	4238	9	0	0
T2	127501	1643	0	0
T3	30428	0	0	0
T4	861677	5	0	0
T5	0	5	0	0
T6	0	5	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	578	0	0
T18	16145	0	0	0
T24	0	1235	0	0
T25	0	1325	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	276	0	0
T48	0	88	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	366124249	0	0
T1	4238	3182	0	0
T2	127501	2856	0	0
T3	30428	6407	0	0
T4	861677	782147	0	0
T7	49612	49559	0	0
T8	9180	9102	0	0
T12	265946	35746	0	0
T18	16145	6475	0	0
T28	41126	586	0	0
T29	7671	3651	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T18
1	1	Covered	T2,T3,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T207,T210
1	1	Covered	T2,T3,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674113279	3301	0	0
DisabledNoTrigBkwd_A	674113279	183608	0	0
DisabledNoTrigFwd_A	674113279	351715903	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	3301	0	0
T62	58242	0	0	0
T63	370809	0	0	0
T204	2922	754	0	0
T207	0	435	0	0
T210	0	625	0	0
T214	0	778	0	0
T215	0	709	0	0
T216	12591	0	0	0
T217	169744	0	0	0
T218	2455	0	0	0
T219	262417	0	0	0
T220	175569	0	0	0
T221	1715	0	0	0
T222	19885	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	183608	0	0
T2	127501	1922	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	78	0	0
T6	0	1666	0	0
T7	49612	4	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	374	0	0
T21	0	20	0	0
T25	0	1558	0	0
T28	41126	0	0	0
T29	7671	5	0	0
T30	15419	0	0	0
T31	0	1157	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	351715903	0	0
T1	4238	3209	0	0
T2	127501	2860	0	0
T3	30428	4009	0	0
T4	861677	777753	0	0
T7	49612	2073	0	0
T8	9180	9102	0	0
T12	265946	265051	0	0
T18	16145	13447	0	0
T28	41126	39979	0	0
T29	7671	3137	0	0