Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T1,T7,T4
1	1	0	Covered	T2,T3,T18
1	1	1	Covered	T2,T3,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T18
0	1	Covered	T3,T18,T5
1	0	Covered	T4,T6,T32

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T32

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Not Covered
1	1	Covered	T3,T18,T5

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T1,T2,T30

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T6

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T2,T3,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T7
IdleSt->TimeoutSt	154	Covered	T2,T3,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T4,T5,T32
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T5,T6,T33
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T5,T33,T34
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T4,T35,T34
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T4,T12,T29
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T2,T3,T28
TimeoutSt->Phase0St	167	Covered	T3,T18,T4

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T6,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T33,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T35,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T12,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1167	0	0
CheckAccumTrig0_A	2147483647	2240	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1007	0	0
CheckEn_A	2147483647	1063276785	0	0
CheckPhase0_A	2147483647	2541	0	0
CheckPhase1_A	2147483647	2498	0	0
CheckPhase2_A	2147483647	2451	0	0
CheckPhase3_A	2147483647	2402	0	0
CheckTimeout0_A	2147483647	4976	0	0
CheckTimeoutSt1_A	2147483647	404105	0	0
CheckTimeoutSt2_A	2147483647	4626	0	0
CheckTimeoutStTrig_A	2147483647	229	0	0
ErrorStAllEscAsserted_A	2147483647	5886	0	0
ErrorStIsTerminal_A	2147483647	4926	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1167	0	0
T9	69948	126	0	0
T10	0	298	0	0
T11	0	323	0	0
T23	486940	0	0	0
T36	0	301	0	0
T37	0	119	0	0
T38	14768	0	0	0
T39	35032	0	0	0
T40	887740	0	0	0
T41	549012	0	0	0
T42	115240	0	0	0
T43	786484	0	0	0
T44	6416	0	0	0
T45	41872	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2240	0	0
T1	4238	1	0	0
T2	510004	4	0	0
T3	121712	0	0	0
T4	3446708	15	0	0
T5	0	19	0	0
T6	0	10	0	0
T7	198448	2	0	0
T8	36720	1	0	0
T12	1063784	5	0	0
T18	64580	0	0	0
T20	0	6	0	0
T21	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T26	0	1	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	46257	1	0	0
T31	0	16	0	0
T33	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T4	1723354	2	0	0
T5	961756	0	0	0
T6	267152	1	0	0
T8	18360	0	0	0
T12	531892	0	0	0
T15	0	2	0	0
T19	0	4	0	0
T20	922784	0	0	0
T21	279120	0	0	0
T27	857523	0	0	0
T28	82252	0	0	0
T29	15342	0	0	0
T30	30838	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T49	992631	1	0	0
T50	31140	1	0	0
T51	8804	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	67313	0	0	0
T65	798343	0	0	0
T66	304996	0	0	0
T67	42748	0	0	0
T68	124147	0	0	0
T69	2657	0	0	0
T70	9545	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1007	0	0
T4	861677	14	0	0
T5	1923512	17	0	0
T6	534304	6	0	0
T8	9180	0	0	0
T12	1063784	3	0	0
T20	1845568	3	0	0
T21	558240	1	0	0
T24	877704	0	0	0
T25	2763027	3	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	61676	0	0	0
T31	0	2	0	0
T32	0	6	0	0
T33	0	21	0	0
T34	0	2	0	0
T35	0	5	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1063276785	0	0
T1	16952	12781	0	0
T2	510004	9375	0	0
T3	121712	67123	0	0
T4	3446708	2549522	0	0
T7	198448	103281	0	0
T8	36720	27885	0	0
T12	1063784	602752	0	0
T18	64580	44497	0	0
T28	164504	120512	0	0
T29	30684	21987	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T1	4238	1	0	0
T2	510004	4	0	0
T3	121712	1	0	0
T4	3446708	16	0	0
T5	0	23	0	0
T6	0	12	0	0
T7	198448	2	0	0
T8	36720	1	0	0
T12	1063784	5	0	0
T18	64580	1	0	0
T20	0	6	0	0
T21	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	46257	1	0	0
T31	0	20	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2498	0	0
T1	4238	1	0	0
T2	510004	4	0	0
T3	121712	1	0	0
T4	3446708	16	0	0
T5	0	22	0	0
T6	0	11	0	0
T7	198448	2	0	0
T8	36720	1	0	0
T12	1063784	5	0	0
T18	64580	1	0	0
T20	0	6	0	0
T21	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	46257	1	0	0
T31	0	20	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2451	0	0
T1	4238	1	0	0
T2	510004	4	0	0
T3	121712	1	0	0
T4	3446708	16	0	0
T5	0	21	0	0
T6	0	11	0	0
T7	198448	2	0	0
T8	36720	1	0	0
T12	1063784	5	0	0
T18	64580	1	0	0
T20	0	6	0	0
T21	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	46257	1	0	0
T31	0	20	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2402	0	0
T1	4238	1	0	0
T2	510004	4	0	0
T3	121712	1	0	0
T4	3446708	14	0	0
T5	0	21	0	0
T6	0	11	0	0
T7	198448	2	0	0
T8	36720	1	0	0
T12	1063784	5	0	0
T18	64580	1	0	0
T20	0	5	0	0
T21	0	3	0	0
T24	0	2	0	0
T25	0	6	0	0
T28	164504	0	0	0
T29	30684	2	0	0
T30	46257	1	0	0
T31	0	20	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4976	0	0
T2	127501	4	0	0
T3	60856	5	0	0
T4	2585031	2	0	0
T5	1442634	75	0	0
T6	267152	21	0	0
T7	99224	0	0	0
T8	27540	0	0	0
T12	797838	0	0	0
T18	32290	1	0	0
T20	922784	0	0	0
T21	279120	0	0	0
T24	292568	9	0	0
T25	921009	0	0	0
T26	0	2	0	0
T27	0	118	0	0
T28	164504	9	0	0
T29	30684	3	0	0
T30	61676	0	0	0
T31	0	20	0	0
T32	0	9	0	0
T33	0	18	0	0
T34	0	5	0	0
T46	74343	0	0	0
T49	0	3	0	0
T71	0	6	0	0
T73	0	4	0	0
T74	0	3	0	0
T75	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	404105	0	0
T2	127501	115	0	0
T3	60856	349	0	0
T4	1723354	0	0	0
T5	1442634	10090	0	0
T6	267152	1434	0	0
T7	99224	0	0	0
T8	18360	0	0	0
T12	531892	0	0	0
T18	32290	146	0	0
T20	922784	0	0	0
T21	279120	0	0	0
T24	585136	912	0	0
T25	1842018	0	0	0
T26	0	54	0	0
T27	0	17582	0	0
T28	123378	841	0	0
T29	23013	1022	0	0
T30	46257	0	0	0
T31	297285	2636	0	0
T32	0	1640	0	0
T33	0	5370	0	0
T34	0	335	0	0
T46	148686	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T49	0	144	0	0
T71	0	377	0	0
T73	0	1260	0	0
T74	0	241	0	0
T75	0	161	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4626	0	0
T2	127501	4	0	0
T3	60856	4	0	0
T4	1723354	0	0	0
T5	1442634	70	0	0
T6	267152	19	0	0
T7	99224	0	0	0
T8	18360	0	0	0
T12	531892	0	0	0
T18	32290	0	0	0
T20	922784	0	0	0
T21	279120	0	0	0
T24	585136	9	0	0
T25	1842018	0	0	0
T26	0	2	0	0
T27	0	117	0	0
T28	123378	9	0	0
T29	23013	3	0	0
T30	46257	0	0	0
T31	297285	16	0	0
T32	0	4	0	0
T33	0	14	0	0
T34	0	15	0	0
T46	148686	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T49	0	4	0	0
T71	0	6	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	229	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	1923512	4	0	0
T6	400728	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	1	0	0
T20	1384176	0	0	0
T21	418680	0	0	0
T24	877704	0	0	0
T25	2763027	0	0	0
T27	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	891855	2	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T46	223029	0	0	0
T47	380421	0	0	0
T48	250431	0	0	0
T51	0	1	0	0
T53	0	10	0	0
T54	0	2	0	0
T58	0	1	0	0
T73	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	5	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5886	0	0
T9	69948	735	0	0
T10	0	1526	0	0
T11	0	1458	0	0
T23	486940	0	0	0
T36	0	1480	0	0
T37	0	687	0	0
T38	14768	0	0	0
T39	35032	0	0	0
T40	887740	0	0	0
T41	549012	0	0	0
T42	115240	0	0	0
T43	786484	0	0	0
T44	6416	0	0	0
T45	41872	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4926	0	0
T9	69948	615	0	0
T10	0	1286	0	0
T11	0	1218	0	0
T23	486940	0	0	0
T36	0	1240	0	0
T37	0	567	0	0
T38	14768	0	0	0
T39	35032	0	0	0
T40	887740	0	0	0
T41	549012	0	0	0
T42	115240	0	0	0
T43	786484	0	0	0
T44	6416	0	0	0
T45	41872	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16952	16556	0	0
T2	510004	509964	0	0
T3	121712	121488	0	0
T4	3446708	3446328	0	0
T7	198448	198236	0	0
T8	36720	36408	0	0
T12	1063784	1063764	0	0
T18	64580	64224	0	0
T28	164504	164204	0	0
T29	30684	30404	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T8

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T8

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T30
1	0	1	Covered	T4,T6,T21
1	1	0	Covered	T3,T18,T4
1	1	1	Covered	T4,T5,T6

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T31
0	1	Covered	T5,T6,T31
1	0	Covered	T4,T32,T33

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T6,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T32,T33

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T31

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T30,T5,T6

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T30
1	Covered	T2,T4,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T8
1	Covered	T5,T20,T31

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T30
1	Covered	T4,T8,T6

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T30,T5,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T8
Phase1St	193	Covered	T2,T4,T8
Phase2St	210	Covered	T2,T4,T8
Phase3St	228	Covered	T2,T4,T8
TerminalSt	244	Covered	T2,T4,T8
TimeoutSt	154	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T4,T8
IdleSt->TimeoutSt	154	Covered	T4,T5,T6
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T32,T33
Phase0St->Phase1St	193	Covered	T2,T4,T8
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T5,T6,T33
Phase1St->Phase2St	210	Covered	T2,T4,T8
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T53,T79,T80
Phase2St->Phase3St	228	Covered	T2,T4,T8
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T4,T56,T81
Phase3St->TerminalSt	244	Covered	T2,T4,T8
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T5,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T5,T6,T31
TimeoutSt->Phase0St	167	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T6,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T53,T79,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T56,T61
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674113279	287	0	0
CheckAccumTrig0_A	674113279	716	0	0
CheckAccumTrig1_A	674113279	59	0	0
CheckClr_A	674113279	336	0	0
CheckEn_A	673960922	221518406	0	0
CheckPhase0_A	674113279	824	0	0
CheckPhase1_A	674113279	810	0	0
CheckPhase2_A	674113279	794	0	0
CheckPhase3_A	674113279	777	0	0
CheckTimeout0_A	674113279	1814	0	0
CheckTimeoutSt1_A	674113279	130994	0	0
CheckTimeoutSt2_A	674113279	1691	0	0
CheckTimeoutStTrig_A	674113279	62	0	0
ErrorStAllEscAsserted_A	674113279	1479	0	0
ErrorStIsTerminal_A	674113279	1239	0	0
u_state_regs_A	674113279	673942298	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	287	0	0
T9	17487	42	0	0
T10	0	76	0	0
T11	0	65	0	0
T23	121735	0	0	0
T36	0	74	0	0
T37	0	30	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	716	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	15	0	0
T5	0	7	0	0
T6	0	4	0	0
T7	49612	0	0	0
T8	9180	1	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	1	0	0
T31	0	5	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	59	0	0
T4	861677	1	0	0
T5	480878	0	0	0
T6	133576	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	1	0	0
T56	0	3	0	0
T57	0	1	0	0
T59	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	336	0	0
T4	861677	14	0	0
T5	480878	6	0	0
T6	133576	3	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T26	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T33	0	4	0	0
T35	0	4	0	0
T46	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673960922	221518406	0	0
T1	4238	3168	0	0
T2	127501	2852	0	0
T3	30428	30371	0	0
T4	861677	197072	0	0
T7	49612	49558	0	0
T8	9180	582	0	0
T12	265946	265551	0	0
T18	16145	16055	0	0
T28	41126	41050	0	0
T29	7671	7600	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	824	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	16	0	0
T5	0	7	0	0
T6	0	5	0	0
T7	49612	0	0	0
T8	9180	1	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	1	0	0
T31	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	810	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	16	0	0
T5	0	6	0	0
T6	0	4	0	0
T7	49612	0	0	0
T8	9180	1	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	1	0	0
T31	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	794	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	16	0	0
T5	0	6	0	0
T6	0	4	0	0
T7	49612	0	0	0
T8	9180	1	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	1	0	0
T31	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	777	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	14	0	0
T5	0	6	0	0
T6	0	4	0	0
T7	49612	0	0	0
T8	9180	1	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T20	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	1	0	0
T31	0	6	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1814	0	0
T4	861677	1	0	0
T5	480878	31	0	0
T6	133576	5	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T26	0	2	0	0
T27	0	52	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0
T32	0	7	0	0
T33	0	9	0	0
T34	0	5	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	130994	0	0
T5	480878	4221	0	0
T6	133576	342	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T26	0	54	0	0
T27	0	8019	0	0
T31	297285	395	0	0
T32	0	1025	0	0
T33	0	3246	0	0
T34	0	335	0	0
T46	74343	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T49	0	40	0	0
T75	0	98	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1691	0	0
T5	480878	30	0	0
T6	133576	4	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T26	0	2	0	0
T27	0	51	0	0
T31	297285	3	0	0
T32	0	3	0	0
T33	0	5	0	0
T34	0	4	0	0
T46	74343	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T49	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	62	0	0
T5	480878	1	0	0
T6	133576	1	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T27	0	1	0	0
T31	297285	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T46	74343	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T53	0	1	0	0
T75	0	1	0	0
T77	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1479	0	0
T9	17487	184	0	0
T10	0	383	0	0
T11	0	356	0	0
T23	121735	0	0	0
T36	0	381	0	0
T37	0	175	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1239	0	0
T9	17487	154	0	0
T10	0	323	0	0
T11	0	296	0	0
T23	121735	0	0	0
T36	0	321	0	0
T37	0	145	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	673942298	0	0
T1	4238	4139	0	0
T2	127501	127491	0	0
T3	30428	30372	0	0
T4	861677	861582	0	0
T7	49612	49559	0	0
T8	9180	9102	0	0
T12	265946	265941	0	0
T18	16145	16056	0	0
T28	41126	41051	0	0
T29	7671	7601	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T1,T4,T12
1	1	0	Covered	T5,T6,T31
1	1	1	Covered	T2,T3,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T18
0	1	Covered	T3,T18,T5
1	0	Covered	T4,T6,T55

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T55

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Not Covered
1	1	Covered	T3,T18,T5

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T1,T5,T48

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T31

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T25,T31

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T5
1	Covered	T2,T3,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T12,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T2,T3,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T12
IdleSt->TimeoutSt	154	Covered	T2,T3,T18
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T4,T33,T53
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T49,T82,T83
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T34,T49,T84
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T35,T43,T49
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T5,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T3,T28
TimeoutSt->Phase0St	167	Covered	T3,T18,T4

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T85,T86
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T49,T82,T83
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T49,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T43,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T5,T71
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674113279	276	0	0
CheckAccumTrig0_A	674113279	499	0	0
CheckAccumTrig1_A	674113279	22	0	0
CheckClr_A	674113279	222	0	0
CheckEn_A	673960922	303570196	0	0
CheckPhase0_A	674113279	573	0	0
CheckPhase1_A	674113279	567	0	0
CheckPhase2_A	674113279	556	0	0
CheckPhase3_A	674113279	541	0	0
CheckTimeout0_A	674113279	1222	0	0
CheckTimeoutSt1_A	674113279	93554	0	0
CheckTimeoutSt2_A	674113279	1138	0	0
CheckTimeoutStTrig_A	674113279	62	0	0
ErrorStAllEscAsserted_A	674113279	1430	0	0
ErrorStIsTerminal_A	674113279	1190	0	0
u_state_regs_A	674113279	673942298	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	276	0	0
T9	17487	37	0	0
T10	0	42	0	0
T11	0	79	0	0
T23	121735	0	0	0
T36	0	90	0	0
T37	0	28	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	499	0	0
T1	4238	1	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	3	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	4	0	0
T33	0	6	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	22	0	0
T4	861677	1	0	0
T5	480878	0	0	0
T6	133576	1	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	222	0	0
T5	480878	3	0	0
T6	133576	0	0	0
T12	265946	1	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673960922	303570196	0	0
T1	4238	3182	0	0
T2	127501	2856	0	0
T3	30428	2372	0	0
T4	861677	782143	0	0
T7	49612	49558	0	0
T8	9180	9101	0	0
T12	265946	35746	0	0
T18	16145	586	0	0
T28	41126	586	0	0
T29	7671	3650	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	573	0	0
T1	4238	1	0	0
T2	127501	1	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	567	0	0
T1	4238	1	0	0
T2	127501	1	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	556	0	0
T1	4238	1	0	0
T2	127501	1	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	541	0	0
T1	4238	1	0	0
T2	127501	1	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T31	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1222	0	0
T2	127501	4	0	0
T3	30428	2	0	0
T4	861677	1	0	0
T5	0	7	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	1	0	0
T24	0	5	0	0
T28	41126	8	0	0
T29	7671	1	0	0
T30	15419	0	0	0
T31	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	93554	0	0
T2	127501	115	0	0
T3	30428	103	0	0
T4	861677	0	0	0
T5	0	909	0	0
T6	0	1	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	146	0	0
T24	0	520	0	0
T28	41126	792	0	0
T29	7671	492	0	0
T30	15419	0	0	0
T31	0	790	0	0
T33	0	863	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1138	0	0
T2	127501	4	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	0	5	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T24	0	5	0	0
T27	0	2	0	0
T28	41126	8	0	0
T29	7671	1	0	0
T30	15419	0	0	0
T31	0	6	0	0
T33	0	2	0	0
T34	0	11	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	62	0	0
T3	30428	1	0	0
T4	861677	0	0	0
T5	480878	2	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T33	0	1	0	0
T42	0	1	0	0
T53	0	9	0	0
T54	0	2	0	0
T74	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1430	0	0
T9	17487	178	0	0
T10	0	363	0	0
T11	0	346	0	0
T23	121735	0	0	0
T36	0	359	0	0
T37	0	184	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1190	0	0
T9	17487	148	0	0
T10	0	303	0	0
T11	0	286	0	0
T23	121735	0	0	0
T36	0	299	0	0
T37	0	154	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	673942298	0	0
T1	4238	4139	0	0
T2	127501	127491	0	0
T3	30428	30372	0	0
T4	861677	861582	0	0
T7	49612	49559	0	0
T8	9180	9102	0	0
T12	265946	265941	0	0
T18	16145	16056	0	0
T28	41126	41051	0	0
T29	7671	7601	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T12

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T7,T4,T29
1	1	0	Covered	T2,T3,T18
1	1	1	Covered	T3,T29,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T29,T5
0	1	Covered	T5,T31,T32
1	0	Covered	T49,T50,T55

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T29,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T50,T55

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T29,T5
1	0	Not Covered
1	1	Covered	T5,T31,T32

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T12,T29
1	Covered	T2,T5,T31

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T29,T5,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T5,T6,T21

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T29,T5
1	Covered	T7,T12,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T12,T29

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T12,T29

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T7,T29,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T7,T12
Phase1St	193	Covered	T2,T7,T12
Phase2St	210	Covered	T2,T7,T12
Phase3St	228	Covered	T2,T7,T12
TerminalSt	244	Covered	T2,T7,T12
TimeoutSt	154	Covered	T3,T29,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T7,T12
IdleSt->TimeoutSt	154	Covered	T3,T29,T5
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T49,T87,T88
Phase0St->Phase1St	193	Covered	T2,T7,T12
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T34,T53,T54
Phase1St->Phase2St	210	Covered	T2,T7,T12
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T5,T33,T23
Phase2St->Phase3St	228	Covered	T2,T7,T12
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T34,T89,T90
Phase3St->TerminalSt	244	Covered	T2,T7,T12
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T29,T5
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T29,T5
TimeoutSt->Phase0St	167	Covered	T5,T31,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T29,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T31,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T29,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T29,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T49,T87,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T53,T54
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T33,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T89,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T29,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674113279	300	0	0
CheckAccumTrig0_A	674113279	530	0	0
CheckAccumTrig1_A	674113279	20	0	0
CheckClr_A	674113279	236	0	0
CheckEn_A	673960922	264911215	0	0
CheckPhase0_A	674113279	593	0	0
CheckPhase1_A	674113279	578	0	0
CheckPhase2_A	674113279	563	0	0
CheckPhase3_A	674113279	552	0	0
CheckTimeout0_A	674113279	595	0	0
CheckTimeoutSt1_A	674113279	71412	0	0
CheckTimeoutSt2_A	674113279	521	0	0
CheckTimeoutStTrig_A	674113279	54	0	0
ErrorStAllEscAsserted_A	674113279	1510	0	0
ErrorStIsTerminal_A	674113279	1270	0	0
u_state_regs_A	674113279	673942298	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	300	0	0
T9	17487	31	0	0
T10	0	93	0	0
T11	0	88	0	0
T23	121735	0	0	0
T36	0	67	0	0
T37	0	21	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	530	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	7	0	0
T6	0	4	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	20	0	0
T15	0	1	0	0
T19	0	3	0	0
T49	992631	1	0	0
T50	31140	1	0	0
T51	8804	0	0	0
T55	0	1	0	0
T64	67313	0	0	0
T65	798343	0	0	0
T66	304996	0	0	0
T67	42748	0	0	0
T68	124147	0	0	0
T69	2657	0	0	0
T70	9545	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	236	0	0
T5	480878	6	0	0
T6	133576	2	0	0
T12	265946	1	0	0
T20	461392	0	0	0
T21	139560	1	0	0
T24	292568	0	0	0
T25	921009	3	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	9	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673960922	264911215	0	0
T1	4238	3209	0	0
T2	127501	2860	0	0
T3	30428	4009	0	0
T4	861677	777748	0	0
T7	49612	2073	0	0
T8	9180	9101	0	0
T12	265946	265051	0	0
T18	16145	13446	0	0
T28	41126	39978	0	0
T29	7671	3137	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	593	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	6	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	578	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	563	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	7	0	0
T6	0	4	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	552	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	7	0	0
T6	0	4	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	1	0	0
T18	16145	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	595	0	0
T3	30428	3	0	0
T4	861677	0	0	0
T5	480878	9	0	0
T6	0	9	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T27	0	49	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	6	0	0
T32	0	2	0	0
T33	0	3	0	0
T71	0	6	0	0
T73	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	71412	0	0
T3	30428	246	0	0
T4	861677	0	0	0
T5	480878	1257	0	0
T6	0	649	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T27	0	7146	0	0
T28	41126	0	0	0
T29	7671	530	0	0
T30	15419	0	0	0
T31	0	1092	0	0
T32	0	615	0	0
T33	0	276	0	0
T71	0	377	0	0
T73	0	1260	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	521	0	0
T3	30428	3	0	0
T4	861677	0	0	0
T5	480878	8	0	0
T6	0	9	0	0
T7	49612	0	0	0
T8	9180	0	0	0
T12	265946	0	0	0
T18	16145	0	0	0
T27	0	49	0	0
T28	41126	0	0	0
T29	7671	2	0	0
T30	15419	0	0	0
T31	0	5	0	0
T32	0	1	0	0
T33	0	3	0	0
T71	0	6	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	54	0	0
T5	480878	1	0	0
T6	133576	0	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T31	297285	1	0	0
T32	0	1	0	0
T39	0	1	0	0
T46	74343	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T51	0	1	0	0
T58	0	1	0	0
T73	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1510	0	0
T9	17487	188	0	0
T10	0	371	0	0
T11	0	403	0	0
T23	121735	0	0	0
T36	0	371	0	0
T37	0	177	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1270	0	0
T9	17487	158	0	0
T10	0	311	0	0
T11	0	343	0	0
T23	121735	0	0	0
T36	0	311	0	0
T37	0	147	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	673942298	0	0
T1	4238	4139	0	0
T2	127501	127491	0	0
T3	30428	30372	0	0
T4	861677	861582	0	0
T7	49612	49559	0	0
T8	9180	9102	0	0
T12	265946	265941	0	0
T18	16145	16056	0	0
T28	41126	41051	0	0
T29	7671	7601	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T12
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T12

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T12

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T18,T4
1	0	1	Covered	T7,T4,T21
1	1	0	Covered	T3,T18,T28
1	1	1	Covered	T28,T5,T6

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T28,T5,T6
0	1	Covered	T5,T31,T33
1	0	Covered	T27,T53,T79

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T28,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T53,T79

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T5,T6
1	0	Not Covered
1	1	Covered	T5,T31,T33

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T6,T24,T31

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T5,T21,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T5
1	Covered	T12,T5,T20

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T5,T6
1	Covered	T2,T7,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T5,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T12,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T7,T12
Phase1St	193	Covered	T2,T7,T12
Phase2St	210	Covered	T2,T7,T12
Phase3St	228	Covered	T2,T7,T12
TerminalSt	244	Covered	T2,T7,T12
TimeoutSt	154	Covered	T28,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T7,T12
IdleSt->TimeoutSt	154	Covered	T28,T5,T6
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T95,T87,T96
Phase0St->Phase1St	193	Covered	T2,T7,T12
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T34,T94,T97
Phase1St->Phase2St	210	Covered	T2,T7,T12
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T98,T99,T100
Phase2St->Phase3St	228	Covered	T2,T7,T12
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T20,T55,T59
Phase3St->TerminalSt	244	Covered	T2,T7,T12
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T5,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T28,T5,T6
TimeoutSt->Phase0St	167	Covered	T5,T31,T33

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T31,T33
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T28,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T28,T5,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T95,T87,T96
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T94,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T98,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T55,T59
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674113279	304	0	0
CheckAccumTrig0_A	674113279	495	0	0
CheckAccumTrig1_A	674113279	16	0	0
CheckClr_A	674113279	213	0	0
CheckEn_A	673960922	273276968	0	0
CheckPhase0_A	674113279	551	0	0
CheckPhase1_A	674113279	543	0	0
CheckPhase2_A	674113279	538	0	0
CheckPhase3_A	674113279	532	0	0
CheckTimeout0_A	674113279	1345	0	0
CheckTimeoutSt1_A	674113279	108145	0	0
CheckTimeoutSt2_A	674113279	1276	0	0
CheckTimeoutStTrig_A	674113279	51	0	0
ErrorStAllEscAsserted_A	674113279	1467	0	0
ErrorStIsTerminal_A	674113279	1227	0	0
u_state_regs_A	674113279	673942298	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	304	0	0
T9	17487	16	0	0
T10	0	87	0	0
T11	0	91	0	0
T23	121735	0	0	0
T36	0	70	0	0
T37	0	40	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	495	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	2	0	0
T6	0	2	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	16	0	0
T19	0	1	0	0
T22	270822	0	0	0
T27	857523	1	0	0
T53	0	1	0	0
T72	54684	0	0	0
T79	0	1	0	0
T83	0	1	0	0
T95	117979	0	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	134470	0	0	0
T107	47805	0	0	0
T108	480134	0	0	0
T109	716975	0	0	0
T110	436549	0	0	0
T111	27045	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	213	0	0
T5	480878	2	0	0
T6	133576	1	0	0
T12	265946	1	0	0
T20	461392	3	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T27	0	2	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T34	0	1	0	0
T73	0	1	0	0
T95	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673960922	273276968	0	0
T1	4238	3222	0	0
T2	127501	807	0	0
T3	30428	30371	0	0
T4	861677	792559	0	0
T7	49612	2092	0	0
T8	9180	9101	0	0
T12	265946	36404	0	0
T18	16145	14410	0	0
T28	41126	38898	0	0
T29	7671	7600	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	551	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	543	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	538	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	532	0	0
T2	127501	1	0	0
T3	30428	0	0	0
T4	861677	0	0	0
T5	0	3	0	0
T6	0	2	0	0
T7	49612	1	0	0
T8	9180	0	0	0
T12	265946	2	0	0
T18	16145	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	41126	0	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1345	0	0
T5	480878	28	0	0
T6	133576	6	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	4	0	0
T25	921009	0	0	0
T27	0	17	0	0
T28	41126	1	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	4	0	0
T33	0	6	0	0
T46	74343	0	0	0
T49	0	3	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	108145	0	0
T5	480878	3703	0	0
T6	133576	442	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	392	0	0
T25	921009	0	0	0
T27	0	2417	0	0
T28	41126	49	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	359	0	0
T33	0	985	0	0
T46	74343	0	0	0
T49	0	104	0	0
T74	0	241	0	0
T75	0	63	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1276	0	0
T5	480878	27	0	0
T6	133576	6	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	4	0	0
T25	921009	0	0	0
T27	0	15	0	0
T28	41126	1	0	0
T29	7671	0	0	0
T30	15419	0	0	0
T31	0	2	0	0
T33	0	4	0	0
T46	74343	0	0	0
T49	0	3	0	0
T74	0	2	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	51	0	0
T5	480878	1	0	0
T6	133576	0	0	0
T20	461392	0	0	0
T21	139560	0	0	0
T24	292568	0	0	0
T25	921009	0	0	0
T27	0	1	0	0
T31	297285	2	0	0
T33	0	2	0	0
T46	74343	0	0	0
T47	126807	0	0	0
T48	83477	0	0	0
T74	0	1	0	0
T91	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1467	0	0
T9	17487	185	0	0
T10	0	409	0	0
T11	0	353	0	0
T23	121735	0	0	0
T36	0	369	0	0
T37	0	151	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	1227	0	0
T9	17487	155	0	0
T10	0	349	0	0
T11	0	293	0	0
T23	121735	0	0	0
T36	0	309	0	0
T37	0	121	0	0
T38	3692	0	0	0
T39	8758	0	0	0
T40	221935	0	0	0
T41	137253	0	0	0
T42	28810	0	0	0
T43	196621	0	0	0
T44	1604	0	0	0
T45	10468	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674113279	673942298	0	0
T1	4238	4139	0	0
T2	127501	127491	0	0
T3	30428	30372	0	0
T4	861677	861582	0	0
T7	49612	49559	0	0
T8	9180	9102	0	0
T12	265946	265941	0	0
T18	16145	16056	0	0
T28	41126	41051	0	0
T29	7671	7601	0	0