Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65217694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31534477

1

T1

105933

T2

1731

T3

142854

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14632903	1			T1	42114		T2	636		T3	56073
values[0x0]	40098535	1			T1	147471		T2	2199		T3	197316
values[0x1]	42020733	1			T1	146982		T2	2249		T3	197212

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55750686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41001485

1

T1

134344

T2

2150

T3

180287

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	549334	1			T1	1310		T2	7		T3	1711
valid_sources[0x01]	589830	1			T1	1278		T3	1740		T4	5
valid_sources[0x02]	537712	1			T1	1319		T2	42		T3	1769
valid_sources[0x03]	289752	1			T1	1200		T2	5		T3	1758
valid_sources[0x04]	334318	1			T1	1452		T2	15		T3	1716
valid_sources[0x05]	496209	1			T1	1291		T2	13		T3	1779
valid_sources[0x06]	705330	1			T1	1460		T2	20		T3	1833
valid_sources[0x07]	283968	1			T1	1324		T2	14		T3	1787
valid_sources[0x08]	278178	1			T1	1453		T2	18		T3	1754
valid_sources[0x09]	648184	1			T1	1405		T2	29		T3	1784
valid_sources[0x0a]	283380	1			T1	1230		T2	14		T3	1779
valid_sources[0x0b]	542416	1			T1	1258		T2	44		T3	1652
valid_sources[0x0c]	882060	1			T1	1309		T2	7		T3	1772
valid_sources[0x0d]	280117	1			T1	1291		T2	42		T3	1798
valid_sources[0x0e]	511160	1			T1	1257		T2	21		T3	1765
valid_sources[0x0f]	282949	1			T1	1287		T2	1		T3	1747
valid_sources[0x10]	279632	1			T1	1291		T2	29		T3	1685
valid_sources[0x11]	283745	1			T1	1241		T2	24		T3	1811
valid_sources[0x12]	286710	1			T1	1296		T2	24		T3	1776
valid_sources[0x13]	293885	1			T1	1335		T2	17		T3	1781
valid_sources[0x14]	592129	1			T1	1335		T2	44		T3	1745
valid_sources[0x15]	291408	1			T1	1457		T2	34		T3	1734
valid_sources[0x16]	284452	1			T1	1484		T2	18		T3	1830
valid_sources[0x17]	337473	1			T1	1364		T2	15		T3	1784
valid_sources[0x18]	713075	1			T1	1180		T2	31		T3	1792
valid_sources[0x19]	278690	1			T1	1343		T2	66		T3	1630
valid_sources[0x1a]	282297	1			T1	1222		T2	9		T3	1715
valid_sources[0x1b]	285386	1			T1	1240		T2	18		T3	1843
valid_sources[0x1c]	1127025	1			T1	1368		T2	24		T3	1890
valid_sources[0x1d]	287359	1			T1	1365		T2	19		T3	1782
valid_sources[0x1e]	273740	1			T1	1447		T2	9		T3	1712
valid_sources[0x1f]	272728	1			T1	1389		T2	19		T3	1828
valid_sources[0x20]	281213	1			T1	1340		T2	10		T3	1757
valid_sources[0x21]	286443	1			T1	1367		T2	11		T3	1715
valid_sources[0x22]	508565	1			T1	1265		T2	2		T3	1770
valid_sources[0x23]	291472	1			T1	1403		T2	15		T3	1876
valid_sources[0x24]	735154	1			T1	1333		T2	11		T3	1703
valid_sources[0x25]	292083	1			T1	1328		T2	55		T3	1766
valid_sources[0x26]	281347	1			T1	1399		T2	10		T3	1790
valid_sources[0x27]	618551	1			T1	1207		T2	23		T3	1779
valid_sources[0x28]	662514	1			T1	1291		T2	27		T3	1813
valid_sources[0x29]	278605	1			T1	1259		T2	7		T3	1649
valid_sources[0x2a]	291388	1			T1	1122		T2	11		T3	1708
valid_sources[0x2b]	280738	1			T1	1364		T2	1		T3	1721
valid_sources[0x2c]	286370	1			T1	1311		T2	13		T3	1650
valid_sources[0x2d]	283370	1			T1	1315		T2	43		T3	1758
valid_sources[0x2e]	616058	1			T1	1420		T2	3		T3	1796
valid_sources[0x2f]	286538	1			T1	1405		T2	10		T3	1819
valid_sources[0x30]	675945	1			T1	1341		T2	3		T3	1723
valid_sources[0x31]	720872	1			T1	1496		T2	22		T3	1878
valid_sources[0x32]	282479	1			T1	1303		T2	60		T3	1716
valid_sources[0x33]	277330	1			T1	1297		T2	38		T3	1736
valid_sources[0x34]	292075	1			T1	1309		T2	22		T3	1770
valid_sources[0x35]	288797	1			T1	1318		T2	34		T3	1820
valid_sources[0x36]	280596	1			T1	1234		T2	14		T3	1715
valid_sources[0x37]	293505	1			T1	1431		T2	11		T3	1765
valid_sources[0x38]	282207	1			T1	1309		T2	28		T3	1728
valid_sources[0x39]	284061	1			T1	1326		T2	12		T3	1883
valid_sources[0x3a]	283671	1			T1	1223		T2	26		T3	1765
valid_sources[0x3b]	564687	1			T1	1236		T2	8		T3	1789
valid_sources[0x3c]	294357	1			T1	1252		T2	36		T3	1748
valid_sources[0x3d]	282698	1			T1	1401		T2	26		T3	1736
valid_sources[0x3e]	329333	1			T1	1370		T2	17		T3	1770
valid_sources[0x3f]	281263	1			T1	1371		T2	41		T3	1722
valid_sources[0x40]	292764	1			T1	1251		T2	12		T3	1793
valid_sources[0x41]	291280	1			T1	1236		T2	10		T3	1770
valid_sources[0x42]	285635	1			T1	1230		T2	26		T3	1817
valid_sources[0x43]	283947	1			T1	1316		T2	23		T3	1733
valid_sources[0x44]	279449	1			T1	1383		T2	20		T3	1777
valid_sources[0x45]	283168	1			T1	1368		T2	14		T3	1678
valid_sources[0x46]	283882	1			T1	1307		T2	29		T3	1799
valid_sources[0x47]	1101055	1			T1	1296		T2	22		T3	1741
valid_sources[0x48]	291887	1			T1	1393		T2	21		T3	1725
valid_sources[0x49]	286132	1			T1	1202		T2	17		T3	1761
valid_sources[0x4a]	280110	1			T1	1420		T2	18		T3	1756
valid_sources[0x4b]	272971	1			T1	1237		T2	34		T3	1747
valid_sources[0x4c]	277019	1			T1	1350		T2	7		T3	1787
valid_sources[0x4d]	279416	1			T1	1295		T2	20		T3	1739
valid_sources[0x4e]	278463	1			T1	1248		T2	33		T3	1742
valid_sources[0x4f]	306059	1			T1	1332		T2	18		T3	1777
valid_sources[0x50]	740977	1			T1	1423		T2	8		T3	1785
valid_sources[0x51]	282798	1			T1	1352		T2	8		T3	1744
valid_sources[0x52]	567485	1			T1	1459		T2	49		T3	1827
valid_sources[0x53]	282545	1			T1	1275		T2	15		T3	1718
valid_sources[0x54]	289967	1			T1	1162		T2	13		T3	1845
valid_sources[0x55]	285289	1			T1	1233		T2	28		T3	1776
valid_sources[0x56]	779534	1			T1	1325		T2	30		T3	1769
valid_sources[0x57]	274818	1			T1	1342		T2	5		T3	1844
valid_sources[0x58]	296705	1			T1	1265		T2	3		T3	1778
valid_sources[0x59]	294348	1			T1	1294		T2	10		T3	1777
valid_sources[0x5a]	285986	1			T1	1416		T2	12		T3	1852
valid_sources[0x5b]	283230	1			T1	1184		T2	14		T3	1666
valid_sources[0x5c]	274216	1			T1	1333		T2	21		T3	1779
valid_sources[0x5d]	300266	1			T1	1167		T2	10		T3	1716
valid_sources[0x5e]	283299	1			T1	1225		T2	14		T3	1690
valid_sources[0x5f]	275833	1			T1	1281		T2	47		T3	1747
valid_sources[0x60]	730876	1			T1	1409		T2	5		T3	1777
valid_sources[0x61]	282291	1			T1	1327		T2	65		T3	1807
valid_sources[0x62]	287998	1			T1	1313		T2	21		T3	1677
valid_sources[0x63]	1076652	1			T1	1384		T2	24		T3	1722
valid_sources[0x64]	285078	1			T1	1377		T2	20		T3	1821
valid_sources[0x65]	674253	1			T1	1384		T2	30		T3	1711
valid_sources[0x66]	281119	1			T1	1419		T2	22		T3	1781
valid_sources[0x67]	286228	1			T1	1283		T2	6		T3	1687
valid_sources[0x68]	298579	1			T1	1330		T2	5		T3	1733
valid_sources[0x69]	301832	1			T1	1156		T2	17		T3	1674
valid_sources[0x6a]	287983	1			T1	1337		T2	28		T3	1810
valid_sources[0x6b]	286291	1			T1	1297		T2	15		T3	1808
valid_sources[0x6c]	580564	1			T1	1366		T2	6		T3	1804
valid_sources[0x6d]	288634	1			T1	1310		T2	9		T3	1759
valid_sources[0x6e]	328554	1			T1	1247		T2	5		T3	1824
valid_sources[0x6f]	284453	1			T1	1345		T2	17		T3	1800
valid_sources[0x70]	287994	1			T1	1252		T2	36		T3	1772
valid_sources[0x71]	507453	1			T1	1231		T2	7		T3	1699
valid_sources[0x72]	651577	1			T1	1384		T2	17		T3	1779
valid_sources[0x73]	279040	1			T1	1515		T2	19		T3	1765
valid_sources[0x74]	279349	1			T1	1288		T2	29		T3	1761
valid_sources[0x75]	769286	1			T1	1253		T2	37		T3	1810
valid_sources[0x76]	298048	1			T1	1304		T2	25		T3	1722
valid_sources[0x77]	296865	1			T1	1282		T2	11		T3	1783
valid_sources[0x78]	694037	1			T1	1345		T2	33		T3	1850
valid_sources[0x79]	782106	1			T1	1262		T2	19		T3	1728
valid_sources[0x7a]	286837	1			T1	1254		T2	26		T3	1834
valid_sources[0x7b]	283677	1			T1	1272		T2	24		T3	1688
valid_sources[0x7c]	277637	1			T1	1388		T2	26		T3	1755
valid_sources[0x7d]	281562	1			T1	1439		T2	15		T3	1654
valid_sources[0x7e]	279435	1			T1	1424		T2	6		T3	1799
valid_sources[0x7f]	277004	1			T1	1608		T2	19		T3	1765
valid_sources[0x80]	280766	1			T1	1326		T2	6		T3	1850

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7246473

1

T1

21169

T2

322

T3

28065

values[0x0]

all_enables

biggest_size

15341559

1

T1

54321

T2

859

T3

73262

values[0x1]

all_enables

biggest_size

8946445

1

T1

30443

T2

550

T3

41527