Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T88,T186
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14269	0	0
DisabledNoTrigBkwd_A	2147483647	791613	0	0
DisabledNoTrigFwd_A	2147483647	1511211851	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14269	0	0
T17	3174	879	0	0
T22	537985	0	0	0
T23	167802	0	0	0
T31	26025	0	0	0
T33	481611	0	0	0
T65	16500	0	0	0
T66	74680	0	0	0
T67	879979	0	0	0
T77	43568	0	0	0
T78	49209	0	0	0
T88	1118	314	0	0
T186	0	537	0	0
T187	0	599	0	0
T188	0	594	0	0
T189	0	529	0	0
T190	0	903	0	0
T191	0	793	0	0
T192	0	1148	0	0
T193	0	491	0	0
T194	0	522	0	0
T195	0	400	0	0
T196	0	1390	0	0
T197	3971	933	0	0
T198	0	736	0	0
T199	0	367	0	0
T200	0	845	0	0
T201	0	730	0	0
T202	0	834	0	0
T203	5608	0	0	0
T204	26156	0	0	0
T205	413199	0	0	0
T206	44588	0	0	0
T207	143078	0	0	0
T208	249733	0	0	0
T209	317255	0	0	0
T210	308851	0	0	0
T211	37992	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	791613	0	0
T1	216996	99	0	0
T2	3583360	11	0	0
T3	107848	0	0	0
T4	2209188	0	0	0
T5	588968	1376	0	0
T6	109808	0	0	0
T7	0	3829	0	0
T8	0	1148	0	0
T9	0	28	0	0
T13	0	1464	0	0
T14	0	7802	0	0
T15	0	20476	0	0
T16	174040	64	0	0
T17	12696	12	0	0
T18	72376	14	0	0
T19	65288	0	0	0
T20	22730	65	0	0
T21	0	2203	0	0
T32	0	509	0	0
T47	0	1	0	0
T48	0	8361	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1511211851	0	0
T1	289328	108270	0	0
T2	3583360	1227813	0	0
T3	107848	90912	0	0
T4	2209188	1138396	0	0
T5	588968	299056	0	0
T6	109808	8535	0	0
T16	174040	27510	0	0
T17	12696	8309	0	0
T18	72376	57159	0	0
T19	65288	46834	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T88,T186,T187
1	1	Covered	T1,T2,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667717896	8082	0	0
DisabledNoTrigBkwd_A	667717896	208982	0	0
DisabledNoTrigFwd_A	667717896	328244904	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	8082	0	0
T22	537985	0	0	0
T23	167802	0	0	0
T31	26025	0	0	0
T33	481611	0	0	0
T65	16500	0	0	0
T66	74680	0	0	0
T67	879979	0	0	0
T77	43568	0	0	0
T78	49209	0	0	0
T88	1118	314	0	0
T186	0	537	0	0
T187	0	599	0	0
T190	0	903	0	0
T192	0	1148	0	0
T193	0	491	0	0
T195	0	400	0	0
T196	0	1390	0	0
T200	0	845	0	0
T201	0	730	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	208982	0	0
T1	72332	28	0	0
T2	895840	5	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	384	0	0
T6	27452	0	0	0
T13	0	1407	0	0
T14	0	1422	0	0
T15	0	4624	0	0
T16	43510	21	0	0
T17	3174	0	0	0
T18	18094	14	0	0
T19	16322	0	0	0
T20	0	4	0	0
T21	0	46	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	328244904	0	0
T1	72332	19273	0	0
T2	895840	245598	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	583	0	0
T6	27452	2118	0	0
T16	43510	5769	0	0
T17	3174	2051	0	0
T18	18094	3033	0	0
T19	16322	6731	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T16,T5
1	1	Covered	T1,T3,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197
1	1	Covered	T1,T3,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667717896	933	0	0
DisabledNoTrigBkwd_A	667717896	209621	0	0
DisabledNoTrigFwd_A	667717896	367731881	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	933	0	0
T197	3971	933	0	0
T203	5608	0	0	0
T204	26156	0	0	0
T205	413199	0	0	0
T206	44588	0	0	0
T207	143078	0	0	0
T208	249733	0	0	0
T209	317255	0	0	0
T210	308851	0	0	0
T211	37992	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	209621	0	0
T1	72332	27	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	989	0	0
T6	27452	0	0	0
T7	0	1655	0	0
T9	0	27	0	0
T13	0	9	0	0
T14	0	3983	0	0
T15	0	8625	0	0
T16	43510	13	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T32	0	480	0	0
T48	0	111	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	367731881	0	0
T1	72332	2059	0	0
T2	895840	48631	0	0
T3	26962	23368	0	0
T4	552297	91334	0	0
T5	147242	4671	0	0
T6	27452	2125	0	0
T16	43510	5783	0	0
T17	3174	2069	0	0
T18	18094	18042	0	0
T19	16322	15249	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T189,T202
1	1	Covered	T2,T3,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667717896	2242	0	0
DisabledNoTrigBkwd_A	667717896	187891	0	0
DisabledNoTrigFwd_A	667717896	417704770	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	2242	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	997766	0	0	0
T13	929117	0	0	0
T17	3174	879	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0
T21	114671	0	0	0
T189	0	529	0	0
T202	0	834	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	187891	0	0
T2	895840	6	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	3	0	0
T6	27452	0	0	0
T8	0	1148	0	0
T13	0	48	0	0
T15	0	2395	0	0
T16	43510	23	0	0
T17	3174	12	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	26	0	0
T21	0	1262	0	0
T47	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	417704770	0	0
T1	72332	72265	0	0
T2	895840	37837	0	0
T3	26962	13786	0	0
T4	552297	492581	0	0
T5	147242	146774	0	0
T6	27452	2142	0	0
T16	43510	10149	0	0
T17	3174	2087	0	0
T18	18094	18042	0	0
T19	16322	10648	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T17
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T16,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T191,T194
1	1	Covered	T1,T16,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	667717896	3012	0	0
DisabledNoTrigBkwd_A	667717896	185119	0	0
DisabledNoTrigFwd_A	667717896	397530296	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	3012	0	0
T96	35175	0	0	0
T101	130686	0	0	0
T188	1425	594	0	0
T191	0	793	0	0
T194	0	522	0	0
T198	0	736	0	0
T199	0	367	0	0
T212	1742	0	0	0
T213	21980	0	0	0
T214	152923	0	0	0
T215	62772	0	0	0
T216	147174	0	0	0
T217	98840	0	0	0
T218	132841	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	185119	0	0
T1	72332	44	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	2174	0	0
T9	0	1	0	0
T14	0	2397	0	0
T15	0	4832	0	0
T16	43510	7	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	35	0	0
T21	0	895	0	0
T32	0	29	0	0
T48	0	8250	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	397530296	0	0
T1	72332	14673	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	2252	0	0
T5	147242	147028	0	0
T6	27452	2150	0	0
T16	43510	5809	0	0
T17	3174	2102	0	0
T18	18094	18042	0	0
T19	16322	14206	0	0