Unified Coverage Report :: Module :: alert_handler_ping_timer

Module : alert_handler_ping_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.46	100.00	97.30		60.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer	99.46	100.00	97.30		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ping_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.46	100.00	97.30		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	97.44	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_buf_spurious_alert_ping	100.00	100.00
u_prim_buf_spurious_esc_ping	100.00	100.00
u_prim_count_cnt	100.00			100.00
u_prim_count_esc_cnt	100.00			100.00
u_prim_double_lfsr	100.00	100.00	100.00	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	138	4	4	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	320	37	37	100.00
ALWAYS	415	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
78	1	1
79	1	1
82	1	1
83	1	1
85	1	1
96	1	1
131	1	1
138	1	1
139	1	1
141	1	1
142	1	1
			MISSING_ELSE
149	1	1
153	1	1
193	1	1
226	1	1
227	1	1
253	1	1
254	1	1
257	1	1
267	1	1
268	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
328	1	1
330	1	1
335	1	1
336	1	1
337	1	1
			MISSING_ELSE
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
			MISSING_ELSE
			MISSING_ELSE
388	1	1
389	1	1
401	1	1
402	1	1
403	1	1
404	1	1
			MISSING_ELSE
415	3	3

---

Cond Coverage for Module : alert_handler_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       131
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION ((esc_cnt >= 16'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ----------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       226
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       227
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       257
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       354
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T4,T5
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T5,T6,T7
1	0	0	Covered	T2,T4,T8

 LINE       374
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T9

 LINE       401
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

---

FSM Coverage for Module : alert_handler_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	6	60.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	343	Covered	T2,T4,T5
AlertWaitSt	336	Covered	T2,T4,T5
EscPingSt	365	Covered	T2,T4,T5
EscWaitSt	355	Covered	T2,T4,T5
FsmErrorSt	402	Covered	T10,T11,T12
InitSt	334	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertPingSt->EscWaitSt	355	Covered	T2,T4,T5
AlertPingSt->FsmErrorSt	402	Not Covered
AlertWaitSt->AlertPingSt	343	Covered	T2,T4,T5
AlertWaitSt->FsmErrorSt	402	Covered	T10,T11,T12
EscPingSt->AlertWaitSt	375	Covered	T2,T4,T5
EscPingSt->FsmErrorSt	402	Not Covered
EscWaitSt->EscPingSt	365	Covered	T2,T4,T5
EscWaitSt->FsmErrorSt	402	Not Covered
InitSt->AlertWaitSt	336	Covered	T2,T4,T5
InitSt->FsmErrorSt	402	Not Covered

---

Branch Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	75	3	3	100.00
TERNARY	96	2	2	100.00
TERNARY	131	2	2	100.00
TERNARY	257	2	2	100.00
IF	82	2	2	100.00
IF	138	3	3	100.00
CASE	330	14	14	100.00
IF	401	2	2	100.00
IF	415	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((reseed_timer_q > '0)) ? 
-2-:	75	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if ((!rst_ni))
-2-:	141	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	335	if (en_i)
-3-:	342	if (timer_expired)
-4-:	354	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	357	if (timer_expired)
-6-:	364	if (timer_expired)
-7-:	374	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	378	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T4,T5
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T4,T5
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T4,T5
AlertPingSt	-	-	1	1	-	-	-	Covered	T2,T4,T8
AlertPingSt	-	-	1	0	-	-	-	Covered	T5,T6,T7
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T4,T5
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T4,T5
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	1	1	Covered	T2,T4,T9
EscPingSt	-	-	-	-	-	1	0	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	401	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	667717896	192845	0	0
EscPingOH_A	667717896	128246	0	0
MaxIdDw_A	626	626	0	0
PingOH0_A	667717896	667542665	0	0
WaitCycMaskIsRightAlignedMask_A	667717896	667542665	0	0
WaitCycMaskMin_A	667717896	667542665	0	0
u_state_regs_A	667717896	667542665	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	192845	0	0
T2	895840	450	0	0
T3	26962	0	0	0
T4	552297	1331	0	0
T5	147242	8	0	0
T6	27452	2667	0	0
T7	0	63	0	0
T8	0	156	0	0
T9	0	3209	0	0
T13	0	115	0	0
T14	0	356	0	0
T15	0	303	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	128246	0	0
T2	895840	330	0	0
T3	26962	0	0	0
T4	552297	855	0	0
T5	147242	100	0	0
T6	27452	2680	0	0
T7	0	75	0	0
T8	0	150	0	0
T9	0	2273	0	0
T13	0	55	0	0
T14	0	270	0	0
T15	0	215	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626	626	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

Line Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	138	4	4	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
ALWAYS	320	37	37	100.00
ALWAYS	415	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
78	1	1
79	1	1
82	1	1
83	1	1
85	1	1
96	1	1
131	1	1
138	1	1
139	1	1
141	1	1
142	1	1
			MISSING_ELSE
149	1	1
153	1	1
193	1	1
226	1	1
227	1	1
253	1	1
254	1	1
257	1	1
267	1	1
268	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
328	1	1
330	1	1
335	1	1
336	1	1
337	1	1
			MISSING_ELSE
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
			MISSING_ELSE
			MISSING_ELSE
388	1	1
389	1	1
401	1	1
402	1	1
403	1	1
404	1	1
			MISSING_ELSE
415	3	3

---

Cond Coverage for Instance : tb.dut.u_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       131
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION ((esc_cnt >= 16'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ----------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       226
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       227
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       257
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       354
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T4,T5
0	0	1	Covered	T5,T6,T7
0	1	0	Covered	T5,T6,T7
1	0	0	Covered	T2,T4,T8

 LINE       374
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T9

 LINE       401
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T10,T11,T12
0	1	0	Covered	T10,T11,T12
1	0	0	Covered	T10,T11,T12

---

FSM Coverage for Instance : tb.dut.u_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	343	Covered	T2,T4,T5
AlertWaitSt	336	Covered	T2,T4,T5
EscPingSt	365	Covered	T2,T4,T5
EscWaitSt	355	Covered	T2,T4,T5
FsmErrorSt	402	Covered	T10,T11,T12
InitSt	334	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AlertPingSt->EscWaitSt	355	Covered	T2,T4,T5
AlertPingSt->FsmErrorSt	402	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
AlertWaitSt->AlertPingSt	343	Covered	T2,T4,T5
AlertWaitSt->FsmErrorSt	402	Covered	T10,T11,T12
EscPingSt->AlertWaitSt	375	Covered	T2,T4,T5
EscPingSt->FsmErrorSt	402	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
EscWaitSt->EscPingSt	365	Covered	T2,T4,T5
EscWaitSt->FsmErrorSt	402	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
InitSt->AlertWaitSt	336	Covered	T2,T4,T5
InitSt->FsmErrorSt	402	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.

---

Branch Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	75	3	3	100.00
TERNARY	96	2	2	100.00
TERNARY	131	2	2	100.00
TERNARY	257	2	2	100.00
IF	82	2	2	100.00
IF	138	3	3	100.00
CASE	330	14	14	100.00
IF	401	2	2	100.00
IF	415	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	((reseed_timer_q > '0)) ? 
-2-:	75	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if ((!rst_ni))
-2-:	141	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	335	if (en_i)
-3-:	342	if (timer_expired)
-4-:	354	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	357	if (timer_expired)
-6-:	364	if (timer_expired)
-7-:	374	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	378	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T4,T5
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T4,T5
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T4,T5
AlertPingSt	-	-	1	1	-	-	-	Covered	T2,T4,T8
AlertPingSt	-	-	1	0	-	-	-	Covered	T5,T6,T7
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T4,T5
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T4,T5
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	1	1	Covered	T2,T4,T9
EscPingSt	-	-	-	-	-	1	0	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	401	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	667717896	192845	0	0
EscPingOH_A	667717896	128246	0	0
MaxIdDw_A	626	626	0	0
PingOH0_A	667717896	667542665	0	0
WaitCycMaskIsRightAlignedMask_A	667717896	667542665	0	0
WaitCycMaskMin_A	667717896	667542665	0	0
u_state_regs_A	667717896	667542665	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	192845	0	0
T2	895840	450	0	0
T3	26962	0	0	0
T4	552297	1331	0	0
T5	147242	8	0	0
T6	27452	2667	0	0
T7	0	63	0	0
T8	0	156	0	0
T9	0	3209	0	0
T13	0	115	0	0
T14	0	356	0	0
T15	0	303	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	128246	0	0
T2	895840	330	0	0
T3	26962	0	0	0
T4	552297	855	0	0
T5	147242	100	0	0
T6	27452	2680	0	0
T7	0	75	0	0
T8	0	150	0	0
T9	0	2273	0	0
T13	0	55	0	0
T14	0	270	0	0
T15	0	215	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626	626	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0