Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T18
1	0	1	Covered	T16,T17,T4
1	1	0	Covered	T1,T3,T20
1	1	1	Covered	T1,T3,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T19
0	1	Covered	T3,T21,T13
1	0	Covered	T15,T22,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T15,T22,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T24,T25,T26
1	1	Covered	T3,T21,T13

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T2,T16,T17

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T5,T13

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T3,T16,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T3,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T16
IdleSt->TimeoutSt	154	Covered	T1,T3,T19
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T1,T23,T27
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T22,T28,T29
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T2,T30,T31
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T32,T33,T34
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T3,T19
TimeoutSt->Phase0St	167	Covered	T3,T21,T13

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T27,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T33,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1018	0	0
CheckAccumTrig0_A	2147483647	2428	0	0
CheckAccumTrig1_A	2147483647	127	0	0
CheckClr_A	2147483647	1189	0	0
CheckEn_A	2147483647	1190965262	0	0
CheckPhase0_A	2147483647	2776	0	0
CheckPhase1_A	2147483647	2722	0	0
CheckPhase2_A	2147483647	2661	0	0
CheckPhase3_A	2147483647	2615	0	0
CheckTimeout0_A	2147483647	4333	0	0
CheckTimeoutSt1_A	2147483647	537370	0	0
CheckTimeoutSt2_A	2147483647	3932	0	0
CheckTimeoutStTrig_A	2147483647	259	0	0
ErrorStAllEscAsserted_A	2147483647	5817	0	0
ErrorStIsTerminal_A	2147483647	4857	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1018	0	0
T10	122660	257	0	0
T11	0	103	0	0
T12	0	240	0	0
T36	0	257	0	0
T37	0	161	0	0
T38	469600	0	0	0
T39	1518276	0	0	0
T40	1193412	0	0	0
T41	141264	0	0	0
T42	294120	0	0	0
T43	524232	0	0	0
T44	1676704	0	0	0
T45	972988	0	0	0
T46	68516	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T1	216996	6	0	0
T2	3583360	7	0	0
T3	107848	0	0	0
T4	2209188	0	0	0
T5	588968	4	0	0
T6	109808	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	0	6	0	0
T14	0	3	0	0
T15	0	28	0	0
T16	174040	4	0	0
T17	12696	1	0	0
T18	72376	1	0	0
T19	65288	0	0	0
T20	22730	5	0	0
T21	0	3	0	0
T32	0	9	0	0
T47	0	1	0	0
T48	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	127	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T15	948793	1	0	0
T22	537985	1	0	0
T23	335604	3	0	0
T27	0	3	0	0
T28	386266	0	0	0
T31	26025	0	0	0
T32	189492	0	0	0
T33	481611	0	0	0
T44	0	2	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	3	0	0
T65	16500	0	0	0
T66	74680	0	0	0
T67	1759958	0	0	0
T68	21192	0	0	0
T69	224828	0	0	0
T70	195628	0	0	0
T71	315934	0	0	0
T72	59962	0	0	0
T73	904328	0	0	0
T74	30851	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1189	0	0
T1	144664	3	0	0
T2	2687520	6	0	0
T3	80886	0	0	0
T4	1656891	0	0	0
T5	441726	1	0	0
T6	82356	0	0	0
T7	997766	0	0	0
T8	215878	1	0	0
T9	120968	0	0	0
T13	929117	1	0	0
T14	375634	0	0	0
T15	948793	12	0	0
T16	130530	0	0	0
T17	9522	0	0	0
T18	54282	0	0	0
T19	48966	0	0	0
T20	45460	2	0	0
T21	114671	0	0	0
T22	0	16	0	0
T23	0	14	0	0
T30	0	10	0	0
T31	0	3	0	0
T32	0	8	0	0
T33	0	5	0	0
T47	751918	1	0	0
T48	502666	0	0	0
T50	0	2	0	0
T65	0	2	0	0
T66	0	3	0	0
T70	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T76	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1190965262	0	0
T1	289328	95684	0	0
T2	3583360	982796	0	0
T3	107848	77723	0	0
T4	2209188	1138394	0	0
T5	588968	158060	0	0
T6	109808	8531	0	0
T16	174040	23158	0	0
T17	12696	8309	0	0
T18	72376	57156	0	0
T19	65288	46831	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2776	0	0
T1	216996	5	0	0
T2	3583360	7	0	0
T3	107848	1	0	0
T4	2209188	0	0	0
T5	588968	4	0	0
T6	109808	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	0	8	0	0
T14	0	3	0	0
T15	0	29	0	0
T16	174040	4	0	0
T17	12696	1	0	0
T18	72376	1	0	0
T19	65288	0	0	0
T20	22730	5	0	0
T21	0	5	0	0
T48	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2722	0	0
T1	216996	5	0	0
T2	3583360	7	0	0
T3	107848	1	0	0
T4	2209188	0	0	0
T5	588968	4	0	0
T6	109808	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	0	8	0	0
T14	0	3	0	0
T15	0	29	0	0
T16	174040	4	0	0
T17	12696	1	0	0
T18	72376	1	0	0
T19	65288	0	0	0
T20	22730	5	0	0
T21	0	5	0	0
T48	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2661	0	0
T1	216996	5	0	0
T2	3583360	5	0	0
T3	107848	1	0	0
T4	2209188	0	0	0
T5	588968	4	0	0
T6	109808	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	0	8	0	0
T14	0	3	0	0
T15	0	29	0	0
T16	174040	4	0	0
T17	12696	1	0	0
T18	72376	1	0	0
T19	65288	0	0	0
T20	22730	5	0	0
T21	0	5	0	0
T48	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2615	0	0
T1	216996	5	0	0
T2	3583360	5	0	0
T3	107848	1	0	0
T4	2209188	0	0	0
T5	588968	4	0	0
T6	109808	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	0	8	0	0
T14	0	3	0	0
T15	0	29	0	0
T16	174040	4	0	0
T17	12696	1	0	0
T18	72376	1	0	0
T19	65288	0	0	0
T20	22730	5	0	0
T21	0	5	0	0
T48	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4333	0	0
T1	216996	8	0	0
T2	2687520	0	0	0
T3	107848	2	0	0
T4	2209188	0	0	0
T5	588968	0	0	0
T6	109808	0	0	0
T7	997766	0	0	0
T13	0	18	0	0
T14	0	1	0	0
T15	0	33	0	0
T16	174040	0	0	0
T17	12696	0	0	0
T18	72376	0	0	0
T19	65288	1	0	0
T20	22730	3	0	0
T21	0	54	0	0
T22	0	68	0	0
T30	0	10	0	0
T32	0	17	0	0
T48	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T77	0	4	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	537370	0	0
T1	216996	713	0	0
T2	2687520	0	0	0
T3	107848	271	0	0
T4	2209188	0	0	0
T5	588968	0	0	0
T6	109808	0	0	0
T7	997766	0	0	0
T13	0	1184	0	0
T14	0	167	0	0
T15	0	2983	0	0
T16	174040	0	0	0
T17	12696	0	0	0
T18	72376	0	0	0
T19	65288	38	0	0
T20	22730	1512	0	0
T21	0	4020	0	0
T22	0	15021	0	0
T30	0	1718	0	0
T32	0	3277	0	0
T48	0	558	0	0
T65	0	2	0	0
T66	0	49	0	0
T77	0	767	0	0
T78	0	728	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3932	0	0
T1	216996	8	0	0
T2	2687520	0	0	0
T3	80886	1	0	0
T4	1656891	0	0	0
T5	441726	0	0	0
T6	82356	0	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	16	0	0
T14	375634	1	0	0
T15	948793	32	0	0
T16	130530	0	0	0
T17	9522	0	0	0
T18	54282	0	0	0
T19	48966	1	0	0
T20	0	3	0	0
T21	114671	52	0	0
T22	0	51	0	0
T30	635233	6	0	0
T32	189492	14	0	0
T47	751918	0	0	0
T48	502666	2	0	0
T50	0	3	0	0
T66	0	2	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	1	0	0
T14	375634	0	0	0
T15	948793	0	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T21	114671	1	0	0
T22	537985	13	0	0
T30	1270466	3	0	0
T31	26025	0	0	0
T32	378984	2	0	0
T47	751918	0	0	0
T48	1005332	1	0	0
T50	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T65	16500	1	0	0
T66	74680	1	0	0
T70	0	1	0	0
T77	43568	0	0	0
T78	49209	0	0	0
T80	0	1	0	0
T81	0	4	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	1118	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5817	0	0
T10	122660	1410	0	0
T11	0	686	0	0
T12	0	1481	0	0
T36	0	1530	0	0
T37	0	710	0	0
T38	469600	0	0	0
T39	1518276	0	0	0
T40	1193412	0	0	0
T41	141264	0	0	0
T42	294120	0	0	0
T43	524232	0	0	0
T44	1676704	0	0	0
T45	972988	0	0	0
T46	68516	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4857	0	0
T10	122660	1170	0	0
T11	0	566	0	0
T12	0	1241	0	0
T36	0	1290	0	0
T37	0	590	0	0
T38	469600	0	0	0
T39	1518276	0	0	0
T40	1193412	0	0	0
T41	141264	0	0	0
T42	294120	0	0	0
T43	524232	0	0	0
T44	1676704	0	0	0
T45	972988	0	0	0
T46	68516	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	289328	289060	0	0
T2	3583360	3582988	0	0
T3	107848	107516	0	0
T4	2209188	2208916	0	0
T5	588968	588944	0	0
T6	109808	109248	0	0
T16	174040	173664	0	0
T17	12696	12368	0	0
T18	72376	72168	0	0
T19	65288	64912	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T17

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T19,T20
1	0	1	Covered	T17,T21,T15
1	1	0	Covered	T1,T21,T14
1	1	1	Covered	T3,T21,T13

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T13
0	1	Covered	T3,T32,T30
1	0	Covered	T15,T23,T84

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T21,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T23,T84

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T13
1	0	Not Covered
1	1	Covered	T3,T32,T30

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T5
1	Covered	T2,T17,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T21,T30,T22

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T5,T13,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T5
1	Covered	T3,T16,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T16,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T16
Phase1St	193	Covered	T2,T3,T16
Phase2St	210	Covered	T2,T3,T16
Phase3St	228	Covered	T2,T3,T16
TerminalSt	244	Covered	T2,T3,T16
TimeoutSt	154	Covered	T3,T21,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T2,T16,T17
IdleSt->TimeoutSt	154	Covered	T3,T21,T13
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T23,T52,T35
Phase0St->Phase1St	193	Covered	T2,T3,T16
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T84,T55,T89
Phase1St->Phase2St	210	Covered	T2,T3,T16
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T2,T33,T90
Phase2St->Phase3St	228	Covered	T2,T3,T16
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T32,T59,T62
Phase3St->TerminalSt	244	Covered	T2,T3,T16
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T20
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T21,T13,T15
TimeoutSt->Phase0St	167	Covered	T3,T15,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T13,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T91,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T84,T55,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T33,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T59,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667717896	248	0	0
CheckAccumTrig0_A	667717896	490	0	0
CheckAccumTrig1_A	667717896	34	0	0
CheckClr_A	667717896	225	0	0
CheckEn_A	667564288	336781323	0	0
CheckPhase0_A	667717896	582	0	0
CheckPhase1_A	667717896	573	0	0
CheckPhase2_A	667717896	560	0	0
CheckPhase3_A	667717896	554	0	0
CheckTimeout0_A	667717896	866	0	0
CheckTimeoutSt1_A	667717896	103934	0	0
CheckTimeoutSt2_A	667717896	762	0	0
CheckTimeoutStTrig_A	667717896	67	0	0
ErrorStAllEscAsserted_A	667717896	1483	0	0
ErrorStIsTerminal_A	667717896	1243	0	0
u_state_regs_A	667717896	667542665	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	248	0	0
T10	30665	54	0	0
T11	0	41	0	0
T12	0	53	0	0
T36	0	58	0	0
T37	0	42	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	490	0	0
T2	895840	6	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	2	0	0
T6	27452	0	0	0
T8	0	2	0	0
T13	0	1	0	0
T15	0	5	0	0
T16	43510	1	0	0
T17	3174	1	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	2	0	0
T21	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	34	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T15	948793	1	0	0
T23	0	1	0	0
T30	635233	0	0	0
T32	189492	0	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T77	43568	0	0	0
T78	49209	0	0	0
T84	0	1	0	0
T87	0	1	0	0
T88	1118	0	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	225	0	0
T2	895840	6	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T8	0	1	0	0
T15	0	3	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	1	0	0
T22	0	4	0	0
T30	0	1	0	0
T32	0	4	0	0
T47	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667564288	336781323	0	0
T1	72332	72264	0	0
T2	895840	37837	0	0
T3	26962	600	0	0
T4	552297	492580	0	0
T5	147242	5778	0	0
T6	27452	2141	0	0
T16	43510	5797	0	0
T17	3174	2087	0	0
T18	18094	18041	0	0
T19	16322	10648	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	582	0	0
T2	895840	6	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	2	0	0
T6	27452	0	0	0
T8	0	2	0	0
T13	0	1	0	0
T15	0	6	0	0
T16	43510	1	0	0
T17	3174	1	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	2	0	0
T21	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	573	0	0
T2	895840	6	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	2	0	0
T6	27452	0	0	0
T8	0	2	0	0
T13	0	1	0	0
T15	0	6	0	0
T16	43510	1	0	0
T17	3174	1	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	2	0	0
T21	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	560	0	0
T2	895840	4	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	2	0	0
T6	27452	0	0	0
T8	0	2	0	0
T13	0	1	0	0
T15	0	6	0	0
T16	43510	1	0	0
T17	3174	1	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	2	0	0
T21	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	554	0	0
T2	895840	4	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	2	0	0
T6	27452	0	0	0
T8	0	2	0	0
T13	0	1	0	0
T15	0	6	0	0
T16	43510	1	0	0
T17	3174	1	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	2	0	0
T21	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	866	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	997766	0	0	0
T13	0	10	0	0
T15	0	27	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0
T21	0	8	0	0
T22	0	10	0	0
T30	0	1	0	0
T32	0	4	0	0
T66	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	103934	0	0
T3	26962	113	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	997766	0	0	0
T13	0	674	0	0
T15	0	2161	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0
T21	0	383	0	0
T22	0	3163	0	0
T30	0	530	0	0
T32	0	1109	0	0
T66	0	49	0	0
T77	0	188	0	0
T78	0	728	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	762	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	10	0	0
T14	375634	0	0	0
T15	948793	26	0	0
T21	114671	8	0	0
T22	0	5	0	0
T30	635233	0	0	0
T32	189492	3	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T50	0	3	0	0
T66	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	67	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	997766	0	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	22730	0	0	0
T22	0	5	0	0
T30	0	1	0	0
T32	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T84	0	3	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1483	0	0
T10	30665	346	0	0
T11	0	178	0	0
T12	0	379	0	0
T36	0	402	0	0
T37	0	178	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1243	0	0
T10	30665	286	0	0
T11	0	148	0	0
T12	0	319	0	0
T36	0	342	0	0
T37	0	148	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T19
1	0	1	Covered	T21,T15,T8
1	1	0	Covered	T1,T3,T21
1	1	1	Covered	T1,T19,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T20
0	1	Covered	T48,T30,T22
1	0	Covered	T23,T50,T51

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T50,T51

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T24
1	1	Covered	T48,T30,T22

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T18
1	Covered	T2,T5,T20

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T5
1	Covered	T1,T18,T13

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T16,T15,T48

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T21,T13,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T16,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T16
Phase1St	193	Covered	T1,T2,T16
Phase2St	210	Covered	T1,T2,T16
Phase3St	228	Covered	T1,T2,T16
TerminalSt	244	Covered	T1,T2,T16
TimeoutSt	154	Covered	T1,T19,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T16
IdleSt->TimeoutSt	154	Covered	T1,T19,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T23,T91,T97
Phase0St->Phase1St	193	Covered	T1,T2,T16
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T28,T29,T82
Phase1St->Phase2St	210	Covered	T1,T2,T16
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T30,T31,T33
Phase2St->Phase3St	228	Covered	T1,T2,T16
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T33,T34,T98
Phase3St->TerminalSt	244	Covered	T1,T2,T16
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T13,T15
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T20
TimeoutSt->Phase0St	167	Covered	T48,T30,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T48,T30,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T39,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T16,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T82
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T16,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T31,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T16,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T16,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T13,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667717896	214	0	0
CheckAccumTrig0_A	667717896	886	0	0
CheckAccumTrig1_A	667717896	45	0	0
CheckClr_A	667717896	463	0	0
CheckEn_A	667564288	253922854	0	0
CheckPhase0_A	667717896	987	0	0
CheckPhase1_A	667717896	963	0	0
CheckPhase2_A	667717896	939	0	0
CheckPhase3_A	667717896	913	0	0
CheckTimeout0_A	667717896	1246	0	0
CheckTimeoutSt1_A	667717896	141487	0	0
CheckTimeoutSt2_A	667717896	1127	0	0
CheckTimeoutStTrig_A	667717896	71	0	0
ErrorStAllEscAsserted_A	667717896	1403	0	0
ErrorStIsTerminal_A	667717896	1163	0	0
u_state_regs_A	667717896	667542665	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	214	0	0
T10	30665	50	0	0
T11	0	23	0	0
T12	0	46	0	0
T36	0	60	0	0
T37	0	35	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	886	0	0
T1	72332	3	0	0
T2	895840	1	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	11	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	1	0	0
T19	16322	0	0	0
T20	0	1	0	0
T21	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	45	0	0
T23	167802	2	0	0
T28	386266	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	879979	0	0	0
T68	10596	0	0	0
T69	112414	0	0	0
T70	97814	0	0	0
T71	315934	0	0	0
T72	59962	0	0	0
T73	904328	0	0	0
T74	30851	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	463	0	0
T1	72332	2	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	1	0	0
T15	0	5	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T22	0	4	0	0
T23	0	9	0	0
T30	0	5	0	0
T31	0	3	0	0
T32	0	1	0	0
T33	0	5	0	0
T65	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667564288	253922854	0	0
T1	72332	19273	0	0
T2	895840	582	0	0
T3	26962	26878	0	0
T4	552297	552228	0	0
T5	147242	583	0	0
T6	27452	2117	0	0
T16	43510	5769	0	0
T17	3174	2051	0	0
T18	18094	3033	0	0
T19	16322	6730	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	987	0	0
T1	72332	3	0	0
T2	895840	1	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	11	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	1	0	0
T19	16322	0	0	0
T20	0	1	0	0
T21	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	963	0	0
T1	72332	3	0	0
T2	895840	1	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	11	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	1	0	0
T19	16322	0	0	0
T20	0	1	0	0
T21	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	939	0	0
T1	72332	3	0	0
T2	895840	1	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	11	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	1	0	0
T19	16322	0	0	0
T20	0	1	0	0
T21	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	913	0	0
T1	72332	3	0	0
T2	895840	1	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T13	0	4	0	0
T14	0	1	0	0
T15	0	11	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	1	0	0
T19	16322	0	0	0
T20	0	1	0	0
T21	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1246	0	0
T1	72332	2	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	2	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	1	0	0
T20	0	3	0	0
T21	0	5	0	0
T22	0	3	0	0
T30	0	4	0	0
T32	0	1	0	0
T48	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	141487	0	0
T1	72332	183	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	138	0	0
T15	0	100	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	38	0	0
T20	0	1512	0	0
T21	0	232	0	0
T22	0	354	0	0
T30	0	504	0	0
T32	0	81	0	0
T48	0	373	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1127	0	0
T1	72332	2	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	2	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	1	0	0
T20	0	3	0	0
T21	0	5	0	0
T22	0	1	0	0
T30	0	3	0	0
T32	0	1	0	0
T48	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	71	0	0
T22	537985	2	0	0
T30	635233	1	0	0
T31	26025	0	0	0
T32	189492	0	0	0
T48	502666	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T65	16500	0	0	0
T66	74680	1	0	0
T70	0	1	0	0
T77	43568	0	0	0
T78	49209	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T88	1118	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1403	0	0
T10	30665	333	0	0
T11	0	149	0	0
T12	0	351	0	0
T36	0	394	0	0
T37	0	176	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1163	0	0
T10	30665	273	0	0
T11	0	119	0	0
T12	0	291	0	0
T36	0	334	0	0
T37	0	146	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T16

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T19
1	0	1	Covered	T16,T4,T5
1	1	0	Covered	T3,T20,T21
1	1	1	Covered	T1,T3,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T21
0	1	Covered	T21,T13,T32
1	0	Covered	T22,T49,T27

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T49,T27

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T26
1	1	Covered	T21,T13,T32

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T16,T7,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T7,T13
1	Covered	T1,T5,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T5
1	Covered	T13,T32,T30

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T5
1	Covered	T15,T32,T78

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T13,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T7,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T5,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T16,T5
Phase1St	193	Covered	T1,T16,T5
Phase2St	210	Covered	T1,T16,T5
Phase3St	228	Covered	T1,T16,T5
TerminalSt	244	Covered	T1,T16,T5
TimeoutSt	154	Covered	T1,T3,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T16,T5
IdleSt->TimeoutSt	154	Covered	T1,T3,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T27,T57
Phase0St->Phase1St	193	Covered	T1,T16,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T22,T86,T99
Phase1St->Phase2St	210	Covered	T1,T16,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T23,T76,T100
Phase2St->Phase3St	228	Covered	T1,T16,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T35,T57,T101
Phase3St->TerminalSt	244	Covered	T1,T16,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T21,T13,T15
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T3,T21
TimeoutSt->Phase0St	167	Covered	T21,T13,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T13,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T27,T44
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T16,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T16,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T86,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T16,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T16,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T76,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T16,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T16,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T57,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T16,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T16,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T32,T30,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667717896	246	0	0
CheckAccumTrig0_A	667717896	508	0	0
CheckAccumTrig1_A	667717896	30	0	0
CheckClr_A	667717896	249	0	0
CheckEn_A	667564288	293861305	0	0
CheckPhase0_A	667717896	590	0	0
CheckPhase1_A	667717896	576	0	0
CheckPhase2_A	667717896	561	0	0
CheckPhase3_A	667717896	554	0	0
CheckTimeout0_A	667717896	1489	0	0
CheckTimeoutSt1_A	667717896	197726	0	0
CheckTimeoutSt2_A	667717896	1396	0	0
CheckTimeoutStTrig_A	667717896	58	0	0
ErrorStAllEscAsserted_A	667717896	1496	0	0
ErrorStIsTerminal_A	667717896	1256	0	0
u_state_regs_A	667717896	667542665	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	246	0	0
T10	30665	65	0	0
T11	0	15	0	0
T12	0	53	0	0
T36	0	76	0	0
T37	0	37	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	508	0	0
T1	72332	2	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T32	0	7	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	30	0	0
T22	537985	1	0	0
T23	167802	0	0	0
T27	0	3	0	0
T31	26025	0	0	0
T33	481611	0	0	0
T44	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	3	0	0
T65	16500	0	0	0
T66	74680	0	0	0
T67	879979	0	0	0
T68	10596	0	0	0
T69	112414	0	0	0
T70	97814	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	249	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T22	0	7	0	0
T23	0	4	0	0
T30	0	2	0	0
T32	0	2	0	0
T50	0	2	0	0
T66	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T76	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667564288	293861305	0	0
T1	72332	2059	0	0
T2	895840	48631	0	0
T3	26962	23367	0	0
T4	552297	91334	0	0
T5	147242	4671	0	0
T6	27452	2124	0	0
T16	43510	5783	0	0
T17	3174	2069	0	0
T18	18094	18041	0	0
T19	16322	15248	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	590	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	576	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	561	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	554	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	1	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	4	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1489	0	0
T1	72332	5	0	0
T2	895840	0	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	3	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	11	0	0
T22	0	10	0	0
T30	0	3	0	0
T32	0	10	0	0
T48	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	197726	0	0
T1	72332	414	0	0
T2	895840	0	0	0
T3	26962	158	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	175	0	0
T15	0	712	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1826	0	0
T22	0	2925	0	0
T30	0	302	0	0
T32	0	1845	0	0
T48	0	185	0	0
T77	0	188	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1396	0	0
T1	72332	5	0	0
T2	895840	0	0	0
T3	26962	1	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	2	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	10	0	0
T22	0	3	0	0
T30	0	2	0	0
T32	0	9	0	0
T48	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	58	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	1	0	0
T14	375634	0	0	0
T15	948793	0	0	0
T21	114671	1	0	0
T22	0	6	0	0
T30	635233	1	0	0
T32	189492	1	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T50	0	2	0	0
T65	0	1	0	0
T81	0	2	0	0
T83	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1496	0	0
T10	30665	384	0	0
T11	0	169	0	0
T12	0	377	0	0
T36	0	366	0	0
T37	0	200	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1256	0	0
T10	30665	324	0	0
T11	0	139	0	0
T12	0	317	0	0
T36	0	306	0	0
T37	0	170	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T20
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T20

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T20

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T16,T4,T7
1	1	0	Covered	T3,T21,T13
1	1	1	Covered	T1,T21,T13

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T13
0	1	Covered	T21,T13,T32
1	0	Covered	T22,T65,T71

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T21,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T65,T71

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T13
1	0	Covered	T25
1	1	Covered	T21,T13,T32

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T15,T32,T30

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T20,T9,T48

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T20
1	Covered	T7,T21,T13

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T20,T7,T21
1	Covered	T1,T16,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T20,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T16,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T20,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T16,T20
Phase1St	193	Covered	T1,T16,T20
Phase2St	210	Covered	T1,T16,T20
Phase3St	228	Covered	T1,T16,T20
TerminalSt	244	Covered	T1,T16,T20
TimeoutSt	154	Covered	T1,T21,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T16,T20
IdleSt->TimeoutSt	154	Covered	T1,T21,T13
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T91,T102,T103
Phase0St->Phase1St	193	Covered	T1,T16,T20
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T30,T104,T105
Phase1St->Phase2St	210	Covered	T1,T16,T20
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T30,T71,T97
Phase2St->Phase3St	228	Covered	T1,T16,T20
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T49,T91,T62
Phase3St->TerminalSt	244	Covered	T1,T16,T20
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T20,T21,T13
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T21,T13
TimeoutSt->Phase0St	167	Covered	T21,T13,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T13,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T102,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T104,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T16,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T16,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T71,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T16,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T16,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T91,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T16,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T16,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T15,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T16,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	667717896	310	0	0
CheckAccumTrig0_A	667717896	544	0	0
CheckAccumTrig1_A	667717896	18	0	0
CheckClr_A	667717896	252	0	0
CheckEn_A	667564288	306399780	0	0
CheckPhase0_A	667717896	617	0	0
CheckPhase1_A	667717896	610	0	0
CheckPhase2_A	667717896	601	0	0
CheckPhase3_A	667717896	594	0	0
CheckTimeout0_A	667717896	732	0	0
CheckTimeoutSt1_A	667717896	94223	0	0
CheckTimeoutSt2_A	667717896	647	0	0
CheckTimeoutStTrig_A	667717896	63	0	0
ErrorStAllEscAsserted_A	667717896	1435	0	0
ErrorStIsTerminal_A	667717896	1195	0	0
u_state_regs_A	667717896	667542665	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	310	0	0
T10	30665	88	0	0
T11	0	24	0	0
T12	0	88	0	0
T36	0	63	0	0
T37	0	47	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	544	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T14	0	1	0	0
T15	0	8	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T32	0	2	0	0
T48	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	18	0	0
T22	537985	1	0	0
T23	167802	0	0	0
T31	26025	0	0	0
T33	481611	0	0	0
T57	0	1	0	0
T64	0	1	0	0
T65	16500	1	0	0
T66	74680	0	0	0
T67	879979	0	0	0
T68	10596	0	0	0
T69	112414	0	0	0
T70	97814	0	0	0
T71	0	1	0	0
T95	0	1	0	0
T102	0	1	0	0
T104	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	252	0	0
T7	997766	0	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	0	0	0
T14	375634	0	0	0
T15	948793	4	0	0
T20	22730	1	0	0
T21	114671	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667564288	306399780	0	0
T1	72332	2088	0	0
T2	895840	895746	0	0
T3	26962	26878	0	0
T4	552297	2252	0	0
T5	147242	147028	0	0
T6	27452	2149	0	0
T16	43510	5809	0	0
T17	3174	2102	0	0
T18	18094	18041	0	0
T19	16322	14205	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	617	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	8	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T48	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	610	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	8	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T48	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	601	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	8	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T48	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	594	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	8	0	0
T16	43510	1	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T48	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	732	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	30	0	0
T22	0	45	0	0
T30	0	2	0	0
T32	0	2	0	0
T65	0	1	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	94223	0	0
T1	72332	116	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	197	0	0
T14	0	167	0	0
T15	0	10	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	1579	0	0
T22	0	8579	0	0
T30	0	382	0	0
T32	0	242	0	0
T65	0	2	0	0
T77	0	391	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	647	0	0
T1	72332	1	0	0
T2	895840	0	0	0
T3	26962	0	0	0
T4	552297	0	0	0
T5	147242	0	0	0
T6	27452	0	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	43510	0	0	0
T17	3174	0	0	0
T18	18094	0	0	0
T19	16322	0	0	0
T21	0	29	0	0
T22	0	42	0	0
T30	0	1	0	0
T32	0	1	0	0
T66	0	1	0	0
T77	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	63	0	0
T8	215878	0	0	0
T9	120968	0	0	0
T13	929117	1	0	0
T14	375634	0	0	0
T15	948793	0	0	0
T21	114671	1	0	0
T22	0	2	0	0
T30	635233	1	0	0
T32	189492	1	0	0
T47	751918	0	0	0
T48	502666	0	0	0
T50	0	1	0	0
T71	0	2	0	0
T80	0	1	0	0
T109	0	1	0	0
T110	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1435	0	0
T10	30665	347	0	0
T11	0	190	0	0
T12	0	374	0	0
T36	0	368	0	0
T37	0	156	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	1195	0	0
T10	30665	287	0	0
T11	0	160	0	0
T12	0	314	0	0
T36	0	308	0	0
T37	0	126	0	0
T38	117400	0	0	0
T39	379569	0	0	0
T40	298353	0	0	0
T41	35316	0	0	0
T42	73530	0	0	0
T43	131058	0	0	0
T44	419176	0	0	0
T45	243247	0	0	0
T46	17129	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667717896	667542665	0	0
T1	72332	72265	0	0
T2	895840	895747	0	0
T3	26962	26879	0	0
T4	552297	552229	0	0
T5	147242	147236	0	0
T6	27452	27312	0	0
T16	43510	43416	0	0
T17	3174	3092	0	0
T18	18094	18042	0	0
T19	16322	16228	0	0