Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64293665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31101727

1

T1

628

T2

4114

T3

1248

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14294193	1			T1	473		T2	1887		T3	458
values[0x0]	39598434	1			T1	643		T2	5417		T3	1708
values[0x1]	41502765	1			T1	633		T2	5285		T3	1700

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54980907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40414485

1

T1

791

T2

5155

T3

1572

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	296724	1			T1	6		T2	55		T3	18
valid_sources[0x01]	329433	1			T1	9		T2	59		T3	17
valid_sources[0x02]	302657	1			T1	7		T2	31		T3	21
valid_sources[0x03]	300858	1			T1	5		T2	53		T3	29
valid_sources[0x04]	899147	1			T1	9		T2	48		T3	15
valid_sources[0x05]	302422	1			T1	9		T2	42		T3	22
valid_sources[0x06]	298655	1			T1	7		T2	49		T3	21
valid_sources[0x07]	674930	1			T1	3		T2	43		T3	24
valid_sources[0x08]	304729	1			T1	3		T2	50		T3	18
valid_sources[0x09]	1019033	1			T1	10		T2	43		T3	13
valid_sources[0x0a]	313787	1			T1	8		T2	47		T3	11
valid_sources[0x0b]	296859	1			T1	5		T2	42		T3	10
valid_sources[0x0c]	310478	1			T1	7		T2	55		T3	13
valid_sources[0x0d]	299871	1			T1	5		T2	53		T3	17
valid_sources[0x0e]	299598	1			T1	6		T2	45		T3	3
valid_sources[0x0f]	295050	1			T1	6		T2	40		T3	9
valid_sources[0x10]	299850	1			T1	6		T2	64		T3	19
valid_sources[0x11]	615482	1			T1	3		T2	40		T3	10
valid_sources[0x12]	511547	1			T1	7		T2	47		T3	16
valid_sources[0x13]	304187	1			T1	11		T2	39		T3	16
valid_sources[0x14]	303632	1			T1	2		T2	49		T3	15
valid_sources[0x15]	302118	1			T1	12		T2	43		T3	16
valid_sources[0x16]	295544	1			T1	10		T2	46		T3	17
valid_sources[0x17]	302382	1			T1	5		T2	26		T3	13
valid_sources[0x18]	337256	1			T1	4		T2	64		T3	24
valid_sources[0x19]	299706	1			T1	11		T2	66		T3	12
valid_sources[0x1a]	298347	1			T1	9		T2	59		T3	15
valid_sources[0x1b]	638047	1			T1	9		T2	45		T3	11
valid_sources[0x1c]	314660	1			T1	13		T2	31		T3	12
valid_sources[0x1d]	294656	1			T1	8		T2	47		T3	14
valid_sources[0x1e]	303480	1			T1	5		T2	42		T3	16
valid_sources[0x1f]	305673	1			T1	8		T2	61		T3	12
valid_sources[0x20]	500261	1			T1	8		T2	27		T3	23
valid_sources[0x21]	299064	1			T1	5		T2	42		T3	16
valid_sources[0x22]	297811	1			T1	7		T2	42		T3	19
valid_sources[0x23]	299551	1			T1	14		T2	37		T3	8
valid_sources[0x24]	313956	1			T1	10		T2	50		T3	15
valid_sources[0x25]	304385	1			T1	7		T2	45		T3	14
valid_sources[0x26]	299751	1			T1	5		T2	53		T3	14
valid_sources[0x27]	310006	1			T1	9		T2	44		T3	15
valid_sources[0x28]	297396	1			T1	8		T2	54		T3	9
valid_sources[0x29]	308701	1			T1	11		T2	52		T3	13
valid_sources[0x2a]	733417	1			T1	5		T2	49		T3	13
valid_sources[0x2b]	298931	1			T1	4		T2	68		T3	11
valid_sources[0x2c]	298024	1			T1	8		T2	62		T3	17
valid_sources[0x2d]	305644	1			T1	7		T2	45		T3	14
valid_sources[0x2e]	295272	1			T1	9		T2	51		T3	9
valid_sources[0x2f]	302520	1			T1	5		T2	73		T3	17
valid_sources[0x30]	301199	1			T1	11		T2	63		T3	11
valid_sources[0x31]	302017	1			T1	5		T2	67		T3	16
valid_sources[0x32]	297309	1			T1	8		T2	38		T3	15
valid_sources[0x33]	302534	1			T1	9		T2	48		T3	19
valid_sources[0x34]	305955	1			T1	9		T2	48		T3	9
valid_sources[0x35]	850413	1			T1	9		T2	39		T3	18
valid_sources[0x36]	337763	1			T1	1		T2	58		T3	16
valid_sources[0x37]	700064	1			T1	7		T2	47		T3	15
valid_sources[0x38]	303475	1			T1	3		T2	62		T3	15
valid_sources[0x39]	300207	1			T1	4		T2	48		T3	10
valid_sources[0x3a]	656343	1			T1	7		T2	37		T3	20
valid_sources[0x3b]	317191	1			T1	8		T2	58		T3	12
valid_sources[0x3c]	301268	1			T1	10		T2	54		T3	20
valid_sources[0x3d]	306731	1			T1	7		T2	59		T3	25
valid_sources[0x3e]	302866	1			T1	8		T2	55		T3	11
valid_sources[0x3f]	292213	1			T1	9		T2	64		T3	19
valid_sources[0x40]	300407	1			T1	3		T2	60		T3	18
valid_sources[0x41]	307009	1			T1	6		T2	36		T3	18
valid_sources[0x42]	308131	1			T1	9		T2	55		T3	10
valid_sources[0x43]	307350	1			T1	7		T2	54		T3	15
valid_sources[0x44]	295330	1			T1	8		T2	44		T3	13
valid_sources[0x45]	301821	1			T1	10		T2	56		T3	32
valid_sources[0x46]	348782	1			T1	10		T2	66		T3	18
valid_sources[0x47]	310871	1			T1	3		T2	47		T3	13
valid_sources[0x48]	304388	1			T1	11		T2	49		T3	22
valid_sources[0x49]	301024	1			T1	8		T2	48		T3	14
valid_sources[0x4a]	300544	1			T1	13		T2	34		T3	11
valid_sources[0x4b]	299616	1			T1	8		T2	70		T3	9
valid_sources[0x4c]	311344	1			T1	4		T2	39		T3	17
valid_sources[0x4d]	305542	1			T1	1		T2	71		T3	22
valid_sources[0x4e]	294610	1			T1	5		T2	43		T3	11
valid_sources[0x4f]	308978	1			T1	7		T2	69		T3	15
valid_sources[0x50]	305715	1			T1	14		T2	67		T3	19
valid_sources[0x51]	302672	1			T1	4		T2	44		T3	10
valid_sources[0x52]	780320	1			T1	4		T2	45		T3	16
valid_sources[0x53]	297325	1			T1	6		T2	37		T3	19
valid_sources[0x54]	303963	1			T1	6		T2	64		T3	17
valid_sources[0x55]	310906	1			T1	13		T2	37		T3	15
valid_sources[0x56]	304732	1			T1	8		T2	44		T3	29
valid_sources[0x57]	337422	1			T1	4		T2	63		T3	32
valid_sources[0x58]	302350	1			T1	2		T2	41		T3	15
valid_sources[0x59]	311417	1			T1	5		T2	36		T3	30
valid_sources[0x5a]	300478	1			T1	4		T2	52		T3	13
valid_sources[0x5b]	297571	1			T1	9		T2	63		T3	19
valid_sources[0x5c]	308938	1			T1	2		T2	54		T3	12
valid_sources[0x5d]	299937	1			T2	77		T3	16		T4	1196
valid_sources[0x5e]	301624	1			T1	5		T2	40		T3	16
valid_sources[0x5f]	302064	1			T1	5		T2	46		T3	17
valid_sources[0x60]	302391	1			T1	3		T2	47		T3	16
valid_sources[0x61]	308339	1			T1	6		T2	66		T3	14
valid_sources[0x62]	500640	1			T1	3		T2	37		T3	14
valid_sources[0x63]	634809	1			T1	6		T2	43		T3	12
valid_sources[0x64]	296669	1			T1	3		T2	30		T3	16
valid_sources[0x65]	620036	1			T1	5		T2	32		T3	24
valid_sources[0x66]	311701	1			T1	8		T2	45		T3	11
valid_sources[0x67]	306758	1			T1	4		T2	50		T3	21
valid_sources[0x68]	301895	1			T1	6		T2	40		T3	8
valid_sources[0x69]	298070	1			T1	7		T2	56		T3	26
valid_sources[0x6a]	302432	1			T1	9		T2	65		T3	14
valid_sources[0x6b]	302392	1			T1	10		T2	34		T3	10
valid_sources[0x6c]	297953	1			T1	4		T2	35		T3	11
valid_sources[0x6d]	346989	1			T1	2		T2	60		T3	10
valid_sources[0x6e]	304648	1			T1	10		T2	44		T3	8
valid_sources[0x6f]	307646	1			T1	14		T2	54		T3	7
valid_sources[0x70]	307094	1			T1	6		T2	33		T3	18
valid_sources[0x71]	521558	1			T1	4		T2	63		T3	12
valid_sources[0x72]	299162	1			T1	12		T2	51		T3	13
valid_sources[0x73]	305526	1			T1	6		T2	58		T3	11
valid_sources[0x74]	305854	1			T1	9		T2	51		T3	14
valid_sources[0x75]	655055	1			T1	5		T2	54		T3	14
valid_sources[0x76]	312885	1			T1	7		T2	39		T3	17
valid_sources[0x77]	600600	1			T1	9		T2	56		T3	12
valid_sources[0x78]	304407	1			T1	8		T2	43		T3	15
valid_sources[0x79]	297992	1			T1	11		T2	65		T3	18
valid_sources[0x7a]	637526	1			T1	9		T2	53		T3	18
valid_sources[0x7b]	648633	1			T1	11		T2	52		T3	13
valid_sources[0x7c]	299579	1			T1	10		T2	36		T3	13
valid_sources[0x7d]	303979	1			T1	7		T2	57		T3	20
valid_sources[0x7e]	297503	1			T1	8		T2	51		T3	23
valid_sources[0x7f]	301572	1			T1	8		T2	38		T3	17
valid_sources[0x80]	303563	1			T1	11		T2	50		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7110479

1

T1

240

T2

960

T3

227

values[0x0]

all_enables

biggest_size

15147477

1

T1

245

T2

2030

T3

639

values[0x1]

all_enables

biggest_size

8843771

1

T1

143

T2

1124

T3

382