Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T80,T100
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11474	0	0
DisabledNoTrigBkwd_A	2147483647	753166	0	0
DisabledNoTrigFwd_A	2147483647	1580670307	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11474	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T10	21673	0	0	0
T19	3848	541	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T29	292956	0	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T48	27567	0	0	0
T49	5944	0	0	0
T80	0	342	0	0
T93	374445	0	0	0
T100	1090	262	0	0
T224	269456	0	0	0
T227	0	613	0	0
T228	1367	632	0	0
T229	0	172	0	0
T230	0	539	0	0
T231	0	831	0	0
T232	0	878	0	0
T233	0	642	0	0
T234	0	506	0	0
T235	0	355	0	0
T236	0	1730	0	0
T237	0	1275	0	0
T238	0	277	0	0
T239	0	487	0	0
T240	0	257	0	0
T241	0	264	0	0
T242	0	302	0	0
T243	0	569	0	0
T244	561636	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	753166	0	0
T1	3904	3	0	0
T2	256558	13	0	0
T3	22446	0	0	0
T4	1256644	6281	0	0
T5	1839276	979	0	0
T7	0	218	0	0
T8	1657996	0	0	0
T13	0	500	0	0
T14	0	2132	0	0
T15	0	21	0	0
T16	0	1631	0	0
T17	2435028	1304	0	0
T18	252416	0	0	0
T19	15392	4	0	0
T20	72860	27	0	0
T21	816228	3424	0	0
T22	1109595	3678	0	0
T29	0	155	0	0
T48	55134	42	0	0
T49	0	1	0	0
T50	0	225	0	0
T51	0	1	0	0
T52	0	290	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1580670307	0	0
T1	15616	8302	0	0
T2	513116	1631781	0	0
T3	44892	44660	0	0
T4	1256644	14937	0	0
T5	1839276	923894	0	0
T17	2435028	2190446	0	0
T18	252416	244925	0	0
T19	15392	12792	0	0
T20	72860	49530	0	0
T21	816228	1316893	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T227
1	1	Covered	T2,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701372543	1154	0	0
DisabledNoTrigBkwd_A	701372543	194072	0	0
DisabledNoTrigFwd_A	701372543	355465809	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1154	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T19	3848	541	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T29	292956	0	0	0
T48	27567	0	0	0
T49	5944	0	0	0
T227	0	613	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	194072	0	0
T4	314161	1535	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	243	0	0
T17	608757	49	0	0
T18	63104	0	0	0
T19	3848	4	0	0
T20	18215	27	0	0
T21	204057	3421	0	0
T22	369865	3284	0	0
T29	0	141	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	355465809	0	0
T1	3904	3820	0	0
T2	128279	317915	0	0
T3	11223	11165	0	0
T4	314161	2633	0	0
T5	459819	459813	0	0
T17	608757	590721	0	0
T18	63104	59395	0	0
T19	3848	3167	0	0
T20	18215	1995	0	0
T21	204057	705496	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T228,T229,T230
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701372543	5563	0	0
DisabledNoTrigBkwd_A	701372543	177368	0	0
DisabledNoTrigFwd_A	701372543	412127459	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	5563	0	0
T10	21673	0	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T93	374445	0	0	0
T224	269456	0	0	0
T228	1367	632	0	0
T229	0	172	0	0
T230	0	539	0	0
T232	0	878	0	0
T234	0	506	0	0
T235	0	355	0	0
T236	0	1730	0	0
T239	0	487	0	0
T241	0	264	0	0
T244	561636	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	177368	0	0
T1	3904	3	0	0
T2	128279	12	0	0
T3	11223	0	0	0
T4	314161	1708	0	0
T5	459819	487	0	0
T7	0	218	0	0
T13	0	249	0	0
T14	0	1100	0	0
T17	608757	731	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	4	0	0
T50	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	412127459	0	0
T1	3904	586	0	0
T2	128279	237389	0	0
T3	11223	11165	0	0
T4	314161	2646	0	0
T5	459819	2121	0	0
T17	608757	534803	0	0
T18	63104	63012	0	0
T19	3848	3183	0	0
T20	18215	11245	0	0
T21	204057	204045	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T100,T238,T240
1	1	Covered	T1,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701372543	1667	0	0
DisabledNoTrigBkwd_A	701372543	178070	0	0
DisabledNoTrigFwd_A	701372543	398524496	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1667	0	0
T9	100217	0	0	0
T30	9432	0	0	0
T33	647124	0	0	0
T79	284915	0	0	0
T84	27307	0	0	0
T100	1090	262	0	0
T129	125415	0	0	0
T130	80262	0	0	0
T212	184957	0	0	0
T238	0	277	0	0
T240	0	257	0	0
T242	0	302	0	0
T243	0	569	0	0
T245	35872	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	178070	0	0
T4	314161	1364	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	8	0	0
T14	0	1028	0	0
T15	0	21	0	0
T16	0	1631	0	0
T17	608757	213	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	249	0	0
T29	0	6	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	290	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	398524496	0	0
T1	3904	1622	0	0
T2	128279	128271	0	0
T3	11223	11165	0	0
T4	314161	2663	0	0
T5	459819	459813	0	0
T17	608757	533655	0	0
T18	63104	59506	0	0
T19	3848	3207	0	0
T20	18215	18145	0	0
T21	204057	203836	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T80,T231,T233
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	701372543	3090	0	0
DisabledNoTrigBkwd_A	701372543	203656	0	0
DisabledNoTrigFwd_A	701372543	414552543	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	3090	0	0
T16	357210	0	0	0
T26	42031	0	0	0
T51	820181	0	0	0
T52	842396	0	0	0
T76	130205	0	0	0
T77	21805	0	0	0
T80	1094	342	0	0
T82	43499	0	0	0
T213	60111	0	0	0
T231	0	831	0	0
T233	0	642	0	0
T237	0	1275	0	0
T246	8831	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	203656	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	1674	0	0
T5	459819	492	0	0
T14	0	4	0	0
T17	608757	311	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	3	0	0
T22	369865	145	0	0
T29	0	4	0	0
T48	0	42	0	0
T50	0	222	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	414552543	0	0
T1	3904	2274	0	0
T2	128279	948206	0	0
T3	11223	11165	0	0
T4	314161	6995	0	0
T5	459819	2147	0	0
T17	608757	531267	0	0
T18	63104	63012	0	0
T19	3848	3235	0	0
T20	18215	18145	0	0
T21	204057	203516	0	0