Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Covered	T4,T23,T24
1	1	1	Covered	T1,T2,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T17
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T17,T18
1	1	1	Covered	T1,T17,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T21
0	1	Covered	T17,T15,T25
1	0	Covered	T17,T26,T27

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T26,T27

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T21
1	0	Covered	T28
1	1	Covered	T17,T15,T25

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T17,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T17,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T17,T21

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T17

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T4
Phase1St	193	Covered	T1,T2,T4
Phase2St	210	Covered	T1,T2,T4
Phase3St	228	Covered	T1,T2,T4
TerminalSt	244	Covered	T1,T2,T4
TimeoutSt	154	Covered	T1,T17,T21

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T4
IdleSt->TimeoutSt	154	Covered	T1,T17,T21
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T29,T25,T30
Phase0St->Phase1St	193	Covered	T1,T2,T4
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T26,T25,T30
Phase1St->Phase2St	210	Covered	T1,T2,T4
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T21,T31,T32
Phase2St->Phase3St	228	Covered	T1,T2,T4
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T33,T34,T35
Phase3St->TerminalSt	244	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T4,T17,T21
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T17,T21
TimeoutSt->Phase0St	167	Covered	T17,T15,T26

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T15,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T33,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T30,T35
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T17,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1158	0	0
CheckAccumTrig0_A	2147483647	2229	0	0
CheckAccumTrig1_A	2147483647	101	0	0
CheckClr_A	2147483647	982	0	0
CheckEn_A	2147483647	1203566593	0	0
CheckPhase0_A	2147483647	2505	0	0
CheckPhase1_A	2147483647	2456	0	0
CheckPhase2_A	2147483647	2395	0	0
CheckPhase3_A	2147483647	2356	0	0
CheckTimeout0_A	2147483647	4904	0	0
CheckTimeoutSt1_A	2147483647	474531	0	0
CheckTimeoutSt2_A	2147483647	4571	0	0
CheckTimeoutStTrig_A	2147483647	223	0	0
ErrorStAllEscAsserted_A	2147483647	5846	0	0
ErrorStIsTerminal_A	2147483647	4886	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158	0	0
T10	86692	157	0	0
T11	0	251	0	0
T12	0	267	0	0
T37	0	166	0	0
T38	0	317	0	0
T39	116520	0	0	0
T40	111288	0	0	0
T41	2175536	0	0	0
T42	2109668	0	0	0
T43	481164	0	0	0
T44	89332	0	0	0
T45	951136	0	0	0
T46	64788	0	0	0
T47	3705540	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2229	0	0
T1	3904	1	0	0
T2	256558	2	0	0
T3	22446	0	0	0
T4	1256644	9	0	0
T5	1839276	2	0	0
T7	0	1	0	0
T8	1657996	0	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	2435028	11	0	0
T18	252416	0	0	0
T19	15392	1	0	0
T20	72860	1	0	0
T21	816228	12	0	0
T22	1109595	9	0	0
T29	0	7	0	0
T48	55134	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	101	0	0
T6	733942	0	0	0
T7	432426	0	0	0
T8	1657996	0	0	0
T17	1217514	3	0	0
T18	126208	0	0	0
T19	7696	0	0	0
T20	36430	0	0	0
T21	408114	0	0	0
T22	739730	0	0	0
T23	0	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T32	157550	0	0	0
T35	434844	1	0	0
T48	55134	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	318708	2	0	0
T56	447917	1	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	492169	0	0	0
T70	602874	0	0	0
T71	44784	0	0	0
T72	750672	0	0	0
T73	693067	0	0	0
T74	40687	0	0	0
T75	21115	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	982	0	0
T4	942483	5	0	0
T5	1379457	0	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	3315992	0	0	0
T14	0	4	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	2435028	11	0	0
T18	252416	0	0	0
T19	15392	0	0	0
T20	72860	0	0	0
T21	816228	9	0	0
T22	1479460	0	0	0
T25	0	3	0	0
T26	0	6	0	0
T27	0	9	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	7	0	0
T32	0	2	0	0
T33	0	14	0	0
T48	110268	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1203566593	0	0
T1	15616	8301	0	0
T2	513116	816642	0	0
T3	44892	44656	0	0
T4	1256644	13388	0	0
T5	1839276	923894	0	0
T17	2435028	2179863	0	0
T18	252416	244921	0	0
T19	15392	12792	0	0
T20	72860	49528	0	0
T21	816228	1316889	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2505	0	0
T1	3904	1	0	0
T2	256558	2	0	0
T3	22446	0	0	0
T4	1256644	9	0	0
T5	1839276	2	0	0
T7	0	1	0	0
T8	1657996	0	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	2435028	17	0	0
T18	252416	0	0	0
T19	15392	1	0	0
T20	72860	1	0	0
T21	816228	11	0	0
T22	1109595	9	0	0
T29	0	5	0	0
T48	55134	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T80	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T1	3904	1	0	0
T2	256558	2	0	0
T3	22446	0	0	0
T4	1256644	9	0	0
T5	1839276	2	0	0
T7	0	1	0	0
T8	1657996	0	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	2435028	17	0	0
T18	252416	0	0	0
T19	15392	1	0	0
T20	72860	1	0	0
T21	816228	11	0	0
T22	1109595	9	0	0
T29	0	5	0	0
T48	55134	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T80	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T1	3904	1	0	0
T2	256558	2	0	0
T3	22446	0	0	0
T4	1256644	9	0	0
T5	1839276	2	0	0
T7	0	1	0	0
T8	1657996	0	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	2435028	17	0	0
T18	252416	0	0	0
T19	15392	1	0	0
T20	72860	1	0	0
T21	816228	10	0	0
T22	1109595	9	0	0
T29	0	5	0	0
T48	55134	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T80	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2356	0	0
T1	3904	1	0	0
T2	256558	2	0	0
T3	22446	0	0	0
T4	1256644	9	0	0
T5	1839276	2	0	0
T7	0	1	0	0
T8	1657996	0	0	0
T13	0	3	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	2435028	17	0	0
T18	252416	0	0	0
T19	15392	1	0	0
T20	72860	1	0	0
T21	816228	10	0	0
T22	1109595	9	0	0
T29	0	5	0	0
T48	55134	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T80	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4904	0	0
T1	3904	1	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	628322	0	0	0
T5	919638	0	0	0
T6	733942	0	0	0
T7	432426	0	0	0
T8	2486994	0	0	0
T15	0	1	0	0
T17	2435028	49	0	0
T18	252416	0	0	0
T19	15392	0	0	0
T20	72860	0	0	0
T21	816228	1	0	0
T22	1109595	7	0	0
T25	0	186	0	0
T26	0	5	0	0
T27	0	52	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T33	0	5	0	0
T48	82701	0	0	0
T78	0	1	0	0
T79	0	16	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	12	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	474531	0	0
T1	3904	72	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	628322	0	0	0
T5	919638	0	0	0
T6	733942	0	0	0
T7	432426	0	0	0
T8	2486994	0	0	0
T15	0	5	0	0
T17	2435028	5073	0	0
T18	252416	0	0	0
T19	15392	0	0	0
T20	72860	0	0	0
T21	816228	15	0	0
T22	1109595	732	0	0
T25	0	12749	0	0
T26	0	850	0	0
T27	0	8646	0	0
T29	0	23	0	0
T30	0	24	0	0
T31	0	188	0	0
T32	0	125	0	0
T33	0	129	0	0
T48	82701	0	0	0
T78	0	145	0	0
T79	0	2346	0	0
T81	0	348	0	0
T82	0	145	0	0
T83	0	79	0	0
T84	0	201	0	0
T85	0	1678	0	0
T86	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4571	0	0
T1	3904	1	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	628322	0	0	0
T5	919638	0	0	0
T6	733942	0	0	0
T7	432426	0	0	0
T8	2486994	0	0	0
T17	2435028	44	0	0
T18	252416	0	0	0
T19	15392	0	0	0
T20	72860	0	0	0
T21	816228	1	0	0
T22	1109595	7	0	0
T25	0	185	0	0
T26	0	2	0	0
T27	0	49	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T33	0	3	0	0
T48	82701	0	0	0
T78	0	1	0	0
T79	0	16	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	24	0	0
T86	0	1	0	0
T87	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	223	0	0
T6	1100913	0	0	0
T7	648639	0	0	0
T8	2486994	0	0	0
T9	100217	0	0	0
T15	0	1	0	0
T17	1826271	2	0	0
T18	189312	0	0	0
T19	11544	0	0	0
T20	54645	0	0	0
T21	612171	0	0	0
T22	1109595	0	0	0
T25	373762	1	0	0
T27	113760	1	0	0
T28	0	1	0	0
T30	9432	0	0	0
T32	157550	0	0	0
T33	0	1	0	0
T35	0	8	0	0
T45	0	1	0	0
T48	82701	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T79	284915	1	0	0
T83	109090	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	181590	0	0	0
T99	158936	0	0	0
T100	1090	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5846	0	0
T10	86692	786	0	0
T11	0	1451	0	0
T12	0	1417	0	0
T37	0	724	0	0
T38	0	1468	0	0
T39	116520	0	0	0
T40	111288	0	0	0
T41	2175536	0	0	0
T42	2109668	0	0	0
T43	481164	0	0	0
T44	89332	0	0	0
T45	951136	0	0	0
T46	64788	0	0	0
T47	3705540	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4886	0	0
T10	86692	666	0	0
T11	0	1211	0	0
T12	0	1177	0	0
T37	0	604	0	0
T38	0	1228	0	0
T39	116520	0	0	0
T40	111288	0	0	0
T41	2175536	0	0	0
T42	2109668	0	0	0
T43	481164	0	0	0
T44	89332	0	0	0
T45	951136	0	0	0
T46	64788	0	0	0
T47	3705540	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15616	15280	0	0
T2	513116	513084	0	0
T3	44892	44660	0	0
T4	1256644	1256608	0	0
T5	1839276	1839252	0	0
T17	2435028	2434836	0	0
T18	252416	252048	0	0
T19	15392	15144	0	0
T20	72860	72580	0	0
T21	816228	816180	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T4,T17,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T20
1	0	1	Covered	T2,T4,T19
1	1	0	Covered	T17,T18,T22
1	1	1	Covered	T17,T21,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Covered	T17,T79,T88
1	0	Covered	T17,T26,T53

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T21,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T26,T53

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T22
1	0	Not Covered
1	1	Covered	T17,T79,T88

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T20
1	Covered	T17,T19,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T19,T20
1	Covered	T4,T17,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T19
1	Covered	T17,T21,T22

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T19
1	Covered	T17,T20,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T19,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T4,T17,T19
Phase1St	193	Covered	T4,T17,T19
Phase2St	210	Covered	T4,T17,T19
Phase3St	228	Covered	T4,T17,T19
TerminalSt	244	Covered	T4,T17,T19
TimeoutSt	154	Covered	T17,T21,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T4,T17,T19
IdleSt->TimeoutSt	154	Covered	T17,T21,T22
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T25,T86,T54
Phase0St->Phase1St	193	Covered	T4,T17,T19
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T25,T35
Phase1St->Phase2St	210	Covered	T4,T17,T19
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T21,T31,T57
Phase2St->Phase3St	228	Covered	T4,T17,T19
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T33,T35,T101
Phase3St->TerminalSt	244	Covered	T4,T17,T19
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T17,T21
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T21,T22
TimeoutSt->Phase0St	167	Covered	T17,T26,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T17,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T26,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T86,T46,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T17,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T17,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T35,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T17,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T17,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T31,T57
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T17,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T17,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T35,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T17,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T17,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T17,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T17,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701372543	277	0	0
CheckAccumTrig0_A	701372543	730	0	0
CheckAccumTrig1_A	701372543	41	0	0
CheckClr_A	701372543	315	0	0
CheckEn_A	701180638	243081837	0	0
CheckPhase0_A	701372543	820	0	0
CheckPhase1_A	701372543	804	0	0
CheckPhase2_A	701372543	782	0	0
CheckPhase3_A	701372543	771	0	0
CheckTimeout0_A	701372543	2074	0	0
CheckTimeoutSt1_A	701372543	194288	0	0
CheckTimeoutSt2_A	701372543	1969	0	0
CheckTimeoutStTrig_A	701372543	61	0	0
ErrorStAllEscAsserted_A	701372543	1448	0	0
ErrorStIsTerminal_A	701372543	1208	0	0
u_state_regs_A	701372543	701200975	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	277	0	0
T10	21673	23	0	0
T11	0	68	0	0
T12	0	61	0	0
T37	0	49	0	0
T38	0	76	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	730	0	0
T4	314161	3	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	1	0	0
T20	18215	1	0	0
T21	204057	11	0	0
T22	369865	5	0	0
T29	0	2	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	41	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	2	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T26	0	3	0	0
T48	27567	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	315	0	0
T4	314161	2	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T16	0	2	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	9	0	0
T22	369865	0	0	0
T26	0	6	0	0
T27	0	3	0	0
T29	0	1	0	0
T31	0	4	0	0
T48	27567	0	0	0
T77	0	1	0	0
T79	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701180638	243081837	0	0
T1	3904	3819	0	0
T2	128279	317915	0	0
T3	11223	11164	0	0
T4	314161	2633	0	0
T5	459819	459813	0	0
T17	608757	590721	0	0
T18	63104	59394	0	0
T19	3848	3167	0	0
T20	18215	1995	0	0
T21	204057	705493	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	820	0	0
T4	314161	3	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T17	608757	6	0	0
T18	63104	0	0	0
T19	3848	1	0	0
T20	18215	1	0	0
T21	204057	11	0	0
T22	369865	5	0	0
T29	0	2	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	804	0	0
T4	314161	3	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T17	608757	6	0	0
T18	63104	0	0	0
T19	3848	1	0	0
T20	18215	1	0	0
T21	204057	11	0	0
T22	369865	5	0	0
T29	0	2	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	782	0	0
T4	314161	3	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T17	608757	6	0	0
T18	63104	0	0	0
T19	3848	1	0	0
T20	18215	1	0	0
T21	204057	10	0	0
T22	369865	5	0	0
T29	0	2	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	771	0	0
T4	314161	3	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T17	608757	6	0	0
T18	63104	0	0	0
T19	3848	1	0	0
T20	18215	1	0	0
T21	204057	10	0	0
T22	369865	5	0	0
T29	0	2	0	0
T48	27567	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	2074	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	12	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	1	0	0
T22	369865	3	0	0
T25	0	176	0	0
T26	0	5	0	0
T29	0	1	0	0
T31	0	1	0	0
T48	27567	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	194288	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	2224	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	15	0	0
T22	369865	313	0	0
T25	0	12077	0	0
T26	0	850	0	0
T29	0	23	0	0
T31	0	188	0	0
T48	27567	0	0	0
T78	0	145	0	0
T81	0	172	0	0
T82	0	145	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1969	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	9	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	1	0	0
T22	369865	3	0	0
T25	0	176	0	0
T26	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T48	27567	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	61	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	1	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T35	0	7	0	0
T48	27567	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T79	0	1	0	0
T88	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1448	0	0
T10	21673	178	0	0
T11	0	378	0	0
T12	0	340	0	0
T37	0	190	0	0
T38	0	362	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1208	0	0
T10	21673	148	0	0
T11	0	318	0	0
T12	0	280	0	0
T37	0	160	0	0
T38	0	302	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	701200975	0	0
T1	3904	3820	0	0
T2	128279	128271	0	0
T3	11223	11165	0	0
T4	314161	314152	0	0
T5	459819	459813	0	0
T17	608757	608709	0	0
T18	63104	63012	0	0
T19	3848	3786	0	0
T20	18215	18145	0	0
T21	204057	204045	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T20
1	0	1	Covered	T2,T5,T22
1	1	0	Covered	T17,T21,T22
1	1	1	Covered	T17,T22,T15

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T22,T15
0	1	Covered	T17,T15,T27
1	0	Covered	T35,T58,T59

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T22,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T35,T58,T59

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T22,T15
1	0	Covered	T28
1	1	Covered	T17,T15,T27

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T15,T31

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T17,T7,T50

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T29,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T17
1	Covered	T2,T4,T17

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T29

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T4
Phase1St	193	Covered	T1,T2,T4
Phase2St	210	Covered	T1,T2,T4
Phase3St	228	Covered	T1,T2,T4
TerminalSt	244	Covered	T1,T2,T4
TimeoutSt	154	Covered	T17,T22,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T2,T4
IdleSt->TimeoutSt	154	Covered	T17,T22,T15
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T33,T86,T89
Phase0St->Phase1St	193	Covered	T1,T2,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T30,T103,T104
Phase1St->Phase2St	210	Covered	T1,T2,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T32,T33,T56
Phase2St->Phase3St	228	Covered	T1,T2,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T105,T59,T92
Phase3St->TerminalSt	244	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T17,T29
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T22,T25
TimeoutSt->Phase0St	167	Covered	T17,T15,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T22,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T15,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T22,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T22,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T86,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T104,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T33,T56
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T105,T59,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T17,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701372543	284	0	0
CheckAccumTrig0_A	701372543	499	0	0
CheckAccumTrig1_A	701372543	20	0	0
CheckClr_A	701372543	218	0	0
CheckEn_A	701180638	322100996	0	0
CheckPhase0_A	701372543	560	0	0
CheckPhase1_A	701372543	551	0	0
CheckPhase2_A	701372543	534	0	0
CheckPhase3_A	701372543	523	0	0
CheckTimeout0_A	701372543	1501	0	0
CheckTimeoutSt1_A	701372543	133393	0	0
CheckTimeoutSt2_A	701372543	1422	0	0
CheckTimeoutStTrig_A	701372543	57	0	0
ErrorStAllEscAsserted_A	701372543	1492	0	0
ErrorStIsTerminal_A	701372543	1252	0	0
u_state_regs_A	701372543	701200975	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	284	0	0
T10	21673	47	0	0
T11	0	56	0	0
T12	0	86	0	0
T37	0	44	0	0
T38	0	51	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	499	0	0
T1	3904	1	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	3	0	0
T5	459819	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	20	0	0
T23	0	1	0	0
T35	434844	1	0	0
T55	318708	0	0	0
T56	447917	0	0	0
T58	0	2	0	0
T59	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	492169	0	0	0
T70	602874	0	0	0
T71	44784	0	0	0
T72	750672	0	0	0
T73	693067	0	0	0
T74	40687	0	0	0
T75	21115	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	218	0	0
T4	314161	2	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T14	0	3	0	0
T17	608757	2	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	13	0	0
T48	27567	0	0	0
T76	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701180638	322100996	0	0
T1	3904	586	0	0
T2	128279	237389	0	0
T3	11223	11164	0	0
T4	314161	2646	0	0
T5	459819	2121	0	0
T17	608757	526727	0	0
T18	63104	63011	0	0
T19	3848	3183	0	0
T20	18215	11245	0	0
T21	204057	204045	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	560	0	0
T1	3904	1	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	3	0	0
T5	459819	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	551	0	0
T1	3904	1	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	3	0	0
T5	459819	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	534	0	0
T1	3904	1	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	3	0	0
T5	459819	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	523	0	0
T1	3904	1	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	3	0	0
T5	459819	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	4	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T29	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1501	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T15	0	1	0	0
T17	608757	23	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T25	0	7	0	0
T27	0	51	0	0
T32	0	3	0	0
T33	0	3	0	0
T48	27567	0	0	0
T79	0	16	0	0
T85	0	12	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	133393	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T15	0	5	0	0
T17	608757	1495	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	215	0	0
T25	0	591	0	0
T27	0	8643	0	0
T32	0	125	0	0
T33	0	128	0	0
T48	27567	0	0	0
T79	0	2346	0	0
T85	0	1678	0	0
T86	0	126	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1422	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	22	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T25	0	7	0	0
T27	0	49	0	0
T32	0	3	0	0
T33	0	3	0	0
T48	27567	0	0	0
T79	0	16	0	0
T85	0	12	0	0
T86	0	1	0	0
T87	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	57	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T15	0	1	0	0
T17	608757	1	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T35	0	1	0	0
T45	0	1	0	0
T48	27567	0	0	0
T89	0	2	0	0
T90	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1492	0	0
T10	21673	195	0	0
T11	0	374	0	0
T12	0	388	0	0
T37	0	186	0	0
T38	0	349	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1252	0	0
T10	21673	165	0	0
T11	0	314	0	0
T12	0	328	0	0
T37	0	156	0	0
T38	0	289	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	701200975	0	0
T1	3904	3820	0	0
T2	128279	128271	0	0
T3	11223	11165	0	0
T4	314161	314152	0	0
T5	459819	459813	0	0
T17	608757	608709	0	0
T18	63104	63012	0	0
T19	3848	3786	0	0
T20	18215	18145	0	0
T21	204057	204045	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T17

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T4,T17,T22

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T18
1	0	1	Covered	T4,T21,T22
1	1	0	Covered	T17,T21,T22
1	1	1	Covered	T1,T17,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T22
0	1	Covered	T25,T33,T88
1	0	Covered	T17,T27,T33

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T27,T33

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Not Covered
1	1	Covered	T25,T33,T88

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T22
1	Covered	T17,T29,T51

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T22,T29
1	Covered	T4,T17,T52

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T29
1	Covered	T17,T22,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T22
1	Covered	T17,T29,T13

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T22,T29

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T22,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T4,T17,T22
Phase1St	193	Covered	T4,T17,T22
Phase2St	210	Covered	T4,T17,T22
Phase3St	228	Covered	T4,T17,T22
TerminalSt	244	Covered	T4,T17,T22
TimeoutSt	154	Covered	T1,T17,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T4,T17,T22
IdleSt->TimeoutSt	154	Covered	T1,T17,T22
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T29,T30,T36
Phase0St->Phase1St	193	Covered	T4,T17,T22
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T107,T104,T108
Phase1St->Phase2St	210	Covered	T4,T17,T22
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T32,T105,T109
Phase2St->Phase3St	228	Covered	T4,T17,T22
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T34,T56,T108
Phase3St->TerminalSt	244	Covered	T4,T17,T22
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T17,T22,T29
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T17,T22
TimeoutSt->Phase0St	167	Covered	T17,T25,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T17,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T36,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T17,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T17,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T107,T104,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T17,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T17,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T105,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T17,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T17,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T56,T108
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T17,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T17,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T29,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T17,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701372543	296	0	0
CheckAccumTrig0_A	701372543	465	0	0
CheckAccumTrig1_A	701372543	17	0	0
CheckClr_A	701372543	187	0	0
CheckEn_A	701180638	327687150	0	0
CheckPhase0_A	701372543	523	0	0
CheckPhase1_A	701372543	517	0	0
CheckPhase2_A	701372543	507	0	0
CheckPhase3_A	701372543	499	0	0
CheckTimeout0_A	701372543	812	0	0
CheckTimeoutSt1_A	701372543	87326	0	0
CheckTimeoutSt2_A	701372543	744	0	0
CheckTimeoutStTrig_A	701372543	50	0	0
ErrorStAllEscAsserted_A	701372543	1464	0	0
ErrorStIsTerminal_A	701372543	1224	0	0
u_state_regs_A	701372543	701200975	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	296	0	0
T10	21673	38	0	0
T11	0	56	0	0
T12	0	47	0	0
T37	0	42	0	0
T38	0	113	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	465	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T29	0	3	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	17	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	1	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T27	0	1	0	0
T33	0	1	0	0
T48	27567	0	0	0
T95	0	1	0	0
T104	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	3	0	0
T114	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	187	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	27567	0	0	0
T51	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701180638	327687150	0	0
T1	3904	1622	0	0
T2	128279	128270	0	0
T3	11223	11164	0	0
T4	314161	2663	0	0
T5	459819	459813	0	0
T17	608757	533001	0	0
T18	63104	59505	0	0
T19	3848	3207	0	0
T20	18215	18144	0	0
T21	204057	203836	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	523	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T29	0	2	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	517	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T29	0	2	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	507	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T29	0	2	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	499	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	608757	4	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T29	0	2	0	0
T48	27567	0	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	812	0	0
T1	3904	1	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	314161	0	0	0
T5	459819	0	0	0
T17	608757	14	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	0	2	0	0
T25	0	3	0	0
T27	0	1	0	0
T30	0	1	0	0
T33	0	2	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	87326	0	0
T1	3904	72	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	314161	0	0	0
T5	459819	0	0	0
T17	608757	1354	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	0	204	0	0
T25	0	81	0	0
T27	0	3	0	0
T30	0	24	0	0
T33	0	1	0	0
T81	0	176	0	0
T83	0	79	0	0
T84	0	201	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	744	0	0
T1	3904	1	0	0
T2	128279	0	0	0
T3	11223	0	0	0
T4	314161	0	0	0
T5	459819	0	0	0
T17	608757	13	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	0	2	0	0
T25	0	2	0	0
T30	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	12	0	0
T115	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	50	0	0
T9	100217	0	0	0
T25	373762	1	0	0
T27	113760	0	0	0
T30	9432	0	0	0
T32	157550	0	0	0
T33	0	1	0	0
T63	0	1	0	0
T79	284915	0	0	0
T83	109090	0	0	0
T88	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T98	181590	0	0	0
T99	158936	0	0	0
T100	1090	0	0	0
T109	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1464	0	0
T10	21673	207	0	0
T11	0	360	0	0
T12	0	343	0	0
T37	0	168	0	0
T38	0	386	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1224	0	0
T10	21673	177	0	0
T11	0	300	0	0
T12	0	283	0	0
T37	0	138	0	0
T38	0	326	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	701200975	0	0
T1	3904	3820	0	0
T2	128279	128271	0	0
T3	11223	11165	0	0
T4	314161	314152	0	0
T5	459819	459813	0	0
T17	608757	608709	0	0
T18	63104	63012	0	0
T19	3848	3786	0	0
T20	18215	18145	0	0
T21	204057	204045	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T4
1	1	1	Covered	T2,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T17
1	0	1	Covered	T1,T22,T48
1	1	0	Covered	T1,T17,T21
1	1	1	Covered	T4,T17,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T22
0	1	Covered	T17,T25,T119
1	0	Covered	T32,T55,T92

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T17,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T32,T55,T92

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T22
1	0	Not Covered
1	1	Covered	T17,T25,T119

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T17
1	Covered	T2,T4,T17

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T4,T22,T51

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T5,T17,T50

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T22,T15,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T17,T48

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T22,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T5
Phase1St	193	Covered	T2,T4,T5
Phase2St	210	Covered	T2,T4,T5
Phase3St	228	Covered	T2,T4,T5
TerminalSt	244	Covered	T2,T4,T5
TimeoutSt	154	Covered	T4,T17,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T2,T4,T5
IdleSt->TimeoutSt	154	Covered	T4,T17,T22
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T21,T29,T25
Phase0St->Phase1St	193	Covered	T2,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T86,T120,T97
Phase1St->Phase2St	210	Covered	T2,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T96,T97,T121
Phase2St->Phase3St	228	Covered	T2,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T16,T52,T119
Phase3St->TerminalSt	244	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T17,T22
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T4,T17,T22
TimeoutSt->Phase0St	167	Covered	T17,T25,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T17,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T25,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T17,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T17,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T120,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T86,T120,T65
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T97,T121
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T52,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T17,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	701372543	301	0	0
CheckAccumTrig0_A	701372543	535	0	0
CheckAccumTrig1_A	701372543	23	0	0
CheckClr_A	701372543	262	0	0
CheckEn_A	701180638	310696610	0	0
CheckPhase0_A	701372543	602	0	0
CheckPhase1_A	701372543	584	0	0
CheckPhase2_A	701372543	572	0	0
CheckPhase3_A	701372543	563	0	0
CheckTimeout0_A	701372543	517	0	0
CheckTimeoutSt1_A	701372543	59524	0	0
CheckTimeoutSt2_A	701372543	436	0	0
CheckTimeoutStTrig_A	701372543	55	0	0
ErrorStAllEscAsserted_A	701372543	1442	0	0
ErrorStIsTerminal_A	701372543	1202	0	0
u_state_regs_A	701372543	701200975	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	301	0	0
T10	21673	49	0	0
T11	0	71	0	0
T12	0	73	0	0
T37	0	31	0	0
T38	0	77	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	535	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	2	0	0
T5	459819	1	0	0
T14	0	1	0	0
T17	608757	2	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	1	0	0
T22	369865	2	0	0
T29	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	23	0	0
T9	100217	0	0	0
T30	9432	0	0	0
T32	157550	1	0	0
T33	647124	0	0	0
T55	0	1	0	0
T65	0	2	0	0
T79	284915	0	0	0
T92	0	1	0	0
T98	181590	0	0	0
T99	158936	0	0	0
T100	1090	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	125415	0	0	0
T130	80262	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	262	0	0
T4	314161	1	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T16	0	2	0	0
T17	608757	2	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T25	0	2	0	0
T27	0	1	0	0
T33	0	1	0	0
T48	27567	0	0	0
T52	0	2	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701180638	310696610	0	0
T1	3904	2274	0	0
T2	128279	133068	0	0
T3	11223	11164	0	0
T4	314161	5446	0	0
T5	459819	2147	0	0
T17	608757	529414	0	0
T18	63104	63011	0	0
T19	3848	3235	0	0
T20	18215	18144	0	0
T21	204057	203515	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	602	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	2	0	0
T5	459819	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T80	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	584	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	2	0	0
T5	459819	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T80	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	572	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	2	0	0
T5	459819	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T80	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	563	0	0
T2	128279	1	0	0
T3	11223	0	0	0
T4	314161	2	0	0
T5	459819	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	608757	3	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T80	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	517	0	0
T4	314161	2	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T17	608757	12	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	1	0	0
T25	0	5	0	0
T27	0	2	0	0
T30	0	1	0	0
T32	0	1	0	0
T48	27567	0	0	0
T78	0	1	0	0
T79	0	3	0	0
T81	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	59524	0	0
T4	314161	379	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T17	608757	2113	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	96	0	0
T25	0	892	0	0
T27	0	587	0	0
T30	0	54	0	0
T32	0	3	0	0
T48	27567	0	0	0
T78	0	144	0	0
T79	0	819	0	0
T81	0	619	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	436	0	0
T4	314161	2	0	0
T5	459819	0	0	0
T8	828998	0	0	0
T17	608757	11	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	1	0	0
T25	0	3	0	0
T27	0	2	0	0
T30	0	1	0	0
T33	0	1	0	0
T48	27567	0	0	0
T78	0	1	0	0
T79	0	3	0	0
T81	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	55	0	0
T6	366971	0	0	0
T7	216213	0	0	0
T8	828998	0	0	0
T17	608757	1	0	0
T18	63104	0	0	0
T19	3848	0	0	0
T20	18215	0	0	0
T21	204057	0	0	0
T22	369865	0	0	0
T25	0	2	0	0
T35	0	1	0	0
T48	27567	0	0	0
T92	0	1	0	0
T95	0	1	0	0
T105	0	1	0	0
T116	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T131	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1442	0	0
T10	21673	206	0	0
T11	0	339	0	0
T12	0	346	0	0
T37	0	180	0	0
T38	0	371	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	1202	0	0
T10	21673	176	0	0
T11	0	279	0	0
T12	0	286	0	0
T37	0	150	0	0
T38	0	311	0	0
T39	29130	0	0	0
T40	27822	0	0	0
T41	543884	0	0	0
T42	527417	0	0	0
T43	120291	0	0	0
T44	22333	0	0	0
T45	237784	0	0	0
T46	16197	0	0	0
T47	926385	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701372543	701200975	0	0
T1	3904	3820	0	0
T2	128279	128271	0	0
T3	11223	11165	0	0
T4	314161	314152	0	0
T5	459819	459813	0	0
T17	608757	608709	0	0
T18	63104	63012	0	0
T19	3848	3786	0	0
T20	18215	18145	0	0
T21	204057	204045	0	0