Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T191,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12483	0	0
DisabledNoTrigBkwd_A	2147483647	710134	0	0
DisabledNoTrigFwd_A	2147483647	1536351691	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12483	0	0
T24	158955	0	0	0
T25	284041	0	0	0
T31	101244	0	0	0
T33	57349	0	0	0
T41	1300	580	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0
T47	68801	0	0	0
T72	85285	0	0	0
T180	0	216	0	0
T191	2778	482	0	0
T192	47152	0	0	0
T193	20077	0	0	0
T194	589792	0	0	0
T195	1736	741	0	0
T196	364313	0	0	0
T197	62671	0	0	0
T211	4315	885	0	0
T212	0	384	0	0
T213	0	1146	0	0
T214	0	625	0	0
T215	0	102	0	0
T216	0	849	0	0
T217	0	842	0	0
T218	0	477	0	0
T219	0	397	0	0
T220	0	739	0	0
T221	0	423	0	0
T222	0	1754	0	0
T223	0	589	0	0
T224	0	222	0	0
T225	0	512	0	0
T226	0	518	0	0
T227	71764	0	0	0
T228	302291	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	710134	0	0
T1	769048	3709	0	0
T2	82332	37	0	0
T3	226888	32	0	0
T4	3224816	2856	0	0
T5	3886360	12232	0	0
T6	110484	9	0	0
T7	1782500	809	0	0
T8	2102808	8083	0	0
T9	1790404	1	0	0
T17	0	695	0	0
T18	0	1661	0	0
T19	0	1448	0	0
T20	0	991	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	111	0	0
T27	0	144	0	0
T44	0	6	0	0
T45	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1536351691	0	0
T1	769048	890257	0	0
T2	82332	64800	0	0
T3	226888	165969	0	0
T4	3224816	2419083	0	0
T5	3886360	988264	0	0
T6	110484	83166	0	0
T7	1782500	1336041	0	0
T8	2102808	535513	0	0
T9	1790404	1095144	0	0
T21	107552	88442	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T218
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	702342450	1057	0	0
DisabledNoTrigBkwd_A	702342450	206659	0	0
DisabledNoTrigFwd_A	702342450	380504481	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1057	0	0
T24	158955	0	0	0
T25	284041	0	0	0
T33	57349	0	0	0
T41	1300	580	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0
T72	85285	0	0	0
T218	0	477	0	0
T227	71764	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	206659	0	0
T1	192262	3188	0	0
T2	20583	37	0	0
T3	56722	28	0	0
T4	806204	0	0	0
T5	971590	3	0	0
T6	27621	9	0	0
T7	445625	0	0	0
T8	525702	1835	0	0
T9	447601	0	0	0
T17	0	352	0	0
T18	0	6	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	380504481	0	0
T1	192262	365008	0	0
T2	20583	9229	0	0
T3	56722	9968	0	0
T4	806204	806153	0	0
T5	971590	968909	0	0
T6	27621	582	0	0
T7	445625	445530	0	0
T8	525702	3632	0	0
T9	447601	244545	0	0
T21	26888	26811	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T191,T195,T214
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	702342450	3502	0	0
DisabledNoTrigBkwd_A	702342450	179342	0	0
DisabledNoTrigFwd_A	702342450	360968169	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	3502	0	0
T31	101244	0	0	0
T47	68801	0	0	0
T191	2778	482	0	0
T192	47152	0	0	0
T193	20077	0	0	0
T194	589792	0	0	0
T195	1736	741	0	0
T196	364313	0	0	0
T197	62671	0	0	0
T214	0	625	0	0
T219	0	397	0	0
T220	0	739	0	0
T226	0	518	0	0
T228	302291	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	179342	0	0
T1	192262	269	0	0
T2	20583	0	0	0
T3	56722	2	0	0
T4	806204	0	0	0
T5	971590	9545	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	3	0	0
T9	447601	0	0	0
T17	0	342	0	0
T19	0	712	0	0
T20	0	272	0	0
T21	26888	0	0	0
T24	0	111	0	0
T27	0	42	0	0
T44	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	360968169	0	0
T1	192262	169670	0	0
T2	20583	19061	0	0
T3	56722	49671	0	0
T4	806204	806153	0	0
T5	971590	10115	0	0
T6	27621	27528	0	0
T7	445625	445530	0	0
T8	525702	524545	0	0
T9	447601	300585	0	0
T21	26888	8009	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T211,T213,T215
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	702342450	5426	0	0
DisabledNoTrigBkwd_A	702342450	165648	0	0
DisabledNoTrigFwd_A	702342450	400071777	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	5426	0	0
T32	209633	0	0	0
T71	21725	0	0	0
T81	64901	0	0	0
T180	0	216	0	0
T211	4315	885	0	0
T213	0	1146	0	0
T215	0	102	0	0
T222	0	1754	0	0
T223	0	589	0	0
T224	0	222	0	0
T225	0	512	0	0
T229	28144	0	0	0
T230	26065	0	0	0
T231	279450	0	0	0
T232	91179	0	0	0
T233	21458	0	0	0
T234	463927	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	165648	0	0
T1	192262	129	0	0
T2	20583	0	0	0
T3	56722	2	0	0
T4	806204	0	0	0
T5	971590	1314	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	3561	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	1655	0	0
T19	0	300	0	0
T21	26888	0	0	0
T27	0	67	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	400071777	0	0
T1	192262	180486	0	0
T2	20583	20530	0	0
T3	56722	49681	0	0
T4	806204	806153	0	0
T5	971590	5089	0	0
T6	27621	27528	0	0
T7	445625	444387	0	0
T8	525702	3658	0	0
T9	447601	320397	0	0
T21	26888	26811	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T216,T217
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	702342450	2498	0	0
DisabledNoTrigBkwd_A	702342450	158485	0	0
DisabledNoTrigFwd_A	702342450	394807264	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	2498	0	0
T16	41769	0	0	0
T212	1138	384	0	0
T216	0	849	0	0
T217	0	842	0	0
T221	0	423	0	0
T235	16176	0	0	0
T236	200703	0	0	0
T237	325121	0	0	0
T238	463135	0	0	0
T239	35420	0	0	0
T240	71548	0	0	0
T241	12503	0	0	0
T242	17719	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	158485	0	0
T1	192262	123	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	2856	0	0
T5	971590	1370	0	0
T6	27621	0	0	0
T7	445625	808	0	0
T8	525702	2684	0	0
T9	447601	0	0	0
T19	0	436	0	0
T20	0	719	0	0
T21	26888	0	0	0
T27	0	34	0	0
T44	0	1	0	0
T45	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	394807264	0	0
T1	192262	175093	0	0
T2	20583	15980	0	0
T3	56722	56649	0	0
T4	806204	624	0	0
T5	971590	4151	0	0
T6	27621	27528	0	0
T7	445625	594	0	0
T8	525702	3678	0	0
T9	447601	229617	0	0
T21	26888	26811	0	0