Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T22,T23

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T23
0	1	Covered	T1,T19,T24
1	0	Covered	T1,T25,T26

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T22,T23
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T25,T26

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T23
1	0	Not Covered
1	1	Covered	T1,T19,T24

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T27,T17

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14,T15,T16
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T22,T23

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T14,T15,T16
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T1,T22,T23
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T28,T29,T30
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T18,T19,T25
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T19,T31,T32
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T33,T34,T35
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T22,T23
TimeoutSt->Phase0St	167	Covered	T1,T19,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T19,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T17,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1306	0	0
CheckAccumTrig0_A	2147483647	2302	0	0
CheckAccumTrig1_A	2147483647	92	0	0
CheckClr_A	2147483647	1066	0	0
CheckEn_A	2147483647	1208749603	0	0
CheckPhase0_A	2147483647	2617	0	0
CheckPhase1_A	2147483647	2573	0	0
CheckPhase2_A	2147483647	2527	0	0
CheckPhase3_A	2147483647	2473	0	0
CheckTimeout0_A	2147483647	4363	0	0
CheckTimeoutSt1_A	2147483647	493725	0	0
CheckTimeoutSt2_A	2147483647	4001	0	0
CheckTimeoutStTrig_A	2147483647	265	0	0
ErrorStAllEscAsserted_A	2147483647	6781	0	0
ErrorStIsTerminal_A	2147483647	5701	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1306	0	0
T14	467128	235	0	0
T15	0	337	0	0
T16	0	299	0	0
T20	1059332	0	0	0
T36	0	292	0	0
T37	0	143	0	0
T38	99452	0	0	0
T39	1379272	0	0	0
T40	456712	0	0	0
T41	5200	0	0	0
T42	269704	0	0	0
T43	110892	0	0	0
T44	434996	0	0	0
T45	1070256	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2302	0	0
T1	769048	10	0	0
T2	82332	3	0	0
T3	226888	3	0	0
T4	3224816	4	0	0
T5	3886360	4	0	0
T6	110484	1	0	0
T7	1782500	4	0	0
T8	2102808	4	0	0
T9	1790404	1	0	0
T17	0	3	0	0
T18	0	7	0	0
T19	0	13	0	0
T20	0	2	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	92	0	0
T1	192262	1	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T10	727932	0	0	0
T11	227578	0	0	0
T21	26888	0	0	0
T25	284041	1	0	0
T26	307166	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T35	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	5	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	71484	0	0	0
T62	325438	0	0	0
T63	1141510	0	0	0
T64	68666	0	0	0
T65	1620182	0	0	0
T66	499034	0	0	0
T67	17189	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1066	0	0
T2	20583	2	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T12	0	1	0	0
T14	233564	0	0	0
T17	101809	1	0	0
T18	0	6	0	0
T19	678104	15	0	0
T20	529666	1	0	0
T21	26888	0	0	0
T22	0	1	0	0
T24	0	3	0	0
T25	0	5	0	0
T26	0	12	0	0
T27	107908	0	0	0
T33	0	3	0	0
T34	0	7	0	0
T35	0	15	0	0
T38	49726	0	0	0
T39	689636	0	0	0
T40	228356	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T61	0	2	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208749603	0	0
T1	769048	1383296	0	0
T2	82332	64797	0	0
T3	226888	72663	0	0
T4	3224816	2419080	0	0
T5	3886360	12463	0	0
T6	110484	83163	0	0
T7	1782500	892242	0	0
T8	2102808	24770	0	0
T9	1790404	787578	0	0
T21	107552	88439	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2617	0	0
T1	769048	12	0	0
T2	82332	3	0	0
T3	226888	3	0	0
T4	3224816	4	0	0
T5	3886360	4	0	0
T6	110484	1	0	0
T7	1782500	4	0	0
T8	2102808	4	0	0
T9	1790404	1	0	0
T17	0	3	0	0
T18	0	7	0	0
T19	0	18	0	0
T20	0	2	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T1	769048	12	0	0
T2	82332	3	0	0
T3	226888	3	0	0
T4	3224816	4	0	0
T5	3886360	4	0	0
T6	110484	1	0	0
T7	1782500	4	0	0
T8	2102808	4	0	0
T9	1790404	1	0	0
T17	0	3	0	0
T18	0	6	0	0
T19	0	16	0	0
T20	0	2	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2527	0	0
T1	769048	11	0	0
T2	82332	3	0	0
T3	226888	3	0	0
T4	3224816	4	0	0
T5	3886360	4	0	0
T6	110484	1	0	0
T7	1782500	4	0	0
T8	2102808	4	0	0
T9	1790404	1	0	0
T17	0	3	0	0
T18	0	6	0	0
T19	0	15	0	0
T20	0	2	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T1	769048	11	0	0
T2	82332	3	0	0
T3	226888	3	0	0
T4	3224816	4	0	0
T5	3886360	4	0	0
T6	110484	1	0	0
T7	1782500	4	0	0
T8	2102808	4	0	0
T9	1790404	1	0	0
T17	0	3	0	0
T18	0	6	0	0
T19	0	15	0	0
T20	0	2	0	0
T21	107552	0	0	0
T22	0	2	0	0
T24	0	2	0	0
T27	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4363	0	0
T1	576786	21	0	0
T2	61749	0	0	0
T3	170166	0	0	0
T4	2418612	0	0	0
T5	2914770	0	0	0
T6	82863	0	0	0
T7	1336875	0	0	0
T8	1577106	0	0	0
T9	1342803	0	0	0
T10	363966	0	0	0
T19	0	127	0	0
T21	80664	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	158955	20	0	0
T25	284041	3	0	0
T26	153583	35	0	0
T35	0	44	0	0
T40	0	7	0	0
T45	0	1	0	0
T46	0	2	0	0
T61	35742	0	0	0
T62	162719	1	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	1	0	0
T67	0	2	0	0
T72	85285	14	0	0
T73	0	2	0	0
T74	0	5	0	0
T75	0	9	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	493725	0	0
T1	576786	1335	0	0
T2	61749	0	0	0
T3	170166	0	0	0
T4	2418612	0	0	0
T5	2914770	0	0	0
T6	82863	0	0	0
T7	1336875	0	0	0
T8	1577106	0	0	0
T9	1342803	0	0	0
T10	363966	0	0	0
T19	0	16160	0	0
T21	80664	0	0	0
T22	0	224	0	0
T23	0	67	0	0
T24	158955	937	0	0
T25	284041	1443	0	0
T26	153583	5274	0	0
T35	0	4311	0	0
T40	0	1290	0	0
T45	0	89	0	0
T46	0	150	0	0
T61	35742	0	0	0
T62	162719	65	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	65	0	0
T67	0	664	0	0
T72	85285	1805	0	0
T73	0	274	0	0
T74	0	791	0	0
T75	0	2489	0	0
T76	0	14	0	0
T77	0	70	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4001	0	0
T1	192262	10	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T14	116782	0	0	0
T18	390478	0	0	0
T19	339052	102	0	0
T20	264833	0	0	0
T21	26888	0	0	0
T22	97275	1	0	0
T23	33062	1	0	0
T24	158955	11	0	0
T26	0	13	0	0
T28	0	41	0	0
T35	0	36	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	7	0	0
T41	1300	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T65	0	1	0	0
T67	0	1	0	0
T72	0	6	0	0
T73	0	3	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	265	0	0
T1	192262	1	0	0
T10	363966	0	0	0
T11	113789	0	0	0
T14	233564	0	0	0
T19	678104	6	0	0
T20	529666	0	0	0
T24	0	1	0	0
T25	284041	2	0	0
T26	153583	5	0	0
T28	0	3	0	0
T29	0	4	0	0
T38	49726	0	0	0
T39	689636	0	0	0
T40	228356	0	0	0
T41	2600	0	0	0
T42	134852	0	0	0
T43	55446	0	0	0
T44	217498	0	0	0
T47	0	2	0	0
T48	0	3	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T66	249517	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	4	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6781	0	0
T14	467128	1502	0	0
T15	0	1591	0	0
T16	0	1519	0	0
T20	1059332	0	0	0
T36	0	1437	0	0
T37	0	732	0	0
T38	99452	0	0	0
T39	1379272	0	0	0
T40	456712	0	0	0
T41	5200	0	0	0
T42	269704	0	0	0
T43	110892	0	0	0
T44	434996	0	0	0
T45	1070256	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5701	0	0
T14	467128	1262	0	0
T15	0	1351	0	0
T16	0	1279	0	0
T20	1059332	0	0	0
T36	0	1197	0	0
T37	0	612	0	0
T38	99452	0	0	0
T39	1379272	0	0	0
T40	456712	0	0	0
T41	5200	0	0	0
T42	269704	0	0	0
T43	110892	0	0	0
T44	434996	0	0	0
T45	1070256	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	769048	768792	0	0
T2	82332	82120	0	0
T3	226888	226596	0	0
T4	3224816	3224612	0	0
T5	3886360	3885992	0	0
T6	110484	110112	0	0
T7	1782500	1782120	0	0
T8	2102808	2102780	0	0
T9	1790404	1790044	0	0
T21	107552	107244	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T9
1	1	0	Covered	T1,T19,T40
1	1	1	Covered	T1,T19,T40

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T40
0	1	Covered	T19,T26,T75
1	0	Covered	T26,T35,T88

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T40
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T35,T88

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T40
1	0	Not Covered
1	1	Covered	T19,T26,T75

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T27
1	Covered	T3,T8,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T5,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T27,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T19,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T5,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14,T15,T16
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T19,T40

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14,T15,T16
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T19,T40
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T89,T90,T91
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T19,T26,T69
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T19,T92,T93
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T32,T93,T94
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T19,T24
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T40
TimeoutSt->Phase0St	167	Covered	T19,T26,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T40
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T26,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T40
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T40
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T89,T90,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T26,T69
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T93,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T26,T35
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	702342450	264	0	0
CheckAccumTrig0_A	702342450	500	0	0
CheckAccumTrig1_A	702342450	16	0	0
CheckClr_A	702342450	212	0	0
CheckEn_A	702003349	267398253	0	0
CheckPhase0_A	702342450	564	0	0
CheckPhase1_A	702342450	555	0	0
CheckPhase2_A	702342450	546	0	0
CheckPhase3_A	702342450	540	0	0
CheckTimeout0_A	702342450	878	0	0
CheckTimeoutSt1_A	702342450	94540	0	0
CheckTimeoutSt2_A	702342450	804	0	0
CheckTimeoutStTrig_A	702342450	57	0	0
ErrorStAllEscAsserted_A	702342450	1696	0	0
ErrorStIsTerminal_A	702342450	1426	0	0
u_state_regs_A	702342450	702154202	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	264	0	0
T14	116782	51	0	0
T15	0	72	0	0
T16	0	41	0	0
T20	264833	0	0	0
T36	0	63	0	0
T37	0	37	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	500	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	16	0	0
T10	363966	0	0	0
T11	113789	0	0	0
T26	153583	1	0	0
T35	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T66	249517	0	0	0
T67	17189	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	212	0	0
T14	116782	0	0	0
T19	339052	4	0	0
T20	264833	0	0	0
T26	0	6	0	0
T35	0	13	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702003349	267398253	0	0
T1	192262	289344	0	0
T2	20583	19060	0	0
T3	56722	3011	0	0
T4	806204	806152	0	0
T5	971590	6452	0	0
T6	27621	27527	0	0
T7	445625	445529	0	0
T8	525702	13802	0	0
T9	447601	300584	0	0
T21	26888	8009	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	564	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T19	0	7	0	0
T20	0	1	0	0
T21	26888	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	555	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T19	0	6	0	0
T20	0	1	0	0
T21	26888	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	546	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	540	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	878	0	0
T1	192262	10	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	82	0	0
T21	26888	0	0	0
T24	0	2	0	0
T26	0	8	0	0
T35	0	26	0	0
T40	0	7	0	0
T46	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	94540	0	0
T1	192262	628	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	10580	0	0
T21	26888	0	0	0
T24	0	90	0	0
T26	0	961	0	0
T35	0	2679	0	0
T40	0	1290	0	0
T46	0	149	0	0
T73	0	274	0	0
T75	0	588	0	0
T77	0	70	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	804	0	0
T1	192262	10	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	80	0	0
T21	26888	0	0	0
T24	0	2	0	0
T26	0	5	0	0
T28	0	37	0	0
T35	0	25	0	0
T40	0	7	0	0
T46	0	1	0	0
T73	0	2	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	57	0	0
T14	116782	0	0	0
T19	339052	2	0	0
T20	264833	0	0	0
T26	0	2	0	0
T29	0	2	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T48	0	1	0	0
T75	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1696	0	0
T14	116782	353	0	0
T15	0	420	0	0
T16	0	379	0	0
T20	264833	0	0	0
T36	0	346	0	0
T37	0	198	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1426	0	0
T14	116782	293	0	0
T15	0	360	0	0
T16	0	319	0	0
T20	264833	0	0	0
T36	0	286	0	0
T37	0	168	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	702154202	0	0
T1	192262	192198	0	0
T2	20583	20530	0	0
T3	56722	56649	0	0
T4	806204	806153	0	0
T5	971590	971498	0	0
T6	27621	27528	0	0
T7	445625	445530	0	0
T8	525702	525695	0	0
T9	447601	447511	0	0
T21	26888	26811	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T22
1	0	1	Covered	T1,T9,T27
1	1	0	Covered	T1,T19,T40
1	1	1	Covered	T24,T72,T25

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T24,T72,T25
0	1	Covered	T25,T26,T75
1	0	Covered	T25,T26,T35

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T24,T72,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T26,T35

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T72,T25
1	0	Not Covered
1	1	Covered	T25,T26,T75

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T3,T8

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T5,T9,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T7,T17,T18

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T27,T45,T25

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T5,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T9,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14,T15,T16
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T24,T72,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14,T15,T16
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T24,T72,T25
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T96,T97,T56
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T18,T19,T98
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T31,T32,T99
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T68,T28,T100
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T17,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T24,T72,T26
TimeoutSt->Phase0St	167	Covered	T25,T26,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T72,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T24,T72,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T24,T72,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T96,T97,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T19,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T32,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T68,T28,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	702342450	360	0	0
CheckAccumTrig0_A	702342450	498	0	0
CheckAccumTrig1_A	702342450	21	0	0
CheckClr_A	702342450	224	0	0
CheckEn_A	702003349	318046848	0	0
CheckPhase0_A	702342450	583	0	0
CheckPhase1_A	702342450	575	0	0
CheckPhase2_A	702342450	568	0	0
CheckPhase3_A	702342450	559	0	0
CheckTimeout0_A	702342450	949	0	0
CheckTimeoutSt1_A	702342450	101108	0	0
CheckTimeoutSt2_A	702342450	854	0	0
CheckTimeoutStTrig_A	702342450	71	0	0
ErrorStAllEscAsserted_A	702342450	1703	0	0
ErrorStIsTerminal_A	702342450	1433	0	0
u_state_regs_A	702342450	702154202	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	360	0	0
T14	116782	95	0	0
T15	0	82	0	0
T16	0	82	0	0
T20	264833	0	0	0
T36	0	53	0	0
T37	0	48	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	498	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	1	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	5	0	0
T19	0	6	0	0
T21	26888	0	0	0
T27	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	21	0	0
T10	363966	0	0	0
T11	113789	0	0	0
T25	284041	1	0	0
T26	153583	1	0	0
T35	0	1	0	0
T46	0	1	0	0
T49	0	2	0	0
T56	0	3	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T66	249517	0	0	0
T97	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	224	0	0
T12	0	1	0	0
T14	116782	0	0	0
T17	101809	1	0	0
T18	390478	4	0	0
T19	339052	2	0	0
T20	264833	1	0	0
T22	97275	0	0	0
T23	33062	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	0	5	0	0
T35	0	2	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702003349	318046848	0	0
T1	192262	394426	0	0
T2	20583	20529	0	0
T3	56722	3036	0	0
T4	806204	806152	0	0
T5	971590	590	0	0
T6	27621	27527	0	0
T7	445625	590	0	0
T8	525702	3658	0	0
T9	447601	12834	0	0
T21	26888	26810	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	583	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	1	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	5	0	0
T19	0	6	0	0
T21	26888	0	0	0
T27	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	575	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	1	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	5	0	0
T21	26888	0	0	0
T27	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	568	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	1	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	5	0	0
T21	26888	0	0	0
T27	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	559	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	1	0	0
T8	525702	1	0	0
T9	447601	1	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	5	0	0
T21	26888	0	0	0
T27	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	949	0	0
T10	363966	0	0	0
T24	158955	5	0	0
T25	284041	2	0	0
T26	153583	9	0	0
T35	0	12	0	0
T46	0	1	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T67	0	1	0	0
T72	85285	1	0	0
T74	0	3	0	0
T75	0	2	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	101108	0	0
T10	363966	0	0	0
T24	158955	221	0	0
T25	284041	798	0	0
T26	153583	1538	0	0
T35	0	1187	0	0
T46	0	1	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T67	0	332	0	0
T72	85285	145	0	0
T74	0	424	0	0
T75	0	335	0	0
T76	0	14	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	854	0	0
T10	363966	0	0	0
T24	158955	5	0	0
T25	284041	0	0	0
T26	153583	6	0	0
T28	0	4	0	0
T35	0	11	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T67	0	1	0	0
T72	85285	1	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	71	0	0
T10	363966	0	0	0
T11	113789	0	0	0
T25	284041	1	0	0
T26	153583	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T66	249517	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1703	0	0
T14	116782	393	0	0
T15	0	393	0	0
T16	0	371	0	0
T20	264833	0	0	0
T36	0	364	0	0
T37	0	182	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1433	0	0
T14	116782	333	0	0
T15	0	333	0	0
T16	0	311	0	0
T20	264833	0	0	0
T36	0	304	0	0
T37	0	152	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	702154202	0	0
T1	192262	192198	0	0
T2	20583	20530	0	0
T3	56722	56649	0	0
T4	806204	806153	0	0
T5	971590	971498	0	0
T6	27621	27528	0	0
T7	445625	445530	0	0
T8	525702	525695	0	0
T9	447601	447511	0	0
T21	26888	26811	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T19
1	0	1	Covered	T1,T27,T17
1	1	0	Covered	T1,T3,T19
1	1	1	Covered	T1,T19,T24

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T24
0	1	Covered	T1,T19,T26
1	0	Covered	T26,T75,T80

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T75,T80

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T24
1	0	Not Covered
1	1	Covered	T1,T19,T26

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T4,T5

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T8

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T19,T24

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T26,T34

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T7,T27

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T4,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T5,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14,T15,T16
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T4,T5
Phase1St	193	Covered	T1,T4,T5
Phase2St	210	Covered	T1,T4,T5
Phase3St	228	Covered	T1,T4,T5
TerminalSt	244	Covered	T1,T4,T5
TimeoutSt	154	Covered	T1,T19,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14,T15,T16
IdleSt->Phase0St	147	Covered	T1,T4,T5
IdleSt->TimeoutSt	154	Covered	T1,T19,T24
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T34,T88,T30
Phase0St->Phase1St	193	Covered	T1,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T105,T106
Phase1St->Phase2St	210	Covered	T1,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T1,T24,T34
Phase2St->Phase3St	228	Covered	T1,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T26,T34,T68
Phase3St->TerminalSt	244	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T4,T7
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T24
TimeoutSt->Phase0St	167	Covered	T1,T19,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T107,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T105,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T24,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T34,T68
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	702342450	350	0	0
CheckAccumTrig0_A	702342450	495	0	0
CheckAccumTrig1_A	702342450	16	0	0
CheckClr_A	702342450	232	0	0
CheckEn_A	702003349	320746987	0	0
CheckPhase0_A	702342450	569	0	0
CheckPhase1_A	702342450	562	0	0
CheckPhase2_A	702342450	553	0	0
CheckPhase3_A	702342450	541	0	0
CheckTimeout0_A	702342450	1622	0	0
CheckTimeoutSt1_A	702342450	193409	0	0
CheckTimeoutSt2_A	702342450	1539	0	0
CheckTimeoutStTrig_A	702342450	67	0	0
ErrorStAllEscAsserted_A	702342450	1678	0	0
ErrorStIsTerminal_A	702342450	1408	0	0
u_state_regs_A	702342450	702154202	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	350	0	0
T14	116782	29	0	0
T15	0	93	0	0
T16	0	102	0	0
T20	264833	0	0	0
T36	0	91	0	0
T37	0	35	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	495	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	4	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	3	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	26888	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	16	0	0
T10	363966	0	0	0
T11	113789	0	0	0
T26	153583	1	0	0
T51	0	1	0	0
T56	0	1	0	0
T61	35742	0	0	0
T62	162719	0	0	0
T63	570755	0	0	0
T64	34333	0	0	0
T65	810091	0	0	0
T66	249517	0	0	0
T67	17189	0	0	0
T75	0	1	0	0
T80	0	1	0	0
T88	0	1	0	0
T94	0	1	0	0
T107	0	2	0	0
T108	0	1	0	0
T109	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	232	0	0
T1	192262	2	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	3	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	2	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T21	26888	0	0	0
T24	0	2	0	0
T26	0	8	0	0
T28	0	5	0	0
T34	0	6	0	0
T68	0	3	0	0
T79	0	1	0	0
T105	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702003349	320746987	0	0
T1	192262	344589	0	0
T2	20583	15979	0	0
T3	56722	56648	0	0
T4	806204	624	0	0
T5	971590	594	0	0
T6	27621	27527	0	0
T7	445625	594	0	0
T8	525702	3678	0	0
T9	447601	229616	0	0
T21	26888	26810	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	569	0	0
T1	192262	4	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	4	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	3	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	562	0	0
T1	192262	4	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	4	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	3	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	553	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	4	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	3	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	541	0	0
T1	192262	3	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	4	0	0
T5	971590	1	0	0
T6	27621	0	0	0
T7	445625	3	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T19	0	5	0	0
T20	0	1	0	0
T21	26888	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1622	0	0
T1	192262	10	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	22	0	0
T21	26888	0	0	0
T24	0	8	0	0
T26	0	16	0	0
T35	0	6	0	0
T62	0	1	0	0
T67	0	1	0	0
T72	0	8	0	0
T74	0	2	0	0
T75	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	193409	0	0
T1	192262	703	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	2932	0	0
T21	26888	0	0	0
T24	0	403	0	0
T26	0	2633	0	0
T35	0	445	0	0
T62	0	65	0	0
T67	0	332	0	0
T72	0	1024	0	0
T74	0	367	0	0
T75	0	1566	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1539	0	0
T1	192262	9	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	19	0	0
T21	26888	0	0	0
T24	0	8	0	0
T26	0	14	0	0
T35	0	6	0	0
T62	0	1	0	0
T67	0	1	0	0
T72	0	8	0	0
T74	0	2	0	0
T75	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	67	0	0
T1	192262	1	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	3	0	0
T21	26888	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0
T85	0	1	0	0
T110	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1678	0	0
T14	116782	346	0	0
T15	0	376	0	0
T16	0	417	0	0
T20	264833	0	0	0
T36	0	369	0	0
T37	0	170	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1408	0	0
T14	116782	286	0	0
T15	0	316	0	0
T16	0	357	0	0
T20	264833	0	0	0
T36	0	309	0	0
T37	0	140	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	702154202	0	0
T1	192262	192198	0	0
T2	20583	20530	0	0
T3	56722	56649	0	0
T4	806204	806153	0	0
T5	971590	971498	0	0
T6	27621	27528	0	0
T7	445625	445530	0	0
T8	525702	525695	0	0
T9	447601	447511	0	0
T21	26888	26811	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T9,T27
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T22,T23

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T23
0	1	Covered	T19,T24,T25
1	0	Covered	T1,T46,T28

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T22,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T46,T28

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T23
1	0	Not Covered
1	1	Covered	T19,T24,T25

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T3,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T17,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T14,T15,T16
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T22,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T14,T15,T16
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T1,T22,T23
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T28,T29,T30
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T25,T34,T73
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T19,T29,T111
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T33,T34,T35
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T2,T22
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T22,T23,T19
TimeoutSt->Phase0St	167	Covered	T1,T19,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T23,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T34,T73
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T111,T113
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T34,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T22,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	702342450	332	0	0
CheckAccumTrig0_A	702342450	809	0	0
CheckAccumTrig1_A	702342450	39	0	0
CheckClr_A	702342450	398	0	0
CheckEn_A	702003349	302557515	0	0
CheckPhase0_A	702342450	901	0	0
CheckPhase1_A	702342450	881	0	0
CheckPhase2_A	702342450	860	0	0
CheckPhase3_A	702342450	833	0	0
CheckTimeout0_A	702342450	914	0	0
CheckTimeoutSt1_A	702342450	104668	0	0
CheckTimeoutSt2_A	702342450	804	0	0
CheckTimeoutStTrig_A	702342450	70	0	0
ErrorStAllEscAsserted_A	702342450	1704	0	0
ErrorStIsTerminal_A	702342450	1434	0	0
u_state_regs_A	702342450	702154202	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	332	0	0
T14	116782	60	0	0
T15	0	90	0	0
T16	0	74	0	0
T20	264833	0	0	0
T36	0	85	0	0
T37	0	23	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	809	0	0
T1	192262	2	0	0
T2	20583	3	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	1	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	39	0	0
T1	192262	1	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T21	26888	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	398	0	0
T2	20583	2	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T18	0	2	0	0
T19	0	9	0	0
T21	26888	0	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	0	3	0	0
T26	0	1	0	0
T27	107908	0	0	0
T33	0	3	0	0
T34	0	7	0	0
T61	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702003349	302557515	0	0
T1	192262	354937	0	0
T2	20583	9229	0	0
T3	56722	9968	0	0
T4	806204	806152	0	0
T5	971590	4827	0	0
T6	27621	582	0	0
T7	445625	445529	0	0
T8	525702	3632	0	0
T9	447601	244544	0	0
T21	26888	26810	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	901	0	0
T1	192262	3	0	0
T2	20583	3	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	1	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	881	0	0
T1	192262	3	0	0
T2	20583	3	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	1	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	860	0	0
T1	192262	3	0	0
T2	20583	3	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	1	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	833	0	0
T1	192262	3	0	0
T2	20583	3	0	0
T3	56722	1	0	0
T4	806204	0	0	0
T5	971590	1	0	0
T6	27621	1	0	0
T7	445625	0	0	0
T8	525702	1	0	0
T9	447601	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T21	26888	0	0	0
T22	0	2	0	0
T27	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	914	0	0
T1	192262	1	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	23	0	0
T21	26888	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	5	0	0
T25	0	1	0	0
T26	0	2	0	0
T45	0	1	0	0
T65	0	1	0	0
T72	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	104668	0	0
T1	192262	4	0	0
T2	20583	0	0	0
T3	56722	0	0	0
T4	806204	0	0	0
T5	971590	0	0	0
T6	27621	0	0	0
T7	445625	0	0	0
T8	525702	0	0	0
T9	447601	0	0	0
T19	0	2648	0	0
T21	26888	0	0	0
T22	0	224	0	0
T23	0	67	0	0
T24	0	223	0	0
T25	0	645	0	0
T26	0	142	0	0
T45	0	89	0	0
T65	0	65	0	0
T72	0	636	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	804	0	0
T14	116782	0	0	0
T18	390478	0	0	0
T19	339052	22	0	0
T20	264833	0	0	0
T22	97275	1	0	0
T23	33062	1	0	0
T24	0	4	0	0
T26	0	2	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T72	0	5	0	0
T73	0	1	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	70	0	0
T14	116782	0	0	0
T19	339052	1	0	0
T20	264833	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1704	0	0
T14	116782	410	0	0
T15	0	402	0	0
T16	0	352	0	0
T20	264833	0	0	0
T36	0	358	0	0
T37	0	182	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	1434	0	0
T14	116782	350	0	0
T15	0	342	0	0
T16	0	292	0	0
T20	264833	0	0	0
T36	0	298	0	0
T37	0	152	0	0
T38	24863	0	0	0
T39	344818	0	0	0
T40	114178	0	0	0
T41	1300	0	0	0
T42	67426	0	0	0
T43	27723	0	0	0
T44	108749	0	0	0
T45	267564	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	702342450	702154202	0	0
T1	192262	192198	0	0
T2	20583	20530	0	0
T3	56722	56649	0	0
T4	806204	806153	0	0
T5	971590	971498	0	0
T6	27621	27528	0	0
T7	445625	445530	0	0
T8	525702	525695	0	0
T9	447601	447511	0	0
T21	26888	26811	0	0