Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 63498148 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30808591 1 T1 830 T2 117518 T3 97445



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 14216733 1 T1 367 T2 45923 T3 38214
values[0x0] 38991821 1 T1 1103 T2 163732 T3 135104
values[0x1] 41098185 1 T1 1051 T2 163350 T3 134664



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 54148304 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 40158435 1 T1 1017 T2 148595 T3 122863



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 300384 1 T1 12 T3 1202 T16 21
valid_sources[0x01] 294378 1 T1 11 T3 1213 T16 25
valid_sources[0x02] 692035 1 T1 8 T3 1118 T16 28
valid_sources[0x03] 291842 1 T1 6 T3 1177 T16 24
valid_sources[0x04] 441146 1 T1 11 T3 1209 T16 21
valid_sources[0x05] 293348 1 T1 8 T3 1150 T16 29
valid_sources[0x06] 302672 1 T1 12 T3 1262 T16 26
valid_sources[0x07] 298692 1 T1 7 T3 1200 T16 34
valid_sources[0x08] 310518 1 T1 14 T3 1232 T16 24
valid_sources[0x09] 324413 1 T1 11 T3 1171 T16 19
valid_sources[0x0a] 314799 1 T1 9 T3 1203 T16 19
valid_sources[0x0b] 288075 1 T1 9 T3 1190 T16 21
valid_sources[0x0c] 303041 1 T1 6 T3 1195 T16 25
valid_sources[0x0d] 1024470 1 T1 10 T3 1144 T16 38
valid_sources[0x0e] 314348 1 T1 12 T3 1194 T16 25
valid_sources[0x0f] 316019 1 T1 7 T3 1197 T16 21
valid_sources[0x10] 300002 1 T1 14 T3 1175 T16 19
valid_sources[0x11] 297588 1 T1 5 T3 1184 T16 22
valid_sources[0x12] 313125 1 T1 10 T3 1224 T16 20
valid_sources[0x13] 305832 1 T1 5 T3 1225 T16 24
valid_sources[0x14] 298788 1 T1 7 T3 1257 T16 28
valid_sources[0x15] 306460 1 T1 6 T3 1200 T16 23
valid_sources[0x16] 295634 1 T1 10 T3 1164 T16 26
valid_sources[0x17] 297866 1 T1 5 T3 1181 T16 21
valid_sources[0x18] 1116008 1 T1 5 T3 1195 T16 22
valid_sources[0x19] 600647 1 T1 15 T3 1286 T16 20
valid_sources[0x1a] 305329 1 T1 17 T3 1218 T16 25
valid_sources[0x1b] 302330 1 T1 4 T3 1210 T16 21
valid_sources[0x1c] 355788 1 T1 7 T3 1178 T16 31
valid_sources[0x1d] 295333 1 T1 18 T3 1239 T16 23
valid_sources[0x1e] 301527 1 T1 20 T3 1189 T16 13
valid_sources[0x1f] 303220 1 T1 2 T3 1217 T16 24
valid_sources[0x20] 300917 1 T1 20 T3 1187 T16 26
valid_sources[0x21] 306158 1 T1 10 T3 1235 T16 25
valid_sources[0x22] 290359 1 T1 18 T3 1174 T16 24
valid_sources[0x23] 290753 1 T1 11 T3 1232 T16 19
valid_sources[0x24] 299788 1 T1 8 T3 1179 T16 18
valid_sources[0x25] 304988 1 T1 8 T3 1265 T16 26
valid_sources[0x26] 291577 1 T1 8 T3 1243 T16 17
valid_sources[0x27] 289714 1 T1 12 T3 1255 T16 20
valid_sources[0x28] 304464 1 T1 12 T3 1226 T16 12
valid_sources[0x29] 308084 1 T1 6 T3 1156 T16 28
valid_sources[0x2a] 298538 1 T1 9 T3 1224 T16 19
valid_sources[0x2b] 809763 1 T1 10 T3 1163 T16 21
valid_sources[0x2c] 296893 1 T1 8 T3 1188 T16 21
valid_sources[0x2d] 297005 1 T1 19 T3 1257 T16 24
valid_sources[0x2e] 304520 1 T1 11 T3 1208 T16 28
valid_sources[0x2f] 303376 1 T1 6 T3 1217 T16 17
valid_sources[0x30] 317607 1 T1 6 T3 1131 T16 29
valid_sources[0x31] 299602 1 T1 12 T3 1205 T16 22
valid_sources[0x32] 317015 1 T1 6 T3 1201 T16 31
valid_sources[0x33] 301693 1 T1 15 T3 1184 T16 23
valid_sources[0x34] 789606 1 T1 3 T3 1163 T16 27
valid_sources[0x35] 648247 1 T1 9 T3 1262 T16 20
valid_sources[0x36] 292849 1 T1 7 T3 1212 T16 19
valid_sources[0x37] 307626 1 T1 15 T3 1234 T16 23
valid_sources[0x38] 305923 1 T1 9 T3 1171 T16 26
valid_sources[0x39] 290530 1 T1 10 T3 1176 T16 22
valid_sources[0x3a] 310451 1 T1 10 T3 1178 T16 19
valid_sources[0x3b] 775842 1 T1 13 T3 1189 T16 24
valid_sources[0x3c] 971078 1 T1 17 T3 1178 T16 23
valid_sources[0x3d] 298267 1 T1 7 T3 1215 T16 17
valid_sources[0x3e] 355667 1 T1 8 T3 1161 T16 18
valid_sources[0x3f] 761059 1 T1 5 T3 1193 T16 27
valid_sources[0x40] 315834 1 T1 2 T3 1278 T16 12
valid_sources[0x41] 297433 1 T1 8 T3 1210 T16 18
valid_sources[0x42] 302912 1 T1 12 T3 1235 T16 38
valid_sources[0x43] 307780 1 T1 13 T3 1248 T16 22
valid_sources[0x44] 304215 1 T1 8 T3 1244 T16 22
valid_sources[0x45] 288585 1 T1 16 T3 1195 T16 24
valid_sources[0x46] 500567 1 T1 9 T3 1227 T16 21
valid_sources[0x47] 306699 1 T1 12 T3 1279 T16 17
valid_sources[0x48] 679774 1 T1 9 T3 1256 T16 34
valid_sources[0x49] 301630 1 T1 9 T3 1279 T16 28
valid_sources[0x4a] 353721 1 T1 9 T3 1229 T16 22
valid_sources[0x4b] 293365 1 T1 9 T3 1288 T16 27
valid_sources[0x4c] 315804 1 T1 7 T3 1227 T16 28
valid_sources[0x4d] 295610 1 T1 12 T3 1109 T16 23
valid_sources[0x4e] 526254 1 T1 10 T3 1188 T16 30
valid_sources[0x4f] 712431 1 T1 13 T3 1246 T16 18
valid_sources[0x50] 332975 1 T1 14 T3 1245 T16 36
valid_sources[0x51] 312258 1 T1 8 T3 1200 T16 26
valid_sources[0x52] 305490 1 T1 4 T3 1200 T16 24
valid_sources[0x53] 311022 1 T1 14 T3 1202 T16 19
valid_sources[0x54] 296201 1 T1 16 T3 1168 T16 18
valid_sources[0x55] 306943 1 T1 8 T3 1193 T16 18
valid_sources[0x56] 297027 1 T1 8 T3 1168 T16 30
valid_sources[0x57] 301539 1 T1 13 T3 1216 T16 14
valid_sources[0x58] 630629 1 T1 9 T3 1170 T16 16
valid_sources[0x59] 305775 1 T1 10 T3 1223 T16 16
valid_sources[0x5a] 319620 1 T1 8 T3 1225 T16 24
valid_sources[0x5b] 307161 1 T1 12 T3 1252 T16 25
valid_sources[0x5c] 306859 1 T1 9 T3 1195 T16 25
valid_sources[0x5d] 316686 1 T1 10 T3 1197 T16 19
valid_sources[0x5e] 300852 1 T1 13 T3 1143 T16 23
valid_sources[0x5f] 293649 1 T1 9 T3 1181 T16 18
valid_sources[0x60] 926469 1 T1 9 T3 1207 T16 22
valid_sources[0x61] 298102 1 T1 15 T3 1275 T16 22
valid_sources[0x62] 299092 1 T1 18 T3 1272 T16 24
valid_sources[0x63] 296411 1 T1 9 T3 1213 T16 23
valid_sources[0x64] 297710 1 T1 5 T3 1152 T16 21
valid_sources[0x65] 296040 1 T1 7 T3 1236 T16 21
valid_sources[0x66] 291732 1 T1 5 T3 1209 T16 20
valid_sources[0x67] 304270 1 T1 12 T3 1209 T16 19
valid_sources[0x68] 306567 1 T1 9 T3 1219 T16 28
valid_sources[0x69] 645551 1 T1 11 T3 1249 T16 20
valid_sources[0x6a] 293515 1 T1 11 T3 1164 T16 16
valid_sources[0x6b] 297349 1 T1 2 T3 1157 T16 17
valid_sources[0x6c] 681795 1 T1 2 T3 1195 T16 29
valid_sources[0x6d] 302945 1 T1 13 T3 1166 T16 20
valid_sources[0x6e] 306251 1 T1 8 T3 1172 T16 16
valid_sources[0x6f] 304659 1 T1 4 T3 1158 T16 34
valid_sources[0x70] 299929 1 T1 6 T3 1165 T16 22
valid_sources[0x71] 304363 1 T1 13 T3 1176 T16 34
valid_sources[0x72] 294450 1 T1 10 T3 1169 T16 18
valid_sources[0x73] 308010 1 T1 11 T3 1266 T16 20
valid_sources[0x74] 305886 1 T1 4 T3 1192 T16 22
valid_sources[0x75] 585345 1 T1 5 T3 1302 T16 23
valid_sources[0x76] 298221 1 T1 10 T3 1240 T16 19
valid_sources[0x77] 298757 1 T1 13 T3 1233 T16 23
valid_sources[0x78] 295853 1 T1 12 T3 1179 T16 30
valid_sources[0x79] 306612 1 T1 12 T3 1034 T16 24
valid_sources[0x7a] 303646 1 T1 13 T3 1218 T16 19
valid_sources[0x7b] 296958 1 T1 3 T3 1213 T16 21
valid_sources[0x7c] 292464 1 T1 7 T3 1223 T16 23
valid_sources[0x7d] 322882 1 T1 6 T3 1184 T16 27
valid_sources[0x7e] 307015 1 T1 15 T3 1192 T16 22
valid_sources[0x7f] 340680 1 T1 9 T3 1265 T16 32
valid_sources[0x80] 294386 1 T1 12 T3 1150 T16 26



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7068782 1 T1 180 T2 22763 T3 19184
values[0x0] all_enables biggest_size 14967751 1 T1 425 T2 60708 T3 50108
values[0x1] all_enables biggest_size 8772058 1 T1 225 T2 34047 T3 28153

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%