Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T39,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15624	0	0
DisabledNoTrigBkwd_A	2147483647	757590	0	0
DisabledNoTrigFwd_A	2147483647	1477983858	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15624	0	0
T10	49854	0	0	0
T28	733407	0	0	0
T31	12186	0	0	0
T39	3104	235	0	0
T40	17376	0	0	0
T41	185203	0	0	0
T48	676813	0	0	0
T49	34409	0	0	0
T192	1375	650	0	0
T219	4696	1287	0	0
T220	0	750	0	0
T221	0	462	0	0
T222	0	350	0	0
T223	0	989	0	0
T224	0	629	0	0
T225	0	1344	0	0
T226	0	668	0	0
T227	0	1564	0	0
T228	0	219	0	0
T229	0	369	0	0
T230	0	844	0	0
T231	0	995	0	0
T232	0	1080	0	0
T233	0	804	0	0
T234	0	741	0	0
T235	0	814	0	0
T236	0	830	0	0
T237	25877	0	0	0
T238	63690	0	0	0
T239	61093	0	0	0
T240	12261	0	0	0
T241	107872	0	0	0
T242	37582	0	0	0
T243	15876	0	0	0
T244	402516	0	0	0
T245	193778	0	0	0
T246	75015	0	0	0
T247	331298	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	757590	0	0
T1	26998	1	0	0
T2	1229058	5773	0	0
T3	1222588	874	0	0
T4	2192512	397	0	0
T5	1300304	2052	0	0
T6	3649832	0	0	0
T8	0	18	0	0
T12	832386	3642	0	0
T13	133103	516	0	0
T14	0	1579	0	0
T15	0	2137	0	0
T16	219804	2	0	0
T17	405424	5	0	0
T18	223780	15	0	0
T19	267756	20	0	0
T20	0	29	0	0
T21	0	1974	0	0
T22	0	3	0	0
T42	0	339	0	0
T44	0	113	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1477983858	0	0
T1	107992	81304	0	0
T2	1638744	832660	0	0
T3	1222588	1585202	0	0
T4	2192512	1149734	0	0
T5	1300304	1451895	0	0
T6	3649832	2785223	0	0
T16	219804	175229	0	0
T17	405424	389874	0	0
T18	223780	165336	0	0
T19	267756	135420	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T223,T226
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671533363	3526	0	0
DisabledNoTrigBkwd_A	671533363	230251	0	0
DisabledNoTrigFwd_A	671533363	323841639	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	3526	0	0
T39	3104	235	0	0
T40	17376	0	0	0
T41	185203	0	0	0
T48	676813	0	0	0
T223	0	989	0	0
T226	0	668	0	0
T233	0	804	0	0
T236	0	830	0	0
T237	25877	0	0	0
T238	63690	0	0	0
T239	61093	0	0	0
T240	12261	0	0	0
T241	107872	0	0	0
T242	37582	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	230251	0	0
T1	26998	1	0	0
T2	409686	1501	0	0
T3	305647	6	0	0
T4	548128	134	0	0
T5	325076	1637	0	0
T6	912458	0	0	0
T12	0	1415	0	0
T15	0	2135	0	0
T16	54951	2	0	0
T17	101356	5	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	87	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	323841639	0	0
T1	26998	19950	0	0
T2	409686	13460	0	0
T3	305647	248030	0	0
T4	548128	50511	0	0
T5	325076	580899	0	0
T6	912458	48041	0	0
T16	54951	10529	0	0
T17	101356	95656	0	0
T18	55945	55856	0	0
T19	66939	860	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T6,T5
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T219,T222,T225
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671533363	3350	0	0
DisabledNoTrigBkwd_A	671533363	195214	0	0
DisabledNoTrigFwd_A	671533363	390227832	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	3350	0	0
T10	49854	0	0	0
T28	733407	0	0	0
T31	12186	0	0	0
T49	34409	0	0	0
T219	4696	1287	0	0
T222	0	350	0	0
T225	0	1344	0	0
T229	0	369	0	0
T243	15876	0	0	0
T244	402516	0	0	0
T245	193778	0	0	0
T246	75015	0	0	0
T247	331298	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	195214	0	0
T2	409686	4254	0	0
T3	305647	115	0	0
T4	548128	263	0	0
T5	325076	318	0	0
T6	912458	0	0	0
T12	277462	2	0	0
T13	0	1	0	0
T14	0	1571	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	5	0	0
T19	66939	20	0	0
T42	0	93	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	390227832	0	0
T1	26998	26898	0	0
T2	409686	3021	0	0
T3	305647	287255	0	0
T4	548128	3137	0	0
T5	325076	281647	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	101268	0	0
T18	55945	44137	0	0
T19	66939	864	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T192,T221,T228
1	1	Covered	T2,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671533363	3152	0	0
DisabledNoTrigBkwd_A	671533363	166220	0	0
DisabledNoTrigFwd_A	671533363	375962011	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	3152	0	0
T25	209421	0	0	0
T79	143035	0	0	0
T83	499357	0	0	0
T85	42808	0	0	0
T128	164096	0	0	0
T192	1375	650	0	0
T221	0	462	0	0
T228	0	219	0	0
T232	0	1080	0	0
T234	0	741	0	0
T248	141266	0	0	0
T249	16005	0	0	0
T250	156720	0	0	0
T251	19482	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	166220	0	0
T3	305647	71	0	0
T4	548128	0	0	0
T5	325076	70	0	0
T6	912458	0	0	0
T12	277462	973	0	0
T13	133103	0	0	0
T15	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	10	0	0
T19	66939	0	0	0
T20	0	29	0	0
T21	0	90	0	0
T22	0	2	0	0
T42	0	76	0	0
T44	0	113	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	375962011	0	0
T1	26998	20321	0	0
T2	409686	409119	0	0
T3	305647	287719	0	0
T4	548128	548043	0	0
T5	325076	274003	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	96475	0	0
T18	55945	9487	0	0
T19	66939	66848	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T220,T224,T227
1	1	Covered	T2,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	671533363	5596	0	0
DisabledNoTrigBkwd_A	671533363	165905	0	0
DisabledNoTrigFwd_A	671533363	387952376	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	5596	0	0
T55	151237	0	0	0
T102	12358	0	0	0
T220	1602	750	0	0
T224	0	629	0	0
T227	0	1564	0	0
T230	0	844	0	0
T231	0	995	0	0
T235	0	814	0	0
T252	11728	0	0	0
T253	11256	0	0	0
T254	134773	0	0	0
T255	40763	0	0	0
T256	920274	0	0	0
T257	50451	0	0	0
T258	18464	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	165905	0	0
T2	409686	18	0	0
T3	305647	682	0	0
T4	548128	0	0	0
T5	325076	27	0	0
T6	912458	0	0	0
T8	0	18	0	0
T12	277462	1252	0	0
T13	0	515	0	0
T14	0	8	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	1884	0	0
T22	0	1	0	0
T42	0	83	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	387952376	0	0
T1	26998	14135	0	0
T2	409686	407060	0	0
T3	305647	762198	0	0
T4	548128	548043	0	0
T5	325076	315346	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	96475	0	0
T18	55945	55856	0	0
T19	66939	66848	0	0