Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T5,T18
1	1	1	Covered	T3,T5,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T18
0	1	Covered	T3,T5,T20
1	0	Covered	T21,T22,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Not Covered
1	1	Covered	T3,T5,T20

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T12

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T3,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T3,T5,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T3,T5,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T24,T25,T26
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T26,T27,T28
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T29,T30,T31
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T13,T14,T23
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T3,T5,T17
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T3,T5,T18
TimeoutSt->Phase0St	167	Covered	T5,T21,T22

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T14,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1149	0	0
CheckAccumTrig0_A	2147483647	2224	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1008	0	0
CheckEn_A	2147483647	1184404025	0	0
CheckPhase0_A	2147483647	2545	0	0
CheckPhase1_A	2147483647	2494	0	0
CheckPhase2_A	2147483647	2448	0	0
CheckPhase3_A	2147483647	2421	0	0
CheckTimeout0_A	2147483647	4118	0	0
CheckTimeoutSt1_A	2147483647	428639	0	0
CheckTimeoutSt2_A	2147483647	3743	0	0
CheckTimeoutStTrig_A	2147483647	264	0	0
ErrorStAllEscAsserted_A	2147483647	5861	0	0
ErrorStIsTerminal_A	2147483647	4901	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1149	0	0
T9	271428	287	0	0
T10	0	140	0	0
T11	0	300	0	0
T27	1928108	0	0	0
T32	0	282	0	0
T33	0	140	0	0
T34	2800288	0	0	0
T35	257928	0	0	0
T36	2655148	0	0	0
T37	221640	0	0	0
T38	1961976	0	0	0
T39	12416	0	0	0
T40	69504	0	0	0
T41	740812	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2224	0	0
T1	26998	1	0	0
T2	1229058	3	0	0
T3	1222588	8	0	0
T4	2192512	2	0	0
T5	1300304	12	0	0
T6	3649832	0	0	0
T8	0	1	0	0
T12	832386	3	0	0
T13	133103	2	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	219804	1	0	0
T17	405424	1	0	0
T18	223780	3	0	0
T19	267756	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	2	0	0
T42	0	7	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T20	180636	0	0	0
T21	321540	1	0	0
T22	171108	1	0	0
T23	0	2	0	0
T30	220934	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T43	20324	0	0	0
T44	594306	0	0	0
T45	545662	0	0	0
T46	0	2	0	0
T47	373358	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	59366	0	0	0
T63	25052	0	0	0
T64	87876	0	0	0
T65	38782	0	0	0
T66	136321	0	0	0
T67	80148	0	0	0
T68	52505	0	0	0
T69	136082	0	0	0
T70	511841	0	0	0
T71	856932	0	0	0
T72	105514	0	0	0
T73	582406	0	0	0
T74	20217	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1008	0	0
T3	305647	1	0	0
T4	548128	0	0	0
T5	650152	2	0	0
T6	912458	0	0	0
T7	1733850	0	0	0
T8	263352	0	0	0
T12	832386	1	0	0
T13	399309	1	0	0
T14	984345	1	0	0
T15	1480122	2	0	0
T16	54951	0	0	0
T17	202712	1	0	0
T18	111890	1	0	0
T19	200817	1	0	0
T20	0	1	0	0
T21	643080	8	0	0
T22	171108	2	0	0
T23	0	2	0	0
T24	0	4	0	0
T25	0	1	0	0
T29	0	2	0	0
T42	892101	0	0	0
T43	10162	0	0	0
T62	29683	0	0	0
T63	12526	0	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	5	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1184404025	0	0
T1	107992	81301	0	0
T2	1638744	434627	0	0
T3	1222588	1930921	0	0
T4	2192512	1149732	0	0
T5	1300304	1372584	0	0
T6	3649832	2785220	0	0
T16	219804	170391	0	0
T17	405424	389870	0	0
T18	223780	131128	0	0
T19	267756	135418	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2545	0	0
T1	26998	1	0	0
T2	1229058	3	0	0
T3	1222588	9	0	0
T4	2192512	2	0	0
T5	1300304	15	0	0
T6	3649832	0	0	0
T8	0	1	0	0
T12	832386	4	0	0
T13	133103	2	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	219804	1	0	0
T17	405424	1	0	0
T18	223780	3	0	0
T19	267756	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	2	0	0
T42	0	7	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T1	26998	1	0	0
T2	1229058	3	0	0
T3	1222588	9	0	0
T4	2192512	2	0	0
T5	1300304	15	0	0
T6	3649832	0	0	0
T8	0	1	0	0
T12	832386	4	0	0
T13	133103	2	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	219804	1	0	0
T17	405424	1	0	0
T18	223780	3	0	0
T19	267756	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	2	0	0
T42	0	7	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448	0	0
T1	26998	1	0	0
T2	1229058	3	0	0
T3	1222588	9	0	0
T4	2192512	2	0	0
T5	1300304	15	0	0
T6	3649832	0	0	0
T8	0	1	0	0
T12	832386	4	0	0
T13	133103	2	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	219804	1	0	0
T17	405424	1	0	0
T18	223780	3	0	0
T19	267756	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	2	0	0
T42	0	7	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2421	0	0
T1	26998	1	0	0
T2	1229058	3	0	0
T3	1222588	9	0	0
T4	2192512	2	0	0
T5	1300304	15	0	0
T6	3649832	0	0	0
T8	0	1	0	0
T12	832386	4	0	0
T13	133103	1	0	0
T14	0	3	0	0
T15	0	4	0	0
T16	219804	1	0	0
T17	405424	1	0	0
T18	223780	3	0	0
T19	267756	2	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	2	0	0
T42	0	7	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4118	0	0
T3	916941	11	0	0
T4	1644384	0	0	0
T5	1300304	35	0	0
T6	2737374	0	0	0
T7	577950	0	0	0
T12	1109848	2	0	0
T13	532412	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T16	164853	0	0	0
T17	405424	0	0	0
T18	223780	3	0	0
T19	267756	0	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	24	0	0
T42	297367	7	0	0
T63	0	6	0	0
T75	0	5	0	0
T76	0	11	0	0
T77	0	11	0	0
T80	0	18	0	0
T81	0	1	0	0
T82	0	11	0	0
T83	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428639	0	0
T3	916941	1446	0	0
T4	1644384	0	0	0
T5	1300304	2391	0	0
T6	2737374	0	0	0
T7	577950	0	0	0
T12	1109848	102	0	0
T13	532412	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T16	164853	0	0	0
T17	405424	0	0	0
T18	223780	347	0	0
T19	267756	0	0	0
T20	0	507	0	0
T21	0	232	0	0
T24	0	4068	0	0
T42	297367	395	0	0
T63	0	262	0	0
T75	0	893	0	0
T76	0	2219	0	0
T77	0	1093	0	0
T80	0	3739	0	0
T81	0	62	0	0
T82	0	1881	0	0
T83	0	557	0	0
T84	0	307	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3743	0	0
T3	916941	10	0	0
T4	1644384	0	0	0
T5	1300304	32	0	0
T6	2737374	0	0	0
T7	577950	0	0	0
T12	1109848	1	0	0
T13	532412	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T16	164853	0	0	0
T17	405424	0	0	0
T18	223780	3	0	0
T19	267756	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T24	0	22	0	0
T42	297367	7	0	0
T63	0	6	0	0
T75	0	2	0	0
T76	0	5	0	0
T77	0	8	0	0
T80	0	17	0	0
T82	0	10	0	0
T83	0	11	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	264	0	0
T3	305647	1	0	0
T5	975228	3	0	0
T7	1155900	0	0	0
T12	832386	0	0	0
T13	399309	0	0	0
T14	656230	0	0	0
T15	986748	0	0	0
T17	304068	0	0	0
T18	167835	0	0	0
T19	200817	0	0	0
T20	90318	1	0	0
T24	449349	0	0	0
T29	379241	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T42	594734	0	0	0
T45	272831	0	0	0
T47	0	4	0	0
T48	0	1	0	0
T65	19391	0	0	0
T66	136321	0	0	0
T70	0	5	0	0
T75	60801	3	0	0
T76	458548	6	0	0
T77	281371	3	0	0
T80	106425	1	0	0
T81	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T92	0	2	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5861	0	0
T9	271428	1494	0	0
T10	0	733	0	0
T11	0	1419	0	0
T27	1928108	0	0	0
T32	0	1475	0	0
T33	0	740	0	0
T34	2800288	0	0	0
T35	257928	0	0	0
T36	2655148	0	0	0
T37	221640	0	0	0
T38	1961976	0	0	0
T39	12416	0	0	0
T40	69504	0	0	0
T41	740812	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4901	0	0
T9	271428	1254	0	0
T10	0	613	0	0
T11	0	1179	0	0
T27	1928108	0	0	0
T32	0	1235	0	0
T33	0	620	0	0
T34	2800288	0	0	0
T35	257928	0	0	0
T36	2655148	0	0	0
T37	221640	0	0	0
T38	1961976	0	0	0
T39	12416	0	0	0
T40	69504	0	0	0
T41	740812	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107992	107592	0	0
T2	1638744	1638704	0	0
T3	1222588	1222412	0	0
T4	2192512	2192172	0	0
T5	1300304	1300012	0	0
T6	3649832	3649576	0	0
T16	219804	219600	0	0
T17	405424	405072	0	0
T18	223780	223424	0	0
T19	267756	267392	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T3,T5,T42
1	1	1	Covered	T3,T5,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T63
0	1	Covered	T5,T76,T80
1	0	Covered	T22,T23,T46

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T63
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T23,T46

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T22
1	0	Not Covered
1	1	Covered	T5,T76,T80

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T2,T3,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T16,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T16,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T3,T5,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T3,T5,T22
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T25,T28,T94
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T27,T28
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T30,T95,T96
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T23,T83,T54
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T5,T17
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T63,T80
TimeoutSt->Phase0St	167	Covered	T5,T22,T76

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T22,T76
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T63
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T63,T80
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T28,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T95,T96
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T83,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T17,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671533363	276	0	0
CheckAccumTrig0_A	671533363	787	0	0
CheckAccumTrig1_A	671533363	47	0	0
CheckClr_A	671533363	380	0	0
CheckEn_A	670865601	228413558	0	0
CheckPhase0_A	671533363	904	0	0
CheckPhase1_A	671533363	889	0	0
CheckPhase2_A	671533363	875	0	0
CheckPhase3_A	671533363	866	0	0
CheckTimeout0_A	671533363	1127	0	0
CheckTimeoutSt1_A	671533363	119778	0	0
CheckTimeoutSt2_A	671533363	994	0	0
CheckTimeoutStTrig_A	671533363	84	0	0
ErrorStAllEscAsserted_A	671533363	1441	0	0
ErrorStIsTerminal_A	671533363	1201	0	0
u_state_regs_A	671533363	671361992	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	276	0	0
T9	67857	56	0	0
T10	0	34	0	0
T11	0	64	0	0
T27	482027	0	0	0
T32	0	84	0	0
T33	0	38	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	787	0	0
T1	26998	1	0	0
T2	409686	1	0	0
T3	305647	3	0	0
T4	548128	1	0	0
T5	325076	6	0	0
T6	912458	0	0	0
T12	0	1	0	0
T15	0	2	0	0
T16	54951	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	47	0	0
T20	90318	0	0	0
T22	85554	1	0	0
T23	0	2	0	0
T36	0	1	0	0
T43	10162	0	0	0
T44	297153	0	0	0
T45	272831	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	5	0	0
T62	29683	0	0	0
T63	12526	0	0	0
T64	43938	0	0	0
T65	19391	0	0	0
T66	136321	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	380	0	0
T5	325076	1	0	0
T7	577950	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	3	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	3	0	0
T25	0	1	0	0
T42	297367	0	0	0
T76	0	4	0	0
T77	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670865601	228413558	0	0
T1	26998	19950	0	0
T2	409686	8564	0	0
T3	305647	248030	0	0
T4	548128	50511	0	0
T5	325076	513074	0	0
T6	912458	48041	0	0
T16	54951	5694	0	0
T17	101356	95655	0	0
T18	55945	55855	0	0
T19	66939	860	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	904	0	0
T1	26998	1	0	0
T2	409686	1	0	0
T3	305647	3	0	0
T4	548128	1	0	0
T5	325076	7	0	0
T6	912458	0	0	0
T12	0	1	0	0
T15	0	2	0	0
T16	54951	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	889	0	0
T1	26998	1	0	0
T2	409686	1	0	0
T3	305647	3	0	0
T4	548128	1	0	0
T5	325076	7	0	0
T6	912458	0	0	0
T12	0	1	0	0
T15	0	2	0	0
T16	54951	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	875	0	0
T1	26998	1	0	0
T2	409686	1	0	0
T3	305647	3	0	0
T4	548128	1	0	0
T5	325076	7	0	0
T6	912458	0	0	0
T12	0	1	0	0
T15	0	2	0	0
T16	54951	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	866	0	0
T1	26998	1	0	0
T2	409686	1	0	0
T3	305647	3	0	0
T4	548128	1	0	0
T5	325076	7	0	0
T6	912458	0	0	0
T12	0	1	0	0
T15	0	2	0	0
T16	54951	1	0	0
T17	101356	1	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1127	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T22	0	1	0	0
T24	0	2	0	0
T63	0	2	0	0
T76	0	2	0	0
T77	0	7	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	119778	0	0
T3	305647	313	0	0
T4	548128	0	0	0
T5	325076	70	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T24	0	175	0	0
T63	0	91	0	0
T76	0	988	0	0
T77	0	635	0	0
T80	0	301	0	0
T81	0	62	0	0
T82	0	692	0	0
T84	0	307	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	994	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	0	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T24	0	2	0	0
T63	0	2	0	0
T77	0	6	0	0
T80	0	1	0	0
T82	0	4	0	0
T83	0	5	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	84	0	0
T5	325076	1	0	0
T7	577950	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T42	297367	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1441	0	0
T9	67857	365	0	0
T10	0	188	0	0
T11	0	321	0	0
T27	482027	0	0	0
T32	0	361	0	0
T33	0	206	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1201	0	0
T9	67857	305	0	0
T10	0	158	0	0
T11	0	261	0	0
T27	482027	0	0	0
T32	0	301	0	0
T33	0	176	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	671361992	0	0
T1	26998	26898	0	0
T2	409686	409676	0	0
T3	305647	305603	0	0
T4	548128	548043	0	0
T5	325076	325003	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	101268	0	0
T18	55945	55856	0	0
T19	66939	66848	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T18
1	0	1	Covered	T4,T5,T19
1	1	0	Covered	T3,T5,T12
1	1	1	Covered	T5,T12,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T12,T21
0	1	Covered	T20,T75,T76
1	0	Covered	T21,T52,T53

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T12,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T52,T53

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T21
1	0	Not Covered
1	1	Covered	T20,T75,T76

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T5,T12,T13

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T14,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T2,T3,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T4,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T5,T12,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T5,T12,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T26,T72
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T97,T98,T99
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T29,T31,T100
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T13,T14,T101
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T5,T19
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T5,T12,T20
TimeoutSt->Phase0St	167	Covered	T21,T20,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T20,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T12,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T26,T72
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T97,T98,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T31,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T14,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T12,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671533363	308	0	0
CheckAccumTrig0_A	671533363	488	0	0
CheckAccumTrig1_A	671533363	22	0	0
CheckClr_A	671533363	224	0	0
CheckEn_A	670865601	307854971	0	0
CheckPhase0_A	671533363	566	0	0
CheckPhase1_A	671533363	556	0	0
CheckPhase2_A	671533363	543	0	0
CheckPhase3_A	671533363	532	0	0
CheckTimeout0_A	671533363	1023	0	0
CheckTimeoutSt1_A	671533363	113744	0	0
CheckTimeoutSt2_A	671533363	930	0	0
CheckTimeoutStTrig_A	671533363	69	0	0
ErrorStAllEscAsserted_A	671533363	1464	0	0
ErrorStIsTerminal_A	671533363	1224	0	0
u_state_regs_A	671533363	671361992	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	308	0	0
T9	67857	89	0	0
T10	0	31	0	0
T11	0	79	0	0
T27	482027	0	0	0
T32	0	74	0	0
T33	0	35	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	488	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	1	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	2	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	22	0	0
T20	90318	0	0	0
T21	321540	1	0	0
T22	85554	0	0	0
T43	10162	0	0	0
T44	297153	0	0	0
T45	272831	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	29683	0	0	0
T63	12526	0	0	0
T64	43938	0	0	0
T65	19391	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	224	0	0
T7	577950	0	0	0
T8	131676	0	0	0
T12	277462	1	0	0
T13	133103	1	0	0
T14	328115	1	0	0
T15	493374	0	0	0
T19	66939	1	0	0
T20	0	1	0	0
T21	321540	1	0	0
T22	85554	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T42	297367	0	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670865601	307854971	0	0
T1	26998	26897	0	0
T2	409686	3021	0	0
T3	305647	633117	0	0
T4	548128	3137	0	0
T5	325076	279066	0	0
T6	912458	912393	0	0
T16	54951	54899	0	0
T17	101356	101267	0	0
T18	55945	9931	0	0
T19	66939	864	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	566	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	1	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	2	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	556	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	1	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	2	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	543	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	1	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	2	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	532	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	1	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	2	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1023	0	0
T5	325076	3	0	0
T7	577950	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T24	0	11	0	0
T42	297367	0	0	0
T75	0	3	0	0
T76	0	4	0	0
T77	0	1	0	0
T80	0	8	0	0
T82	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	113744	0	0
T5	325076	384	0	0
T7	577950	0	0	0
T12	277462	64	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T20	0	507	0	0
T21	0	10	0	0
T24	0	1513	0	0
T42	297367	0	0	0
T75	0	515	0	0
T76	0	254	0	0
T77	0	105	0	0
T80	0	1747	0	0
T82	0	862	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	930	0	0
T5	325076	3	0	0
T7	577950	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T20	0	1	0	0
T24	0	11	0	0
T42	297367	0	0	0
T75	0	1	0	0
T76	0	3	0	0
T80	0	8	0	0
T82	0	5	0	0
T83	0	5	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	69	0	0
T20	90318	1	0	0
T24	449349	0	0	0
T29	379241	0	0	0
T34	0	2	0	0
T45	272831	0	0	0
T47	0	1	0	0
T65	19391	0	0	0
T66	136321	0	0	0
T70	0	2	0	0
T75	60801	2	0	0
T76	458548	1	0	0
T77	281371	1	0	0
T80	106425	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1464	0	0
T9	67857	366	0	0
T10	0	172	0	0
T11	0	357	0	0
T27	482027	0	0	0
T32	0	392	0	0
T33	0	177	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1224	0	0
T9	67857	306	0	0
T10	0	142	0	0
T11	0	297	0	0
T27	482027	0	0	0
T32	0	332	0	0
T33	0	147	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	671361992	0	0
T1	26998	26898	0	0
T2	409686	409676	0	0
T3	305647	305603	0	0
T4	548128	548043	0	0
T5	325076	325003	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	101268	0	0
T18	55945	55856	0	0
T19	66939	66848	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T18

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T5,T17
1	0	1	Covered	T5,T42,T15
1	1	0	Covered	T3,T5,T18
1	1	1	Covered	T3,T5,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T18
0	1	Covered	T5,T75,T76
1	0	Covered	T47,T38,T102

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T38,T102

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Not Covered
1	1	Covered	T5,T75,T76

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T3,T5,T42

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T5,T18,T12

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T18,T21,T22

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T3,T5,T42

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T5,T18
Phase1St	193	Covered	T3,T5,T18
Phase2St	210	Covered	T3,T5,T18
Phase3St	228	Covered	T3,T5,T18
TerminalSt	244	Covered	T3,T5,T18
TimeoutSt	154	Covered	T3,T5,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T3,T5,T18
IdleSt->TimeoutSt	154	Covered	T3,T5,T18
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T47,T27,T103
Phase0St->Phase1St	193	Covered	T3,T5,T18
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T55,T93,T104
Phase1St->Phase2St	210	Covered	T3,T5,T18
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T96,T105,T106
Phase2St->Phase3St	228	Covered	T3,T5,T18
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T107,T108,T109
Phase3St->TerminalSt	244	Covered	T3,T5,T18
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T5,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T5,T18
TimeoutSt->Phase0St	167	Covered	T5,T75,T76

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T75,T76
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T103,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T55,T104,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T105,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T5,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671533363	262	0	0
CheckAccumTrig0_A	671533363	491	0	0
CheckAccumTrig1_A	671533363	19	0	0
CheckClr_A	671533363	211	0	0
CheckEn_A	670865601	330622728	0	0
CheckPhase0_A	671533363	548	0	0
CheckPhase1_A	671533363	538	0	0
CheckPhase2_A	671533363	526	0	0
CheckPhase3_A	671533363	522	0	0
CheckTimeout0_A	671533363	1111	0	0
CheckTimeoutSt1_A	671533363	102859	0	0
CheckTimeoutSt2_A	671533363	1039	0	0
CheckTimeoutStTrig_A	671533363	52	0	0
ErrorStAllEscAsserted_A	671533363	1466	0	0
ErrorStIsTerminal_A	671533363	1226	0	0
u_state_regs_A	671533363	671361992	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	262	0	0
T9	67857	78	0	0
T10	0	25	0	0
T11	0	90	0	0
T27	482027	0	0	0
T32	0	47	0	0
T33	0	22	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	491	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	4	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	2	0	0
T19	66939	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	19	0	0
T30	220934	0	0	0
T38	0	1	0	0
T47	373358	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	80148	0	0	0
T68	52505	0	0	0
T69	136082	0	0	0
T70	511841	0	0	0
T71	856932	0	0	0
T72	105514	0	0	0
T73	582406	0	0	0
T74	20217	0	0	0
T102	0	1	0	0
T105	0	1	0	0
T110	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	211	0	0
T3	305647	1	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	1	0	0
T19	66939	0	0	0
T21	0	4	0	0
T29	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670865601	330622728	0	0
T1	26998	20320	0	0
T2	409686	409119	0	0
T3	305647	287580	0	0
T4	548128	548042	0	0
T5	325076	265099	0	0
T6	912458	912393	0	0
T16	54951	54899	0	0
T17	101356	96474	0	0
T18	55945	9487	0	0
T19	66939	66847	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	548	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	5	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	2	0	0
T19	66939	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	538	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	5	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	2	0	0
T19	66939	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	526	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	5	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	2	0	0
T19	66939	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	522	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	5	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T15	0	1	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	2	0	0
T19	66939	0	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1111	0	0
T3	305647	7	0	0
T4	548128	0	0	0
T5	325076	28	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	3	0	0
T19	66939	0	0	0
T21	0	1	0	0
T42	0	7	0	0
T63	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0
T80	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	102859	0	0
T3	305647	946	0	0
T4	548128	0	0	0
T5	325076	1285	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	347	0	0
T19	66939	0	0	0
T21	0	101	0	0
T42	0	395	0	0
T63	0	171	0	0
T75	0	378	0	0
T76	0	804	0	0
T77	0	321	0	0
T80	0	1347	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1039	0	0
T3	305647	7	0	0
T4	548128	0	0	0
T5	325076	27	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	3	0	0
T19	66939	0	0	0
T21	0	1	0	0
T42	0	7	0	0
T63	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T80	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	52	0	0
T5	325076	1	0	0
T7	577950	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T14	328115	0	0	0
T15	493374	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	297367	0	0	0
T47	0	2	0	0
T48	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1466	0	0
T9	67857	388	0	0
T10	0	167	0	0
T11	0	358	0	0
T27	482027	0	0	0
T32	0	371	0	0
T33	0	182	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1226	0	0
T9	67857	328	0	0
T10	0	137	0	0
T11	0	298	0	0
T27	482027	0	0	0
T32	0	311	0	0
T33	0	152	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	671361992	0	0
T1	26998	26898	0	0
T2	409686	409676	0	0
T3	305647	305603	0	0
T4	548128	548043	0	0
T5	325076	325003	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	101268	0	0
T18	55945	55856	0	0
T19	66939	66848	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T13

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T3,T13,T42
1	1	0	Covered	T3,T5,T42
1	1	1	Covered	T3,T5,T12

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T48,T51,T54

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T51,T54

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T12
1	0	Not Covered
1	1	Covered	T3,T5,T12

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T13,T14,T42

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T2,T3,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T5,T12,T22

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T8,T21

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T5
Phase1St	193	Covered	T2,T3,T5
Phase2St	210	Covered	T2,T3,T5
Phase3St	228	Covered	T2,T3,T5
TerminalSt	244	Covered	T2,T3,T5
TimeoutSt	154	Covered	T3,T5,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T13
IdleSt->TimeoutSt	154	Covered	T3,T5,T12
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T70,T36,T114
Phase0St->Phase1St	193	Covered	T2,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T70,T55,T92
Phase1St->Phase2St	210	Covered	T2,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T114,T109,T115
Phase2St->Phase3St	228	Covered	T2,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T26,T70,T116
Phase3St->TerminalSt	244	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T5,T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T5,T21
TimeoutSt->Phase0St	167	Covered	T3,T5,T12

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T70,T114,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T70,T55,T92
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T114,T109,T115
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T70,T116
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T21,T77
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	671533363	303	0	0
CheckAccumTrig0_A	671533363	458	0	0
CheckAccumTrig1_A	671533363	18	0	0
CheckClr_A	671533363	193	0	0
CheckEn_A	670865601	317512768	0	0
CheckPhase0_A	671533363	527	0	0
CheckPhase1_A	671533363	511	0	0
CheckPhase2_A	671533363	504	0	0
CheckPhase3_A	671533363	501	0	0
CheckTimeout0_A	671533363	857	0	0
CheckTimeoutSt1_A	671533363	92258	0	0
CheckTimeoutSt2_A	671533363	780	0	0
CheckTimeoutStTrig_A	671533363	59	0	0
ErrorStAllEscAsserted_A	671533363	1490	0	0
ErrorStIsTerminal_A	671533363	1250	0	0
u_state_regs_A	671533363	671361992	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	303	0	0
T9	67857	64	0	0
T10	0	50	0	0
T11	0	67	0	0
T27	482027	0	0	0
T32	0	77	0	0
T33	0	45	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	458	0	0
T2	409686	1	0	0
T3	305647	1	0	0
T4	548128	0	0	0
T5	325076	0	0	0
T6	912458	0	0	0
T8	0	1	0	0
T12	277462	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	18	0	0
T48	676813	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T92	0	1	0	0
T97	0	1	0	0
T101	140201	0	0	0
T109	0	1	0	0
T114	190860	0	0	0
T117	0	4	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	10852	0	0	0
T122	128978	0	0	0
T123	3359	0	0	0
T124	335865	0	0	0
T125	184238	0	0	0
T126	21404	0	0	0
T127	52290	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	193	0	0
T7	577950	0	0	0
T8	131676	0	0	0
T14	328115	1	0	0
T15	493374	0	0	0
T21	321540	1	0	0
T22	85554	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T42	297367	0	0	0
T43	10162	0	0	0
T62	29683	0	0	0
T63	12526	0	0	0
T70	0	9	0	0
T77	0	1	0	0
T83	0	6	0	0
T84	0	2	0	0
T85	0	1	0	0
T128	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670865601	317512768	0	0
T1	26998	14134	0	0
T2	409686	13923	0	0
T3	305647	762194	0	0
T4	548128	548042	0	0
T5	325076	315345	0	0
T6	912458	912393	0	0
T16	54951	54899	0	0
T17	101356	96474	0	0
T18	55945	55855	0	0
T19	66939	66847	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	527	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T8	0	1	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	511	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T8	0	1	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	504	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T8	0	1	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	501	0	0
T2	409686	1	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T8	0	1	0	0
T12	277462	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	857	0	0
T3	305647	2	0	0
T4	548128	0	0	0
T5	325076	3	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	1	0	0
T24	0	11	0	0
T76	0	3	0	0
T77	0	1	0	0
T80	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	92258	0	0
T3	305647	187	0	0
T4	548128	0	0	0
T5	325076	652	0	0
T6	912458	0	0	0
T12	277462	38	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	121	0	0
T24	0	2380	0	0
T76	0	173	0	0
T77	0	32	0	0
T80	0	344	0	0
T82	0	327	0	0
T83	0	557	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	780	0	0
T3	305647	1	0	0
T4	548128	0	0	0
T5	325076	2	0	0
T6	912458	0	0	0
T12	277462	0	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T21	0	1	0	0
T24	0	9	0	0
T76	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T87	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	59	0	0
T3	305647	1	0	0
T4	548128	0	0	0
T5	325076	1	0	0
T6	912458	0	0	0
T12	277462	1	0	0
T13	133103	0	0	0
T16	54951	0	0	0
T17	101356	0	0	0
T18	55945	0	0	0
T19	66939	0	0	0
T24	0	2	0	0
T47	0	1	0	0
T70	0	3	0	0
T76	0	2	0	0
T77	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1490	0	0
T9	67857	375	0	0
T10	0	206	0	0
T11	0	383	0	0
T27	482027	0	0	0
T32	0	351	0	0
T33	0	175	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	1250	0	0
T9	67857	315	0	0
T10	0	176	0	0
T11	0	323	0	0
T27	482027	0	0	0
T32	0	291	0	0
T33	0	145	0	0
T34	700072	0	0	0
T35	64482	0	0	0
T36	663787	0	0	0
T37	55410	0	0	0
T38	490494	0	0	0
T39	3104	0	0	0
T40	17376	0	0	0
T41	185203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671533363	671361992	0	0
T1	26998	26898	0	0
T2	409686	409676	0	0
T3	305647	305603	0	0
T4	548128	548043	0	0
T5	325076	325003	0	0
T6	912458	912394	0	0
T16	54951	54900	0	0
T17	101356	101268	0	0
T18	55945	55856	0	0
T19	66939	66848	0	0