Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70911597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34701412

1

T1

2264

T2

264958

T3

67177

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15771114	1			T1	1064		T2	101066		T3	26288
values[0x0]	43453977	1			T1	2975		T2	329766		T3	92865
values[0x1]	46387918	1			T1	3015		T2	366776		T3	93921

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60148720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45464289

1

T1

2888

T2

353510

T3

85095

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	360040	1			T1	24		T2	2854		T3	927
valid_sources[0x01]	350494	1			T1	28		T2	3196		T3	902
valid_sources[0x02]	357698	1			T1	23		T2	3019		T3	947
valid_sources[0x03]	825863	1			T1	37		T2	3315		T3	895
valid_sources[0x04]	355098	1			T1	20		T2	2392		T3	1036
valid_sources[0x05]	352771	1			T1	36		T2	3094		T3	946
valid_sources[0x06]	376219	1			T1	13		T2	3110		T3	870
valid_sources[0x07]	366682	1			T1	16		T2	3457		T3	802
valid_sources[0x08]	352693	1			T1	29		T2	3183		T3	768
valid_sources[0x09]	355132	1			T1	24		T2	2786		T3	830
valid_sources[0x0a]	357112	1			T1	20		T2	2472		T3	891
valid_sources[0x0b]	360113	1			T1	28		T2	2409		T3	821
valid_sources[0x0c]	355160	1			T1	34		T2	2866		T3	842
valid_sources[0x0d]	371529	1			T1	28		T2	2926		T3	737
valid_sources[0x0e]	620121	1			T1	29		T2	3733		T3	862
valid_sources[0x0f]	361691	1			T1	21		T2	2960		T3	818
valid_sources[0x10]	350864	1			T1	27		T2	2868		T3	627
valid_sources[0x11]	359227	1			T1	27		T2	2962		T3	766
valid_sources[0x12]	367293	1			T1	26		T2	3313		T3	753
valid_sources[0x13]	355054	1			T1	29		T2	3361		T3	864
valid_sources[0x14]	352081	1			T1	33		T2	3045		T3	929
valid_sources[0x15]	356872	1			T1	36		T2	3360		T3	950
valid_sources[0x16]	363721	1			T1	35		T2	2951		T3	846
valid_sources[0x17]	782365	1			T1	27		T2	2874		T3	912
valid_sources[0x18]	361679	1			T1	21		T2	2878		T3	755
valid_sources[0x19]	358235	1			T1	31		T2	3323		T3	741
valid_sources[0x1a]	345624	1			T1	27		T2	2969		T3	706
valid_sources[0x1b]	824545	1			T1	32		T2	3031		T3	815
valid_sources[0x1c]	352738	1			T1	18		T2	3442		T3	806
valid_sources[0x1d]	359251	1			T1	37		T2	3512		T3	809
valid_sources[0x1e]	356244	1			T1	18		T2	3211		T3	804
valid_sources[0x1f]	353410	1			T1	21		T2	2651		T3	729
valid_sources[0x20]	743092	1			T1	34		T2	3535		T3	852
valid_sources[0x21]	361771	1			T1	24		T2	2822		T3	864
valid_sources[0x22]	352238	1			T1	29		T2	2988		T3	781
valid_sources[0x23]	359665	1			T1	30		T2	3571		T3	830
valid_sources[0x24]	358135	1			T1	30		T2	3629		T3	789
valid_sources[0x25]	358692	1			T1	36		T2	3072		T3	847
valid_sources[0x26]	367855	1			T1	23		T2	3962		T3	810
valid_sources[0x27]	358490	1			T1	27		T2	3149		T3	816
valid_sources[0x28]	362956	1			T1	22		T2	3397		T3	705
valid_sources[0x29]	584986	1			T1	32		T2	3069		T3	798
valid_sources[0x2a]	357660	1			T1	16		T2	3292		T3	830
valid_sources[0x2b]	357435	1			T1	16		T2	3089		T3	849
valid_sources[0x2c]	364454	1			T1	25		T2	2821		T3	694
valid_sources[0x2d]	650151	1			T1	23		T2	2775		T3	902
valid_sources[0x2e]	360042	1			T1	20		T2	2944		T3	796
valid_sources[0x2f]	358571	1			T1	32		T2	3215		T3	831
valid_sources[0x30]	353302	1			T1	29		T2	3299		T3	805
valid_sources[0x31]	775365	1			T1	22		T2	3248		T3	825
valid_sources[0x32]	348977	1			T1	22		T2	2982		T3	846
valid_sources[0x33]	363282	1			T1	27		T2	3653		T3	779
valid_sources[0x34]	808638	1			T1	27		T2	3172		T3	880
valid_sources[0x35]	361164	1			T1	31		T2	3403		T3	773
valid_sources[0x36]	352690	1			T1	24		T2	3061		T3	798
valid_sources[0x37]	359878	1			T1	20		T2	3261		T3	742
valid_sources[0x38]	357660	1			T1	28		T2	3118		T3	874
valid_sources[0x39]	355039	1			T1	28		T2	3401		T3	840
valid_sources[0x3a]	353336	1			T1	35		T2	2945		T3	809
valid_sources[0x3b]	623862	1			T1	29		T2	2820		T3	904
valid_sources[0x3c]	357559	1			T1	28		T2	3535		T3	740
valid_sources[0x3d]	360325	1			T1	22		T2	2661		T3	712
valid_sources[0x3e]	591178	1			T1	39		T2	3803		T3	853
valid_sources[0x3f]	356424	1			T1	24		T2	3227		T3	769
valid_sources[0x40]	359960	1			T1	21		T2	2343		T3	1044
valid_sources[0x41]	357542	1			T1	27		T2	2303		T3	869
valid_sources[0x42]	353456	1			T1	32		T2	3368		T3	791
valid_sources[0x43]	352835	1			T1	19		T2	3558		T3	821
valid_sources[0x44]	355221	1			T1	18		T2	3232		T3	910
valid_sources[0x45]	356908	1			T1	22		T2	2849		T3	842
valid_sources[0x46]	358615	1			T1	19		T2	3707		T3	914
valid_sources[0x47]	354299	1			T1	27		T2	3263		T3	727
valid_sources[0x48]	371997	1			T1	31		T2	3065		T3	879
valid_sources[0x49]	358310	1			T1	28		T2	3296		T3	903
valid_sources[0x4a]	353238	1			T1	24		T2	2728		T3	843
valid_sources[0x4b]	361906	1			T1	28		T2	2607		T3	705
valid_sources[0x4c]	357142	1			T1	31		T2	3357		T3	741
valid_sources[0x4d]	362263	1			T1	22		T2	2675		T3	983
valid_sources[0x4e]	791496	1			T1	20		T2	2658		T3	956
valid_sources[0x4f]	380753	1			T1	41		T2	3379		T3	930
valid_sources[0x50]	393026	1			T1	14		T2	2874		T3	757
valid_sources[0x51]	354425	1			T1	23		T2	3418		T3	731
valid_sources[0x52]	363407	1			T1	35		T2	3167		T3	766
valid_sources[0x53]	349774	1			T1	28		T2	3465		T3	816
valid_sources[0x54]	357925	1			T1	28		T2	3338		T3	916
valid_sources[0x55]	378638	1			T1	21		T2	3387		T3	803
valid_sources[0x56]	392199	1			T1	34		T2	2515		T3	795
valid_sources[0x57]	728346	1			T1	38		T2	3294		T3	932
valid_sources[0x58]	359632	1			T1	15		T2	2925		T3	895
valid_sources[0x59]	361082	1			T1	31		T2	2784		T3	846
valid_sources[0x5a]	415843	1			T1	31		T2	3403		T3	829
valid_sources[0x5b]	361333	1			T1	11		T2	3920		T3	883
valid_sources[0x5c]	363983	1			T1	16		T2	2777		T3	927
valid_sources[0x5d]	351175	1			T1	19		T2	2433		T3	924
valid_sources[0x5e]	385057	1			T1	30		T2	3095		T3	858
valid_sources[0x5f]	357895	1			T1	28		T2	3215		T3	853
valid_sources[0x60]	553168	1			T1	28		T2	2696		T3	613
valid_sources[0x61]	363807	1			T1	25		T2	3333		T3	895
valid_sources[0x62]	355135	1			T1	40		T2	3438		T3	977
valid_sources[0x63]	353445	1			T1	37		T2	3644		T3	971
valid_sources[0x64]	355467	1			T1	30		T2	2981		T3	919
valid_sources[0x65]	365571	1			T1	30		T2	3139		T3	876
valid_sources[0x66]	375982	1			T1	23		T2	3130		T3	748
valid_sources[0x67]	383014	1			T1	38		T2	3582		T3	659
valid_sources[0x68]	365050	1			T1	26		T2	2841		T3	824
valid_sources[0x69]	358147	1			T1	27		T2	3665		T3	762
valid_sources[0x6a]	355656	1			T1	20		T2	2732		T3	989
valid_sources[0x6b]	691061	1			T1	36		T2	3783		T3	723
valid_sources[0x6c]	357949	1			T1	28		T2	2559		T3	885
valid_sources[0x6d]	353482	1			T1	28		T2	3269		T3	977
valid_sources[0x6e]	352644	1			T1	26		T2	2857		T3	886
valid_sources[0x6f]	357813	1			T1	29		T2	2380		T3	1112
valid_sources[0x70]	358900	1			T1	35		T2	3478		T3	945
valid_sources[0x71]	350877	1			T1	39		T2	2573		T3	796
valid_sources[0x72]	356642	1			T1	34		T2	3405		T3	994
valid_sources[0x73]	357310	1			T1	30		T2	3014		T3	777
valid_sources[0x74]	363425	1			T1	25		T2	3266		T3	718
valid_sources[0x75]	358935	1			T1	27		T2	2714		T3	932
valid_sources[0x76]	361038	1			T1	20		T2	2934		T3	750
valid_sources[0x77]	354448	1			T1	14		T2	2840		T3	752
valid_sources[0x78]	362286	1			T1	26		T2	2150		T3	765
valid_sources[0x79]	358613	1			T1	24		T2	3097		T3	785
valid_sources[0x7a]	349311	1			T1	20		T2	3195		T3	739
valid_sources[0x7b]	364313	1			T1	18		T2	2764		T3	815
valid_sources[0x7c]	361431	1			T1	30		T2	2699		T3	846
valid_sources[0x7d]	359379	1			T1	44		T2	3238		T3	916
valid_sources[0x7e]	351596	1			T1	33		T2	3507		T3	756
valid_sources[0x7f]	650360	1			T1	28		T2	2980		T3	831
valid_sources[0x80]	357011	1			T1	44		T2	2847		T3	880

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7946319

1

T1

563

T2

54659

T3

13140

values[0x0]

all_enables

biggest_size

16811081

1

T1

1075

T2

130821

T3

34437

values[0x1]

all_enables

biggest_size

9944012

1

T1

626

T2

79478

T3

19600