Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T188,T189
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14594	0	0
DisabledNoTrigBkwd_A	2147483647	885453	0	0
DisabledNoTrigFwd_A	2147483647	1671168877	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14594	0	0
T60	180902	0	0	0
T63	13743	0	0	0
T64	23036	0	0	0
T66	20371	0	0	0
T76	11947	0	0	0
T172	0	463	0	0
T187	0	454	0	0
T188	4753	1644	0	0
T189	5144	315	0	0
T190	3774	301	0	0
T191	0	514	0	0
T192	0	892	0	0
T193	0	1545	0	0
T194	0	463	0	0
T195	0	858	0	0
T196	0	641	0	0
T197	0	633	0	0
T198	0	505	0	0
T199	0	922	0	0
T200	0	976	0	0
T201	0	255	0	0
T202	0	793	0	0
T203	0	921	0	0
T204	0	827	0	0
T205	0	672	0	0
T206	586787	0	0	0
T207	315805	0	0	0
T208	455556	0	0	0
T209	49064	0	0	0
T210	1373	0	0	0
T211	109079	0	0	0
T212	563416	0	0	0
T213	246516	0	0	0
T214	145332	0	0	0
T215	135428	0	0	0
T216	231487	0	0	0
T217	515621	0	0	0
T218	291063	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	885453	0	0
T1	75927	75	0	0
T2	1241776	8145	0	0
T3	3388228	591	0	0
T4	1557388	5838	0	0
T5	1368576	1160	0	0
T12	574264	4817	0	0
T13	0	5743	0	0
T14	0	3982	0	0
T15	0	2	0	0
T16	0	1944	0	0
T18	59696	9	0	0
T19	1261160	353	0	0
T20	309184	26	0	0
T21	132100	2	0	0
T22	91299	23	0	0
T41	0	253	0	0
T42	0	4	0	0
T43	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1671168877	0	0
T1	303708	230254	0	0
T2	1241776	1650640	0	0
T3	3388228	1697592	0	0
T4	1557388	1938329	0	0
T5	1368576	433590	0	0
T12	574264	297571	0	0
T18	59696	33024	0	0
T19	1261160	2369142	0	0
T20	309184	236163	0	0
T21	132100	84768	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T191,T192
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	756152024	5244	0	0
DisabledNoTrigBkwd_A	756152024	274813	0	0
DisabledNoTrigFwd_A	756152024	371981522	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	5244	0	0
T76	11947	0	0	0
T190	3774	301	0	0
T191	0	514	0	0
T192	0	892	0	0
T194	0	463	0	0
T198	0	505	0	0
T200	0	976	0	0
T203	0	921	0	0
T205	0	672	0	0
T211	109079	0	0	0
T212	563416	0	0	0
T213	246516	0	0	0
T214	145332	0	0	0
T215	135428	0	0	0
T216	231487	0	0	0
T217	515621	0	0	0
T218	291063	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	274813	0	0
T1	75927	75	0	0
T2	310444	194	0	0
T3	847057	0	0	0
T4	389347	5548	0	0
T5	342144	0	0	0
T12	143566	1878	0	0
T13	0	5	0	0
T18	14924	0	0	0
T19	315290	114	0	0
T20	77296	22	0	0
T21	33025	0	0	0
T22	0	23	0	0
T42	0	2	0	0
T43	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	371981522	0	0
T1	75927	2719	0	0
T2	310444	266163	0	0
T3	847057	845676	0	0
T4	389347	919852	0	0
T5	342144	339832	0	0
T12	143566	6323	0	0
T18	14924	13121	0	0
T19	315290	276983	0	0
T20	77296	16831	0	0
T21	33025	31297	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T18
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T172,T193
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	756152024	4574	0	0
DisabledNoTrigBkwd_A	756152024	214193	0	0
DisabledNoTrigFwd_A	756152024	406851599	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	4574	0	0
T60	180902	0	0	0
T63	13743	0	0	0
T64	11518	0	0	0
T66	20371	0	0	0
T172	0	463	0	0
T188	4753	1644	0	0
T189	2572	0	0	0
T193	0	1545	0	0
T199	0	922	0	0
T206	586787	0	0	0
T207	315805	0	0	0
T208	227778	0	0	0
T209	24532	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	214193	0	0
T2	310444	3122	0	0
T3	847057	193	0	0
T4	389347	0	0	0
T5	342144	2	0	0
T12	143566	2916	0	0
T13	0	4136	0	0
T18	14924	3	0	0
T19	315290	42	0	0
T20	77296	4	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	83	0	0
T42	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	406851599	0	0
T1	75927	75845	0	0
T2	310444	193801	0	0
T3	847057	586	0	0
T4	389347	362807	0	0
T5	342144	36653	0	0
T12	143566	6162	0	0
T18	14924	1876	0	0
T19	315290	723970	0	0
T20	77296	64868	0	0
T21	33025	30364	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T197,T202
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	756152024	1741	0	0
DisabledNoTrigBkwd_A	756152024	200777	0	0
DisabledNoTrigFwd_A	756152024	435598926	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1741	0	0
T9	23598	0	0	0
T25	407732	0	0	0
T33	18545	0	0	0
T56	428501	0	0	0
T57	29755	0	0	0
T64	11518	0	0	0
T189	2572	315	0	0
T197	0	633	0	0
T202	0	793	0	0
T208	227778	0	0	0
T209	24532	0	0	0
T210	1373	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	200777	0	0
T2	310444	2862	0	0
T3	847057	398	0	0
T4	389347	151	0	0
T5	342144	613	0	0
T12	143566	11	0	0
T13	0	1596	0	0
T14	0	1845	0	0
T16	0	1944	0	0
T18	14924	0	0	0
T19	315290	115	0	0
T20	77296	0	0	0
T21	33025	2	0	0
T22	30433	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	435598926	0	0
T1	75927	75845	0	0
T2	310444	453797	0	0
T3	847057	4336	0	0
T4	389347	323436	0	0
T5	342144	14311	0	0
T12	143566	142798	0	0
T18	14924	14864	0	0
T19	315290	754978	0	0
T20	77296	77232	0	0
T21	33025	19843	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T195,T196
1	1	Covered	T2,T4,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	756152024	3035	0	0
DisabledNoTrigBkwd_A	756152024	195670	0	0
DisabledNoTrigFwd_A	756152024	456736830	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	3035	0	0
T60	180902	0	0	0
T63	13743	0	0	0
T64	11518	0	0	0
T66	20371	0	0	0
T187	3723	454	0	0
T188	4753	0	0	0
T189	2572	0	0	0
T195	0	858	0	0
T196	0	641	0	0
T201	0	255	0	0
T204	0	827	0	0
T206	586787	0	0	0
T207	315805	0	0	0
T219	159487	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	195670	0	0
T2	310444	1967	0	0
T3	847057	0	0	0
T4	389347	139	0	0
T5	342144	545	0	0
T12	143566	12	0	0
T13	0	6	0	0
T14	0	2137	0	0
T15	0	2	0	0
T18	14924	6	0	0
T19	315290	82	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	170	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	456736830	0	0
T1	75927	75845	0	0
T2	310444	736879	0	0
T3	847057	846994	0	0
T4	389347	332234	0	0
T5	342144	42794	0	0
T12	143566	142288	0	0
T18	14924	3163	0	0
T19	315290	613211	0	0
T20	77296	77232	0	0
T21	33025	3264	0	0