Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T18
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T4,T18
1	1	1	Covered	T2,T4,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T18
0	1	Covered	T4,T18,T19
1	0	Covered	T19,T22,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T22,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T25
1	1	Covered	T4,T18,T19

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T19

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T2,T4,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T2,T4,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T12,T15,T26
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T20,T27,T26
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T19,T26,T28
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T26,T29,T30
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T4,T18
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T2,T4,T18
TimeoutSt->Phase0St	167	Covered	T4,T18,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T12,T15
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T27,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T26,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	989	0	0
CheckAccumTrig0_A	2147483647	2488	0	0
CheckAccumTrig1_A	2147483647	109	0	0
CheckClr_A	2147483647	1144	0	0
CheckEn_A	2147483647	1254540975	0	0
CheckPhase0_A	2147483647	2829	0	0
CheckPhase1_A	2147483647	2780	0	0
CheckPhase2_A	2147483647	2731	0	0
CheckPhase3_A	2147483647	2683	0	0
CheckTimeout0_A	2147483647	6870	0	0
CheckTimeoutSt1_A	2147483647	687773	0	0
CheckTimeoutSt2_A	2147483647	6485	0	0
CheckTimeoutStTrig_A	2147483647	266	0	0
ErrorStAllEscAsserted_A	2147483647	5111	0	0
ErrorStIsTerminal_A	2147483647	4271	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	989	0	0
T7	1492436	0	0	0
T9	94392	161	0	0
T10	0	119	0	0
T11	0	146	0	0
T31	0	270	0	0
T32	0	293	0	0
T33	74180	0	0	0
T34	148332	0	0	0
T35	227912	0	0	0
T36	3903324	0	0	0
T37	1777840	0	0	0
T38	17904	0	0	0
T39	65808	0	0	0
T40	1805312	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T1	75927	1	0	0
T2	1241776	18	0	0
T3	3388228	2	0	0
T4	1557388	10	0	0
T5	1368576	3	0	0
T12	574264	5	0	0
T13	0	10	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	59696	2	0	0
T19	1261160	27	0	0
T20	309184	4	0	0
T21	132100	1	0	0
T22	91299	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109	0	0
T7	373109	0	0	0
T9	23598	0	0	0
T12	430698	0	0	0
T13	741900	0	0	0
T14	418680	0	0	0
T19	945870	4	0	0
T20	231888	0	0	0
T21	99075	0	0	0
T22	91299	1	0	0
T24	0	1	0	0
T25	407732	0	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	1295934	0	0	0
T42	72564	0	0	0
T43	324246	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	428501	0	0	0
T57	29755	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T2	1241776	5	0	0
T3	3388228	0	0	0
T4	1557388	3	0	0
T5	1368576	0	0	0
T12	574264	1	0	0
T13	0	7	0	0
T15	0	2	0	0
T17	0	5	0	0
T18	59696	3	0	0
T19	1261160	25	0	0
T20	309184	3	0	0
T21	132100	0	0	0
T22	121732	1	0	0
T24	0	3	0	0
T26	0	5	0	0
T28	0	4	0	0
T29	0	1	0	0
T30	0	3	0	0
T42	0	2	0	0
T44	0	10	0	0
T58	0	4	0	0
T59	0	1	0	0
T60	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1254540975	0	0
T1	303708	230251	0	0
T2	1241776	1642645	0	0
T3	3388228	1697590	0	0
T4	1557388	1925886	0	0
T5	1368576	422241	0	0
T12	574264	18894	0	0
T18	59696	29217	0	0
T19	1261160	2176985	0	0
T20	309184	236160	0	0
T21	132100	78238	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2829	0	0
T1	75927	1	0	0
T2	1241776	18	0	0
T3	3388228	2	0	0
T4	1557388	12	0	0
T5	1368576	3	0	0
T12	574264	4	0	0
T13	0	9	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	59696	3	0	0
T19	1261160	42	0	0
T20	309184	4	0	0
T21	132100	1	0	0
T22	91299	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2780	0	0
T1	75927	1	0	0
T2	1241776	18	0	0
T3	3388228	2	0	0
T4	1557388	12	0	0
T5	1368576	3	0	0
T12	574264	4	0	0
T13	0	11	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	59696	3	0	0
T19	1261160	42	0	0
T20	309184	1	0	0
T21	132100	1	0	0
T22	91299	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2731	0	0
T1	75927	1	0	0
T2	1241776	18	0	0
T3	3388228	2	0	0
T4	1557388	12	0	0
T5	1368576	3	0	0
T12	574264	4	0	0
T13	0	11	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	59696	3	0	0
T19	1261160	39	0	0
T20	309184	1	0	0
T21	132100	1	0	0
T22	91299	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2683	0	0
T1	75927	1	0	0
T2	1241776	18	0	0
T3	3388228	2	0	0
T4	1557388	12	0	0
T5	1368576	3	0	0
T12	574264	4	0	0
T13	0	11	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	59696	3	0	0
T19	1261160	39	0	0
T20	309184	1	0	0
T21	132100	1	0	0
T22	91299	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6870	0	0
T2	1241776	12	0	0
T3	3388228	0	0	0
T4	1557388	89	0	0
T5	1368576	0	0	0
T12	574264	0	0	0
T13	0	4	0	0
T18	59696	3	0	0
T19	1261160	444	0	0
T20	309184	1	0	0
T21	132100	0	0	0
T22	121732	1	0	0
T24	0	2	0	0
T25	0	483	0	0
T26	0	23	0	0
T27	0	2	0	0
T28	0	5	0	0
T29	0	2	0	0
T44	0	6	0	0
T58	0	2	0	0
T59	0	21	0	0
T61	0	9	0	0
T62	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	687773	0	0
T2	1241776	2057	0	0
T3	3388228	0	0	0
T4	1557388	5427	0	0
T5	1368576	0	0	0
T12	574264	0	0	0
T13	0	675	0	0
T18	59696	701	0	0
T19	1261160	62440	0	0
T20	309184	145	0	0
T21	132100	0	0	0
T22	121732	0	0	0
T24	0	155	0	0
T25	0	49100	0	0
T26	0	4251	0	0
T27	0	116	0	0
T28	0	208	0	0
T29	0	263	0	0
T44	0	671	0	0
T58	0	376	0	0
T59	0	3435	0	0
T61	0	2432	0	0
T62	0	70	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6485	0	0
T2	1241776	12	0	0
T3	3388228	0	0	0
T4	1557388	87	0	0
T5	1368576	0	0	0
T12	574264	0	0	0
T13	0	3	0	0
T18	59696	2	0	0
T19	1261160	428	0	0
T20	309184	1	0	0
T21	132100	0	0	0
T22	121732	0	0	0
T25	0	1186	0	0
T26	0	16	0	0
T27	0	1	0	0
T28	0	3	0	0
T29	0	2	0	0
T40	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T58	0	2	0	0
T59	0	19	0	0
T61	0	18	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	266	0	0
T4	778694	1	0	0
T5	684288	0	0	0
T12	574264	0	0	0
T13	494600	1	0	0
T14	279120	0	0	0
T18	29848	1	0	0
T19	1261160	5	0	0
T20	309184	0	0	0
T21	132100	0	0	0
T22	121732	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T41	1727912	0	0	0
T42	96752	0	0	0
T43	216164	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	1	0	0
T59	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5111	0	0
T7	1492436	0	0	0
T9	94392	733	0	0
T10	0	728	0	0
T11	0	742	0	0
T31	0	1474	0	0
T32	0	1434	0	0
T33	74180	0	0	0
T34	148332	0	0	0
T35	227912	0	0	0
T36	3903324	0	0	0
T37	1777840	0	0	0
T38	17904	0	0	0
T39	65808	0	0	0
T40	1805312	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4271	0	0
T7	1492436	0	0	0
T9	94392	613	0	0
T10	0	608	0	0
T11	0	622	0	0
T31	0	1234	0	0
T32	0	1194	0	0
T33	74180	0	0	0
T34	148332	0	0	0
T35	227912	0	0	0
T36	3903324	0	0	0
T37	1777840	0	0	0
T38	17904	0	0	0
T39	65808	0	0	0
T40	1805312	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	303708	303380	0	0
T2	1241776	1241736	0	0
T3	3388228	3387976	0	0
T4	1557388	1557144	0	0
T5	1368576	1368540	0	0
T12	574264	574228	0	0
T18	59696	59456	0	0
T19	1261160	1260856	0	0
T20	309184	308928	0	0
T21	132100	131876	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T18
1	0	1	Covered	T2,T4,T14
1	1	0	Covered	T2,T4,T18
1	1	1	Covered	T2,T4,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T19
0	1	Covered	T19,T28,T46
1	0	Covered	T19,T22,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T22,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T19
1	0	Not Covered
1	1	Covered	T19,T28,T46

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T1,T2,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T19,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T4
Phase1St	193	Covered	T1,T2,T4
Phase2St	210	Covered	T1,T2,T4
Phase3St	228	Covered	T1,T2,T4
TerminalSt	244	Covered	T1,T2,T4
TimeoutSt	154	Covered	T2,T4,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T4
IdleSt->TimeoutSt	154	Covered	T2,T4,T19
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T12,T26,T75
Phase0St->Phase1St	193	Covered	T1,T2,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T20,T27,T26
Phase1St->Phase2St	210	Covered	T1,T2,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T76,T77
Phase2St->Phase3St	228	Covered	T1,T2,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T29,T78,T75
Phase3St->TerminalSt	244	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T4,T19
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T4,T19
TimeoutSt->Phase0St	167	Covered	T19,T22,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T22,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T26,T75
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T27,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T76,T77
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T78,T75
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	756152024	270	0	0
CheckAccumTrig0_A	756152024	872	0	0
CheckAccumTrig1_A	756152024	42	0	0
CheckClr_A	756152024	404	0	0
CheckEn_A	755979266	262792351	0	0
CheckPhase0_A	756152024	958	0	0
CheckPhase1_A	756152024	933	0	0
CheckPhase2_A	756152024	912	0	0
CheckPhase3_A	756152024	890	0	0
CheckTimeout0_A	756152024	1464	0	0
CheckTimeoutSt1_A	756152024	149228	0	0
CheckTimeoutSt2_A	756152024	1364	0	0
CheckTimeoutStTrig_A	756152024	56	0	0
ErrorStAllEscAsserted_A	756152024	1293	0	0
ErrorStIsTerminal_A	756152024	1083	0	0
u_state_regs_A	756152024	755992484	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	270	0	0
T7	373109	0	0	0
T9	23598	46	0	0
T10	0	16	0	0
T11	0	26	0	0
T31	0	87	0	0
T32	0	95	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	872	0	0
T1	75927	1	0	0
T2	310444	6	0	0
T3	847057	0	0	0
T4	389347	5	0	0
T5	342144	0	0	0
T12	143566	2	0	0
T13	0	1	0	0
T18	14924	0	0	0
T19	315290	7	0	0
T20	77296	2	0	0
T21	33025	0	0	0
T22	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	42	0	0
T12	143566	0	0	0
T13	247300	0	0	0
T14	139560	0	0	0
T19	315290	1	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T43	108082	0	0	0
T44	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	404	0	0
T2	310444	2	0	0
T3	847057	0	0	0
T4	389347	3	0	0
T5	342144	0	0	0
T12	143566	1	0	0
T17	0	2	0	0
T18	14924	0	0	0
T19	315290	4	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	30433	1	0	0
T24	0	1	0	0
T42	0	1	0	0
T58	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755979266	262792351	0	0
T1	75927	2719	0	0
T2	310444	108514	0	0
T3	847057	845675	0	0
T4	389347	916612	0	0
T5	342144	339832	0	0
T12	143566	6323	0	0
T18	14924	13120	0	0
T19	315290	266088	0	0
T20	77296	16831	0	0
T21	33025	31296	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	958	0	0
T1	75927	1	0	0
T2	310444	6	0	0
T3	847057	0	0	0
T4	389347	5	0	0
T5	342144	0	0	0
T12	143566	1	0	0
T13	0	1	0	0
T18	14924	0	0	0
T19	315290	9	0	0
T20	77296	2	0	0
T21	33025	0	0	0
T22	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	933	0	0
T1	75927	1	0	0
T2	310444	6	0	0
T3	847057	0	0	0
T4	389347	5	0	0
T5	342144	0	0	0
T12	143566	1	0	0
T13	0	1	0	0
T18	14924	0	0	0
T19	315290	9	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	912	0	0
T1	75927	1	0	0
T2	310444	6	0	0
T3	847057	0	0	0
T4	389347	5	0	0
T5	342144	0	0	0
T12	143566	1	0	0
T13	0	1	0	0
T18	14924	0	0	0
T19	315290	9	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	890	0	0
T1	75927	1	0	0
T2	310444	6	0	0
T3	847057	0	0	0
T4	389347	5	0	0
T5	342144	0	0	0
T12	143566	1	0	0
T13	0	1	0	0
T18	14924	0	0	0
T19	315290	9	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1464	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	4	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	4	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	30433	1	0	0
T24	0	1	0	0
T26	0	6	0	0
T27	0	2	0	0
T28	0	2	0	0
T44	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	149228	0	0
T2	310444	596	0	0
T3	847057	0	0	0
T4	389347	336	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	583	0	0
T20	77296	145	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	1	0	0
T26	0	1087	0	0
T27	0	116	0	0
T28	0	24	0	0
T44	0	35	0	0
T61	0	1281	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1364	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	4	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	2	0	0
T20	77296	1	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	4	0	0
T27	0	1	0	0
T29	0	1	0	0
T61	0	10	0	0
T63	0	1	0	0
T64	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	56	0	0
T12	143566	0	0	0
T13	247300	0	0	0
T14	139560	0	0	0
T19	315290	1	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T28	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T43	108082	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1293	0	0
T7	373109	0	0	0
T9	23598	186	0	0
T10	0	161	0	0
T11	0	184	0	0
T31	0	400	0	0
T32	0	362	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1083	0	0
T7	373109	0	0	0
T9	23598	156	0	0
T10	0	131	0	0
T11	0	154	0	0
T31	0	340	0	0
T32	0	302	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	755992484	0	0
T1	75927	75845	0	0
T2	310444	310434	0	0
T3	847057	846994	0	0
T4	389347	389286	0	0
T5	342144	342135	0	0
T12	143566	143557	0	0
T18	14924	14864	0	0
T19	315290	315214	0	0
T20	77296	77232	0	0
T21	33025	32969	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T19
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T4,T18
1	1	1	Covered	T2,T4,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T19
0	1	Covered	T19,T44,T59
1	0	Covered	T19,T26,T40

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T26,T40

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T19
1	0	Not Covered
1	1	Covered	T19,T44,T59

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T21,T14

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T2,T3,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T19,T12

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T19

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T2,T4,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T2,T4,T19
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T28,T79,T77
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T80,T74,T81
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T19,T26,T29
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T30,T82,T83
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T4,T19
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T4,T19
TimeoutSt->Phase0St	167	Covered	T19,T26,T44

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T26,T44
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T79,T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T80,T74,T81
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T26,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T82,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	756152024	247	0	0
CheckAccumTrig0_A	756152024	523	0	0
CheckAccumTrig1_A	756152024	20	0	0
CheckClr_A	756152024	223	0	0
CheckEn_A	755979266	322445793	0	0
CheckPhase0_A	756152024	607	0	0
CheckPhase1_A	756152024	601	0	0
CheckPhase2_A	756152024	590	0	0
CheckPhase3_A	756152024	586	0	0
CheckTimeout0_A	756152024	1469	0	0
CheckTimeoutSt1_A	756152024	151438	0	0
CheckTimeoutSt2_A	756152024	1376	0	0
CheckTimeoutStTrig_A	756152024	71	0	0
ErrorStAllEscAsserted_A	756152024	1276	0	0
ErrorStIsTerminal_A	756152024	1066	0	0
u_state_regs_A	756152024	755992484	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	247	0	0
T7	373109	0	0	0
T9	23598	53	0	0
T10	0	16	0	0
T11	0	40	0	0
T31	0	63	0	0
T32	0	75	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	523	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	7	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	14924	0	0	0
T19	315290	8	0	0
T20	77296	0	0	0
T21	33025	1	0	0
T22	30433	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	20	0	0
T12	143566	0	0	0
T13	247300	0	0	0
T14	139560	0	0	0
T19	315290	2	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	1	0	0
T40	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T43	108082	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	223	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	0	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	6	0	0
T18	14924	0	0	0
T19	315290	10	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T28	0	3	0	0
T29	0	1	0	0
T30	0	3	0	0
T44	0	3	0	0
T60	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755979266	322445793	0	0
T1	75927	75844	0	0
T2	310444	445847	0	0
T3	847057	4336	0	0
T4	389347	319888	0	0
T5	342144	14311	0	0
T12	143566	6829	0	0
T18	14924	14863	0	0
T19	315290	754971	0	0
T20	77296	77231	0	0
T21	33025	13315	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	607	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	7	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	14924	0	0	0
T19	315290	13	0	0
T20	77296	0	0	0
T21	33025	1	0	0
T22	30433	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	601	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	7	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	14924	0	0	0
T19	315290	13	0	0
T20	77296	0	0	0
T21	33025	1	0	0
T22	30433	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	590	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	7	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	14924	0	0	0
T19	315290	11	0	0
T20	77296	0	0	0
T21	33025	1	0	0
T22	30433	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	586	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	7	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	14924	0	0	0
T19	315290	11	0	0
T20	77296	0	0	0
T21	33025	1	0	0
T22	30433	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1469	0	0
T2	310444	2	0	0
T3	847057	0	0	0
T4	389347	27	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	204	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	259	0	0
T26	0	5	0	0
T28	0	2	0	0
T44	0	4	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	151438	0	0
T2	310444	85	0	0
T3	847057	0	0	0
T4	389347	1114	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	29426	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	26739	0	0
T26	0	958	0	0
T28	0	119	0	0
T44	0	636	0	0
T59	0	27	0	0
T61	0	136	0	0
T62	0	70	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1376	0	0
T2	310444	2	0	0
T3	847057	0	0	0
T4	389347	27	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	199	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	258	0	0
T26	0	4	0	0
T28	0	2	0	0
T40	0	1	0	0
T44	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	71	0	0
T12	143566	0	0	0
T13	247300	0	0	0
T14	139560	0	0	0
T19	315290	3	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T43	108082	0	0	0
T44	0	2	0	0
T46	0	3	0	0
T59	0	1	0	0
T65	0	1	0	0
T79	0	3	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1276	0	0
T7	373109	0	0	0
T9	23598	193	0	0
T10	0	170	0	0
T11	0	187	0	0
T31	0	358	0	0
T32	0	368	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1066	0	0
T7	373109	0	0	0
T9	23598	163	0	0
T10	0	140	0	0
T11	0	157	0	0
T31	0	298	0	0
T32	0	308	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	755992484	0	0
T1	75927	75845	0	0
T2	310444	310434	0	0
T3	847057	846994	0	0
T4	389347	389286	0	0
T5	342144	342135	0	0
T12	143566	143557	0	0
T18	14924	14864	0	0
T19	315290	315214	0	0
T20	77296	77232	0	0
T21	33025	32969	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T18
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T4,T19
1	1	1	Covered	T2,T4,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T18
0	1	Covered	T4,T18,T19
1	0	Covered	T19,T46,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T46,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T25
1	1	Covered	T4,T18,T19

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T2,T3,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T2,T4,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T19,T42,T13

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T41,T26

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T18,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T18,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T2,T4,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T5
IdleSt->TimeoutSt	154	Covered	T2,T4,T18
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T15,T29,T92
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T20,T93,T94
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T95,T96,T97
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T26,T98,T75
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T4,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T4,T18
TimeoutSt->Phase0St	167	Covered	T4,T18,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T29,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T93,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T95,T96,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T98,T75
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	756152024	204	0	0
CheckAccumTrig0_A	756152024	532	0	0
CheckAccumTrig1_A	756152024	20	0	0
CheckClr_A	756152024	241	0	0
CheckEn_A	755979266	339124461	0	0
CheckPhase0_A	756152024	621	0	0
CheckPhase1_A	756152024	612	0	0
CheckPhase2_A	756152024	608	0	0
CheckPhase3_A	756152024	599	0	0
CheckTimeout0_A	756152024	2379	0	0
CheckTimeoutSt1_A	756152024	216239	0	0
CheckTimeoutSt2_A	756152024	2280	0	0
CheckTimeoutStTrig_A	756152024	76	0	0
ErrorStAllEscAsserted_A	756152024	1241	0	0
ErrorStIsTerminal_A	756152024	1031	0	0
u_state_regs_A	756152024	755992484	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	204	0	0
T7	373109	0	0	0
T9	23598	32	0	0
T10	0	35	0	0
T11	0	36	0	0
T31	0	47	0	0
T32	0	54	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	532	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	0	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	14924	0	0	0
T19	315290	5	0	0
T20	77296	2	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	20	0	0
T12	143566	0	0	0
T13	247300	0	0	0
T14	139560	0	0	0
T19	315290	1	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T43	108082	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	241	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	0	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	0	3	0	0
T18	14924	1	0	0
T19	315290	4	0	0
T20	77296	2	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	2	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755979266	339124461	0	0
T1	75927	75844	0	0
T2	310444	642003	0	0
T3	847057	586	0	0
T4	389347	361507	0	0
T5	342144	36653	0	0
T12	143566	4015	0	0
T18	14924	613	0	0
T19	315290	723964	0	0
T20	77296	64867	0	0
T21	33025	30363	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	621	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	1	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T18	14924	1	0	0
T19	315290	7	0	0
T20	77296	2	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	612	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	1	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	2	0	0
T18	14924	1	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	608	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	1	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	2	0	0
T18	14924	1	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	599	0	0
T2	310444	4	0	0
T3	847057	1	0	0
T4	389347	1	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	2	0	0
T18	14924	1	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	2379	0	0
T2	310444	8	0	0
T3	847057	0	0	0
T4	389347	30	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	4	0	0
T18	14924	3	0	0
T19	315290	226	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	8	0	0
T28	0	1	0	0
T29	0	1	0	0
T59	0	14	0	0
T61	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	216239	0	0
T2	310444	1302	0	0
T3	847057	0	0	0
T4	389347	1824	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	675	0	0
T18	14924	701	0	0
T19	315290	30340	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	1422	0	0
T28	0	65	0	0
T29	0	84	0	0
T59	0	2204	0	0
T61	0	952	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	2280	0	0
T2	310444	8	0	0
T3	847057	0	0	0
T4	389347	29	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	3	0	0
T18	14924	2	0	0
T19	315290	224	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	706	0	0
T26	0	5	0	0
T28	0	1	0	0
T59	0	14	0	0
T61	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	76	0	0
T4	389347	1	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T13	0	1	0	0
T18	14924	1	0	0
T19	315290	1	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T26	0	2	0	0
T29	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T45	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1241	0	0
T7	373109	0	0	0
T9	23598	179	0	0
T10	0	193	0	0
T11	0	186	0	0
T31	0	338	0	0
T32	0	345	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1031	0	0
T7	373109	0	0	0
T9	23598	149	0	0
T10	0	163	0	0
T11	0	156	0	0
T31	0	278	0	0
T32	0	285	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	755992484	0	0
T1	75927	75845	0	0
T2	310444	310434	0	0
T3	847057	846994	0	0
T4	389347	389286	0	0
T5	342144	342135	0	0
T12	143566	143557	0	0
T18	14924	14864	0	0
T19	315290	315214	0	0
T20	77296	77232	0	0
T21	33025	32969	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T2,T4,T18

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T18
1	0	1	Covered	T4,T5,T21
1	1	0	Covered	T2,T4,T19
1	1	1	Covered	T2,T4,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T19
0	1	Covered	T4,T19,T24
1	0	Covered	T58,T25,T78

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T58,T25,T78

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T19
1	0	Not Covered
1	1	Covered	T4,T19,T24

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T2,T19,T15

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T2,T4,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T2,T4,T18

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T18
1	Covered	T4,T5,T12

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T18,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T18
Phase1St	193	Covered	T2,T4,T18
Phase2St	210	Covered	T2,T4,T18
Phase3St	228	Covered	T2,T4,T18
TerminalSt	244	Covered	T2,T4,T18
TimeoutSt	154	Covered	T2,T4,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T4,T18
IdleSt->TimeoutSt	154	Covered	T2,T4,T19
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T19,T26,T99
Phase0St->Phase1St	193	Covered	T2,T4,T18
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T75,T100,T23
Phase1St->Phase2St	210	Covered	T2,T4,T18
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T19,T101,T75
Phase2St->Phase3St	228	Covered	T2,T4,T18
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T102,T99,T103
Phase3St->TerminalSt	244	Covered	T2,T4,T18
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T4,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T4,T19
TimeoutSt->Phase0St	167	Covered	T4,T19,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T19,T58
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T26,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T75,T100,T23
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T101,T75
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T102,T99,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	756152024	268	0	0
CheckAccumTrig0_A	756152024	561	0	0
CheckAccumTrig1_A	756152024	27	0	0
CheckClr_A	756152024	276	0	0
CheckEn_A	755979266	330178370	0	0
CheckPhase0_A	756152024	643	0	0
CheckPhase1_A	756152024	634	0	0
CheckPhase2_A	756152024	621	0	0
CheckPhase3_A	756152024	608	0	0
CheckTimeout0_A	756152024	1558	0	0
CheckTimeoutSt1_A	756152024	170868	0	0
CheckTimeoutSt2_A	756152024	1465	0	0
CheckTimeoutStTrig_A	756152024	63	0	0
ErrorStAllEscAsserted_A	756152024	1301	0	0
ErrorStIsTerminal_A	756152024	1091	0	0
u_state_regs_A	756152024	755992484	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	268	0	0
T7	373109	0	0	0
T9	23598	30	0	0
T10	0	52	0	0
T11	0	44	0	0
T31	0	73	0	0
T32	0	69	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	561	0	0
T2	310444	4	0	0
T3	847057	0	0	0
T4	389347	2	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	14924	2	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	27	0	0
T7	373109	0	0	0
T9	23598	0	0	0
T25	407732	1	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T56	428501	0	0	0
T57	29755	0	0	0
T75	0	2	0	0
T78	0	1	0	0
T94	0	1	0	0
T98	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	276	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	0	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	2	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	1	0	0
T26	0	2	0	0
T28	0	1	0	0
T44	0	3	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755979266	330178370	0	0
T1	75927	75844	0	0
T2	310444	446281	0	0
T3	847057	846993	0	0
T4	389347	327879	0	0
T5	342144	31445	0	0
T12	143566	1727	0	0
T18	14924	621	0	0
T19	315290	431962	0	0
T20	77296	77231	0	0
T21	33025	3264	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	643	0	0
T2	310444	4	0	0
T3	847057	0	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	14924	2	0	0
T19	315290	13	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	634	0	0
T2	310444	4	0	0
T3	847057	0	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	14924	2	0	0
T19	315290	13	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	621	0	0
T2	310444	4	0	0
T3	847057	0	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	14924	2	0	0
T19	315290	12	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	608	0	0
T2	310444	4	0	0
T3	847057	0	0	0
T4	389347	3	0	0
T5	342144	1	0	0
T12	143566	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	14924	2	0	0
T19	315290	12	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1558	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	28	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	10	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	1	0	0
T25	0	224	0	0
T26	0	4	0	0
T29	0	1	0	0
T58	0	2	0	0
T59	0	6	0	0
T61	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	170868	0	0
T2	310444	74	0	0
T3	847057	0	0	0
T4	389347	2153	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	2091	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	154	0	0
T25	0	22361	0	0
T26	0	784	0	0
T29	0	179	0	0
T58	0	376	0	0
T59	0	1204	0	0
T61	0	63	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1465	0	0
T2	310444	1	0	0
T3	847057	0	0	0
T4	389347	27	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	3	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T25	0	222	0	0
T26	0	3	0	0
T29	0	1	0	0
T45	0	1	0	0
T58	0	2	0	0
T59	0	5	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	63	0	0
T4	389347	1	0	0
T5	342144	0	0	0
T12	143566	0	0	0
T18	14924	0	0	0
T19	315290	7	0	0
T20	77296	0	0	0
T21	33025	0	0	0
T22	30433	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T41	431978	0	0	0
T42	24188	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T65	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1301	0	0
T7	373109	0	0	0
T9	23598	175	0	0
T10	0	204	0	0
T11	0	185	0	0
T31	0	378	0	0
T32	0	359	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	1091	0	0
T7	373109	0	0	0
T9	23598	145	0	0
T10	0	174	0	0
T11	0	155	0	0
T31	0	318	0	0
T32	0	299	0	0
T33	18545	0	0	0
T34	37083	0	0	0
T35	56978	0	0	0
T36	975831	0	0	0
T37	444460	0	0	0
T38	4476	0	0	0
T39	16452	0	0	0
T40	451328	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756152024	755992484	0	0
T1	75927	75845	0	0
T2	310444	310434	0	0
T3	847057	846994	0	0
T4	389347	389286	0	0
T5	342144	342135	0	0
T12	143566	143557	0	0
T18	14924	14864	0	0
T19	315290	315214	0	0
T20	77296	77232	0	0
T21	33025	32969	0	0