Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61083896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29372335

1

T1

129887

T2

2068

T3

117956

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13662824	1			T1	51206		T2	796		T3	46119
values[0x0]	37686094	1			T1	179242		T2	3046		T3	163579
values[0x1]	39107313	1			T1	179582		T2	3138		T3	162837

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52453750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38002481

1

T1

164220

T2

2694

T3

149027

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	289282	1			T3	1438		T4	1737		T12	1934
valid_sources[0x01]	681895	1			T2	168		T3	1515		T4	1385
valid_sources[0x02]	289236	1			T3	1418		T4	1827		T12	1832
valid_sources[0x03]	298594	1			T3	1428		T4	1421		T12	1834
valid_sources[0x04]	336994	1			T3	1393		T4	1632		T12	1859
valid_sources[0x05]	281799	1			T3	1449		T4	1422		T12	1876
valid_sources[0x06]	713991	1			T3	1444		T4	1649		T12	1868
valid_sources[0x07]	650870	1			T3	1493		T4	1771		T12	1905
valid_sources[0x08]	290504	1			T3	1472		T4	1983		T12	1768
valid_sources[0x09]	283703	1			T3	1417		T4	1806		T12	1831
valid_sources[0x0a]	289024	1			T2	23		T3	1456		T4	1832
valid_sources[0x0b]	285466	1			T3	1407		T4	1558		T12	1807
valid_sources[0x0c]	684523	1			T1	410030		T3	1498		T4	1333
valid_sources[0x0d]	277163	1			T3	1494		T4	1703		T12	1899
valid_sources[0x0e]	286366	1			T2	30		T3	1463		T4	1911
valid_sources[0x0f]	284427	1			T2	25		T3	1408		T4	1601
valid_sources[0x10]	287175	1			T3	1421		T4	1519		T12	1869
valid_sources[0x11]	279561	1			T3	1515		T4	1754		T12	1890
valid_sources[0x12]	704301	1			T3	1542		T4	1582		T12	1931
valid_sources[0x13]	281484	1			T3	1437		T4	1914		T12	1919
valid_sources[0x14]	294507	1			T3	1436		T4	1761		T12	1803
valid_sources[0x15]	499190	1			T3	1368		T4	1456		T12	1823
valid_sources[0x16]	291435	1			T2	76		T3	1495		T4	1745
valid_sources[0x17]	286981	1			T3	1511		T4	1549		T12	1878
valid_sources[0x18]	294866	1			T3	1463		T4	1313		T12	1807
valid_sources[0x19]	282557	1			T3	1472		T4	2241		T12	2004
valid_sources[0x1a]	288188	1			T2	3		T3	1419		T4	1880
valid_sources[0x1b]	290285	1			T3	1437		T4	1486		T12	1907
valid_sources[0x1c]	285348	1			T2	268		T3	1390		T4	1480
valid_sources[0x1d]	285497	1			T3	1373		T4	1909		T12	1943
valid_sources[0x1e]	295186	1			T3	1525		T4	2106		T12	1886
valid_sources[0x1f]	293808	1			T3	1476		T4	1846		T12	1942
valid_sources[0x20]	296557	1			T3	1476		T4	1994		T12	1887
valid_sources[0x21]	289552	1			T3	1469		T4	1351		T12	1894
valid_sources[0x22]	288614	1			T3	1497		T4	1921		T12	1945
valid_sources[0x23]	285242	1			T2	34		T3	1462		T4	2048
valid_sources[0x24]	293010	1			T3	1498		T4	1795		T12	1777
valid_sources[0x25]	284722	1			T3	1505		T4	1921		T12	1923
valid_sources[0x26]	290501	1			T2	183		T3	1457		T4	1952
valid_sources[0x27]	285696	1			T3	1427		T4	1674		T12	1918
valid_sources[0x28]	287510	1			T3	1479		T4	2041		T12	1959
valid_sources[0x29]	290225	1			T3	1380		T4	1567		T12	1783
valid_sources[0x2a]	294121	1			T2	113		T3	1463		T4	1746
valid_sources[0x2b]	284481	1			T3	1383		T4	1776		T12	1904
valid_sources[0x2c]	294920	1			T3	1406		T4	1858		T12	1879
valid_sources[0x2d]	282015	1			T3	1540		T4	1647		T12	1908
valid_sources[0x2e]	281621	1			T2	57		T3	1475		T4	1979
valid_sources[0x2f]	283008	1			T2	33		T3	1464		T4	1759
valid_sources[0x30]	280638	1			T3	1344		T4	1592		T12	1834
valid_sources[0x31]	287374	1			T2	40		T3	1439		T4	1766
valid_sources[0x32]	285730	1			T3	1429		T4	1495		T12	1798
valid_sources[0x33]	293409	1			T3	1464		T4	1858		T12	1833
valid_sources[0x34]	297813	1			T3	1548		T4	1471		T12	1891
valid_sources[0x35]	586236	1			T2	227		T3	1337		T4	1921
valid_sources[0x36]	284398	1			T3	1383		T4	1678		T12	1872
valid_sources[0x37]	294208	1			T3	1457		T4	1656		T12	1885
valid_sources[0x38]	292245	1			T3	1515		T4	1897		T12	1859
valid_sources[0x39]	282298	1			T2	31		T3	1411		T4	1702
valid_sources[0x3a]	513497	1			T2	601		T3	1410		T4	1618
valid_sources[0x3b]	284780	1			T2	543		T3	1403		T4	1885
valid_sources[0x3c]	283786	1			T3	1413		T4	1691		T12	1842
valid_sources[0x3d]	279641	1			T2	35		T3	1440		T4	1616
valid_sources[0x3e]	282556	1			T3	1411		T4	1596		T12	1879
valid_sources[0x3f]	304463	1			T3	1374		T4	1875		T12	1836
valid_sources[0x40]	287921	1			T3	1470		T4	1744		T12	1795
valid_sources[0x41]	666959	1			T3	1427		T4	1817		T12	1881
valid_sources[0x42]	292839	1			T3	1509		T4	1861		T12	1843
valid_sources[0x43]	305747	1			T3	1393		T4	1865		T12	1905
valid_sources[0x44]	555357	1			T3	1469		T4	1837		T12	1873
valid_sources[0x45]	278388	1			T3	1468		T4	1851		T12	1912
valid_sources[0x46]	287248	1			T3	1458		T4	1844		T12	1986
valid_sources[0x47]	293676	1			T3	1553		T4	1705		T12	1909
valid_sources[0x48]	287708	1			T3	1472		T4	1633		T12	1884
valid_sources[0x49]	290316	1			T3	1442		T4	1886		T12	1877
valid_sources[0x4a]	288599	1			T3	1514		T4	1697		T12	1893
valid_sources[0x4b]	288164	1			T2	28		T3	1453		T4	1647
valid_sources[0x4c]	288308	1			T3	1391		T4	2041		T12	1789
valid_sources[0x4d]	294086	1			T2	38		T3	1511		T4	1959
valid_sources[0x4e]	286837	1			T3	1490		T4	1586		T12	1818
valid_sources[0x4f]	283376	1			T3	1449		T4	1811		T12	1912
valid_sources[0x50]	288175	1			T3	1376		T4	1612		T12	1814
valid_sources[0x51]	306285	1			T3	1492		T4	1404		T12	1831
valid_sources[0x52]	284610	1			T3	1476		T4	1608		T12	1925
valid_sources[0x53]	313028	1			T2	47		T3	1478		T4	1891
valid_sources[0x54]	297134	1			T2	173		T3	1487		T4	1631
valid_sources[0x55]	724209	1			T3	1515		T4	1442		T12	1830
valid_sources[0x56]	293813	1			T3	1387		T4	2109		T12	1835
valid_sources[0x57]	278969	1			T2	4		T3	1461		T4	2061
valid_sources[0x58]	287171	1			T3	1467		T4	2014		T12	1940
valid_sources[0x59]	290776	1			T3	1474		T4	2011		T12	1988
valid_sources[0x5a]	285945	1			T3	1479		T4	2021		T12	1863
valid_sources[0x5b]	279918	1			T2	135		T3	1436		T4	1536
valid_sources[0x5c]	279692	1			T2	209		T3	1535		T4	1971
valid_sources[0x5d]	282392	1			T3	1464		T4	1703		T12	1879
valid_sources[0x5e]	283157	1			T3	1540		T4	1667		T12	1908
valid_sources[0x5f]	280465	1			T3	1533		T4	1920		T12	1738
valid_sources[0x60]	287015	1			T3	1419		T4	1532		T12	1920
valid_sources[0x61]	287799	1			T3	1488		T4	1418		T12	1843
valid_sources[0x62]	521150	1			T2	42		T3	1464		T4	1793
valid_sources[0x63]	289286	1			T3	1393		T4	1956		T12	1902
valid_sources[0x64]	292835	1			T3	1462		T4	1420		T12	1893
valid_sources[0x65]	291414	1			T3	1413		T4	1882		T12	1918
valid_sources[0x66]	292686	1			T3	1540		T4	1793		T12	1912
valid_sources[0x67]	285851	1			T3	1387		T4	1836		T12	1908
valid_sources[0x68]	283740	1			T2	29		T3	1451		T4	1855
valid_sources[0x69]	277416	1			T3	1439		T4	1467		T12	1856
valid_sources[0x6a]	306694	1			T2	159		T3	1444		T4	2116
valid_sources[0x6b]	337854	1			T3	1445		T4	1405		T12	1781
valid_sources[0x6c]	286594	1			T3	1431		T4	1839		T12	1846
valid_sources[0x6d]	285928	1			T3	1467		T4	1530		T12	1915
valid_sources[0x6e]	290319	1			T2	2		T3	1493		T4	1983
valid_sources[0x6f]	294829	1			T3	1466		T4	1778		T12	1977
valid_sources[0x70]	297117	1			T3	1446		T4	1709		T12	1877
valid_sources[0x71]	282386	1			T3	1468		T4	1922		T12	1873
valid_sources[0x72]	326134	1			T3	1453		T4	1717		T12	1822
valid_sources[0x73]	282346	1			T3	1472		T4	1901		T12	1923
valid_sources[0x74]	291127	1			T3	1379		T4	1924		T12	1910
valid_sources[0x75]	288968	1			T2	68		T3	1425		T4	1721
valid_sources[0x76]	281616	1			T3	1435		T4	1776		T12	1812
valid_sources[0x77]	288988	1			T3	1418		T4	1507		T12	1934
valid_sources[0x78]	278740	1			T3	1484		T4	1498		T12	1923
valid_sources[0x79]	292767	1			T3	1400		T4	1799		T12	1850
valid_sources[0x7a]	291137	1			T3	1483		T4	1886		T12	1959
valid_sources[0x7b]	722258	1			T3	1531		T4	1723		T12	1889
valid_sources[0x7c]	288626	1			T3	1512		T4	1609		T12	1910
valid_sources[0x7d]	702331	1			T2	76		T3	1526		T4	1575
valid_sources[0x7e]	283310	1			T3	1492		T4	1983		T12	1962
valid_sources[0x7f]	281803	1			T3	1444		T4	1588		T12	1929
valid_sources[0x80]	726607	1			T3	1398		T4	1455		T12	1813

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6746559

1

T1

25699

T2

402

T3

23093

values[0x0]

all_enables

biggest_size

14325149

1

T1

66345

T2

1102

T3

60646

values[0x1]

all_enables

biggest_size

8300627

1

T1

37843

T2

564

T3

34217