Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T199,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16358	0	0
DisabledNoTrigBkwd_A	2147483647	766666	0	0
DisabledNoTrigFwd_A	2147483647	1434382748	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16358	0	0
T6	817532	0	0	0
T7	429130	0	0	0
T8	559606	0	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T16	433332	0	0	0
T41	1089	387	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0
T49	49085	0	0	0
T123	22729	0	0	0
T127	12258	0	0	0
T128	96661	0	0	0
T199	2111	843	0	0
T200	0	1080	0	0
T201	0	1363	0	0
T202	0	1292	0	0
T203	0	1224	0	0
T204	0	1293	0	0
T205	0	642	0	0
T206	3818	888	0	0
T207	0	279	0	0
T208	0	98	0	0
T209	0	228	0	0
T210	0	693	0	0
T211	0	459	0	0
T212	0	1131	0	0
T213	0	1612	0	0
T214	0	339	0	0
T215	0	328	0	0
T216	0	1856	0	0
T217	0	323	0	0
T218	14717	0	0	0
T219	90956	0	0	0
T220	3233	0	0	0
T221	37713	0	0	0
T222	3357	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	766666	0	0
T1	492906	1137	0	0
T2	253470	2	0	0
T3	1824064	5718	0	0
T4	560044	7664	0	0
T5	0	4629	0	0
T6	0	9	0	0
T9	17128	0	0	0
T12	1626944	4282	0	0
T13	116244	85	0	0
T16	0	5801	0	0
T17	526156	3	0	0
T18	337916	0	0	0
T19	92824	0	0	0
T20	316876	0	0	0
T23	0	39	0	0
T40	0	94	0	0
T41	0	8	0	0
T43	0	31	0	0
T45	37798	50	0	0
T46	0	722	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1434382748	0	0
T1	657208	340793	0	0
T2	337960	112363	0	0
T3	1824064	488713	0	0
T4	560044	2032653	0	0
T12	1626944	1638696	0	0
T13	116244	87609	0	0
T17	526156	397636	0	0
T18	337916	120703	0	0
T19	92824	69991	0	0
T20	316876	116751	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T201,T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	633039078	8008	0	0
DisabledNoTrigBkwd_A	633039078	234327	0	0
DisabledNoTrigFwd_A	633039078	326808553	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	8008	0	0
T6	817532	0	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T16	433332	0	0	0
T41	1089	387	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0
T127	12258	0	0	0
T128	96661	0	0	0
T201	0	1363	0	0
T202	0	1292	0	0
T204	0	1293	0	0
T207	0	279	0	0
T212	0	1131	0	0
T213	0	1612	0	0
T215	0	328	0	0
T217	0	323	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	234327	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2188	0	0
T4	140011	4878	0	0
T5	0	3595	0	0
T12	406736	1740	0	0
T13	29061	85	0	0
T17	131539	3	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	94	0	0
T41	0	8	0	0
T45	0	21	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	326808553	0	0
T1	164302	163651	0	0
T2	84490	26253	0	0
T3	456016	13600	0	0
T4	140011	724583	0	0
T12	406736	370728	0	0
T13	29061	2355	0	0
T17	131539	3253	0	0
T18	84479	14011	0	0
T19	23206	23132	0	0
T20	79219	27841	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T205,T208
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	633039078	2504	0	0
DisabledNoTrigBkwd_A	633039078	156013	0	0
DisabledNoTrigFwd_A	633039078	374394707	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	2504	0	0
T7	429130	0	0	0
T8	559606	0	0	0
T49	49085	0	0	0
T123	22729	0	0	0
T199	2111	843	0	0
T205	0	642	0	0
T208	0	98	0	0
T209	0	228	0	0
T210	0	693	0	0
T218	14717	0	0	0
T219	90956	0	0	0
T220	3233	0	0	0
T221	37713	0	0	0
T222	3357	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	156013	0	0
T1	164302	739	0	0
T2	84490	0	0	0
T3	456016	1376	0	0
T4	140011	536	0	0
T5	0	503	0	0
T6	0	6	0	0
T12	406736	30	0	0
T13	29061	0	0	0
T16	0	2243	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	23	0	0
T45	0	21	0	0
T46	0	25	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	374394707	0	0
T1	164302	1956	0	0
T2	84490	8326	0	0
T3	456016	11347	0	0
T4	140011	887732	0	0
T12	406736	394931	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	44745	0	0
T19	23206	23132	0	0
T20	79219	29488	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T216
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	633039078	2744	0	0
DisabledNoTrigBkwd_A	633039078	187139	0	0
DisabledNoTrigFwd_A	633039078	372682463	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	2744	0	0
T98	51557	0	0	0
T104	57420	0	0	0
T206	3818	888	0	0
T216	0	1856	0	0
T223	89319	0	0	0
T224	202885	0	0	0
T225	376176	0	0	0
T226	820996	0	0	0
T227	537488	0	0	0
T228	422492	0	0	0
T229	101407	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	187139	0	0
T3	456016	7	0	0
T4	140011	332	0	0
T5	0	91	0	0
T6	0	3	0	0
T9	17128	0	0	0
T12	406736	158	0	0
T13	29061	0	0	0
T16	0	1711	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T23	0	39	0	0
T43	0	6	0	0
T45	37798	5	0	0
T46	0	87	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	372682463	0	0
T1	164302	164297	0	0
T2	84490	64040	0	0
T3	456016	453918	0	0
T4	140011	103061	0	0
T12	406736	376434	0	0
T13	29061	27242	0	0
T17	131539	131461	0	0
T18	84479	17920	0	0
T19	23206	2263	0	0
T20	79219	18757	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T203,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	633039078	3102	0	0
DisabledNoTrigBkwd_A	633039078	189187	0	0
DisabledNoTrigFwd_A	633039078	360497025	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	3102	0	0
T56	321506	0	0	0
T57	66277	0	0	0
T200	4449	1080	0	0
T203	0	1224	0	0
T211	0	459	0	0
T214	0	339	0	0
T230	27985	0	0	0
T231	636669	0	0	0
T232	183872	0	0	0
T233	452938	0	0	0
T234	92229	0	0	0
T235	50573	0	0	0
T236	10874	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	189187	0	0
T1	164302	397	0	0
T2	84490	2	0	0
T3	456016	2147	0	0
T4	140011	1918	0	0
T5	0	440	0	0
T12	406736	2354	0	0
T13	29061	0	0	0
T16	0	1847	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	2	0	0
T45	0	3	0	0
T46	0	610	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	360497025	0	0
T1	164302	10889	0	0
T2	84490	13744	0	0
T3	456016	9848	0	0
T4	140011	317277	0	0
T12	406736	496603	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	44027	0	0
T19	23206	21464	0	0
T20	79219	40665	0	0